US20150097273A1 - Method and structure of forming backside through silicon via connections - Google Patents
Method and structure of forming backside through silicon via connections Download PDFInfo
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- US20150097273A1 US20150097273A1 US14/569,844 US201414569844A US2015097273A1 US 20150097273 A1 US20150097273 A1 US 20150097273A1 US 201414569844 A US201414569844 A US 201414569844A US 2015097273 A1 US2015097273 A1 US 2015097273A1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 14/153,145, filed on Jan. 13, 2014, which is a divisional of U.S. patent application Ser. No. 13/562,927, filed on Jul. 31, 2012. Each patent application identified above is incorporated here by reference in its entirety to provide continuity of disclosure.
- The present invention generally relates to microelectronic structures, and more particularly to through silicon vias (TSVs), and even more preferably to the formation of TSVs connected to conducting structures.
- In the past, microelectronic devices, including integrated circuits (ICs), have increased performance by shrinking device features, thereby creating a higher density of circuits on a substrate. To continue the quest for increased performance, in additional the described two-dimensional (2D) shrinking, manufactures are stacking substrates to gain density in a third dimension (i.e. 3D-ICs). To enable the 3D efforts, TSVs are used to connect a first substrate to bond pads, interposers, redistribution layers, a second substrate, or other conductive features.
- TSVs extend from within an integrated circuit built on/in a first substrate to the backside of the first substrate. Initially, the TSVs end within the substrate. The substrate is thinned to expose the TSVs so they may subsequently be connected to the bond pads, interposer, redistribution layer, second substrate or the like. However, during the thinning/exposure process(es) the substrate may form a fissure or break. This is particularly true if the TSVs are different heights. And even if the substrate is not damaged, the current process and resulting structure are prone to shorting or leakage.
- Therefore, a robust process is needed to accommodate TSVs of varying heights. This invention provides a novel process and resulting structure to accommodate TSVs of varying heights and is also applicable to TSVs having uniform heights.
- The general principal of the present invention is a method, and the resulting structure, to make a connection between one or more conductors and vias. The method is particularly applicable to through silicon vias having different heights.
- The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, preferably including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening.
- The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.
- One aspect of the invention is a structure which includes a substrate having a backside; a first through silicon via having sides; a bottom surface; and a first height protruding from the backside of the substrate. The structure further includes a first conductor facing the backside of the substrate and in electrical contact with the first silicon via. In the structure, a first via liner encapsulates the sides and the bottom surface of the first through silicon via.
- A further aspect of the invention is a structure which includes a conductor having a conductor fill material and having a conductor liner covering at least one side of the conductor. The structure also includes a via having a via fill material and having a via liner covering at least one side of the via. In the structure, the at least one side of the via covered by the via liner is facing and in direct contact with the at least one side of the conductor covered by the wiring liner.
- Another aspect of the invention is a method of forming an integrated circuit substrate connected to a conductor, the method includes providing a substrate having a first through silicon via within the substrate wherein the substrate has a backside; exposing, through the backside of the substrate, an end of the first through silicon via; forming an insulator over the backside of the substrate and the end of the first through silicon via; forming an opening in the insulator over the end of the first through silicon via; and forming a conductor in the opening.
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FIG. 1 illustrates a flow chart for a method of making the conductor/via structure according to an embodiment of the present invention. -
FIG. 2 illustrates an embodiment of an integrated circuit having TSVs of different heights according to a step in the method of the present invention; -
FIG. 3 illustrates an embodiment of an integrated circuit after thinning the backside of the substrate to form protruding TSVs according to an embodiment of the present invention; -
FIG. 4 illustrates an embodiment of an integrated circuit after forming a planarized insulating layer according to an embodiment of the present invention; -
FIG. 5 illustrates an embodiment of an integrated circuit after etching to reveal TSVs according to the embodiment of the present invention; -
FIG. 6 illustrates forming a planarized conductor in electrical contact with the TSVs according to an embodiment of the present invention; -
FIG. 7 illustrates an enlarged view of the conductor making electrical contact with a TSV according to an embodiment of the present invention; and -
FIG. 8 illustrates the film stack along line A-A′ ofFIG. 7 according to an embodiment of the present invention. - Other objects, aspects and advantages of the invention will become obvious in combination with the description of accompanying drawings, wherein the same number represents the same or similar parts in all figures.
- Embodiments of methods of making a conductor in contact with a through silicon via of the present invention are described in conjunction with
FIGS. 1-6 . Various embodiments of the structure of the present invention are described in conjunction withFIGS. 6-8 . -
FIG. 1 illustrates aflow chart 10 of the steps of a method to create a conductor in contact with a through silicon via or via(s). The method starts atstep 20 by providing an integrated circuit (IC) having one or more through silicon vias (TSV) within a substrate. Next, step 30 thins the substrate so that the TSVs are exposed, and preferably protruding, from the backside of the substrate. Instep 40, an insulator stack is formed on the backside of the substrate and over the exposed TSVs. The insulator stack is planarized. Instep 50, the insulator stack is patterned an etch to form and opening which reveals the TSV(s). Finally, instep 60, a conductor is formed in the opening and in contact with the TSV(s). The steps are discussed in more detail in the following paragraphs. -
FIG. 2 illustrates a starting point of the method: providing an integrated circuit (IC) 100. InFIG. 2 , the IC is shown upside down, such that the bottom the IC having thesubstrate 110 is at the top of the page, and the top of the IC having theinterconnect levels 120 is at the bottom of the page.FIG. 2 also shows an optionalglass handling layer 130 andadhesive layer 135. Those skilled in the art realize that other layers of features could be in addition to or in lieu of the glass handling layer. - Still referring to
FIG. 2 , thesubstrate 110 is preferably a semiconductor substrate and can include semiconductor on insulator substrates. In a preferred embodiment the semiconductor is silicon. The substrate has a back-side 112 and a front-side 114. The transistors of the IC are in and/or on the front-side 114 of thesubstrate 110, but our not shown inFIG. 2 . The transistors are in electrical communication with theinterconnects levels 120 of the IC. - The
interconnect levels 120 comprisedielectrics 124 andmetals 122 levels. Preferably, one or more of thedielectrics 124 of theinterconnect levels 120 comprises a low k dielectric. Low k dielectrics include dielectrics having a dielectric constant less than 3.9, preferably less than 3.2, and more preferably 2.2 or less. Low k dielectrics include, but are note limited to, halogen doped silicon oxides, carbon doped silicon oxides, and porous silicon carbon doped oxides. Preferably, themetal 122 levels comprise copper. One or more of themetal 122 levels of theinterconnect 120 are connected to one or more through silicon vias (TSVs) 90. InFIG. 2 , the TSVs are connects to the lowest or first metal level, but a TSV could be connected to other metal levels, and each TSV could be connected to the same or different metal levels. - Continuing with
FIG. 2 , three TSVs are shown. Each TSV has afill material 92, a vialiner 94 and a viainsulator 96. Preferably, the viafill material 92 is a conductor and in particular, comprises copper. The vialiner 94 is preferably a conductive material, it may also optionally function as a diffusion barrier. In a preferred embodiment, the vialiner 94 is a dual layer of Ta and TaN with the Ta being between the copper and the TaN. The viainsulator 96 electrically isolates theTSV 90 from thesubstrate 110. In a preferred embodiment the via insulator includes a silicon oxide. - Still referring to
FIG. 2 , theTSVs 90 are embedded in thesubstrate 110. Each TSV has a height measured from the top 114 of the substrate to the bottom surface of the via defined by the viafill 92/vialiner 94 interface.FIG. 2 shows an example in which one of the vias has a first height h1 whereas another via has a second height h2 which is different from the first height. The difference in TSV height is designated byreference numeral 98 inFIG. 2 and can be from about 0.5 micron to about 10 microns and ranges therebetween. The height difference can be intentional or more likely is a result of process variation while etching to form theTSVs 90 in thesubstrate 110. - Referring to
FIG. 3 , thesubstrate 110 has been thinned such that thebackside 112 of thesubstrate 110 is below the bottom surface of theTSVs 90. Notice that theheight difference 98, if any, of the TSVs remains intact after thesubstrate 110 thinning. Thesubstrate 110 thinning process is a combination of grinding/polishing, cleaning and reactive ion etching (RIE). The TSVs 90 now protrude from the back-side 112 of the substrate 110 a distance, d. Note, for the TSV having the lesser height, h1, it's distance, d1, from the backs-side 112 of thesubstrate 110 is lesser than the distance, d2, protruded by the taller TSV having height h2. A typical protruding distance, d, can be from about 0.5 micron to about 10 microns and ranges there between. - Referring to
FIG. 4 , an insulator stack comprising anetch stop layer 88 andinsulator layer 86 is deposited. Note that theetch stop layer 88 substantially conforms with the protrudingTSVs 90 while theinsulator layer 86 fills the area between the protrudingTSVs 90. Theinsulator layer 86 has a thickness such that is completely covers all of theTSVs 90 protruding above the back-side 112 of thesubstrate 110, as illustrated inFIG. 4 . Theetch stop layer 88 is a nitrogen containing dielectric layer. In a preferred embodiment theetch stop layer 88 is silicon nitride. Theetch stop layer 88 may include multiple layers of films of the same or different type. Preferably theetch stop layer 88 is from about 500 A to about 1 um thick and ranges therebetween. Theinsulator layer 86 can be any dielectric layer that etches more rapidly than theetch stop layer 88. In a preferred embodiment theinsulator layer 86 is silicon dioxide. Theinsulator layer 86 may include multiple layers of films of the same or different type. Preferably theinsulator layer 86 is from about 5 um to about 20 um thick and ranges therebetween. InFIG. 4 , the insulator stack has been planarized either by chemical mechanical polishing or an etch back. - Referring to
FIG. 5 , with a planarized surface in place, the lithography and etching to form openings in theinsulator layer 86 can progress. Here,openings 87 formed in the insulator stack reveal the vialiner 94, but leave the vialiner 94 in place over the bottom surface of the via 90. Theheight 85 of the openings is substantially the same regardless of TSV heights (h1 and h2) and TSV protrusion distance (d1 or d2) from the thinned substrate back-side 112. Thus, as is shown in the TSV on the left ofFIG. 5 , some TSVs can be just revealed by the opening, while other TSVs, on the right ofFIG. 5 , also exposes the part of the sides of the TSVs. - Referring to
FIG. 6 , theopenings 87 are filled and co-planarized to form aconductor 80. The conductor includes aconductor liner 89 and aconductor fill 82. In a preferred embodiment theconductor liner 89 is TaN/Ta and the conductor fill 82 contains copper. However, other combinations are possible. WhileFIG. 6 only shows asingle conductor 80 layer, other conductor layers can be built aboveconductor 80. In one embodiment theconductor 80 is a redistribution line. In another embodiment theconductor 80 can be, by way of example and not limitation, a capture pad for packaging interconnect (i.e. aC4 ball or wirebond). -
FIG. 6 shows an embodiment of a final structure of the present invention. Unique features of the final structure include that theTSVs 90 retain theirheight difference 98 after formation of theconductor 80. As such, the TSVs of different heights also retain their different distances from the back-side 112 ofsubstrate 110 to the bottom surface (interface between viafill 92 and via liner 94). Another unique feature is that there is a double liner where theconductor 80 and theTSV 90 meet. The double liner feature can be seen more clearly inFIG. 7 . - Referring to
FIG. 7 , an enlargement of a portion ofFIG. 6 is shown. Here, it can be clearly sent that the bottom surface of theTSV 90 retains it vialiner 94 and that it is in contact with theconductor liner 89. The points A-A′ ofFIG. 7 are further enlarged inFIG. 8 showing the preferred embodiment of the double liner. - Referring to
FIG. 8 , on the left hand side of are theconductor 80, conductor fill 82,conductor liner 89, vialiner 94 and viafill 92 as depicted inFIG. 7 . On the right hand side ofFIG. 8 , is the preferred embodiment wherein the conductor fill 82 contains copper, theconductor liner 89 is Ta film on at TaN film, the vialiner 94 is in this inverted view, a TaN film on a Ta film, and the via fill 92 contains copper. The advantage of a double line layer is that a diffusion barrier remains in place throughout all processing; therefore, the substrate is never exposed to a highly diffusive metal, such as copper. - Other advantages of the present invention include that the method does not require any polishing of the TSVs which means there is no smearing of the via fill material. Instead, the TSVs remain encapsulated by the via liner. Furthermore, by not polishing the TSVs cracking of the substrate is minimized, if not eliminated completely. A further advantage is that multiple redistribution levels are enabled by planarized conductor. Conductors, such as redistribution layers (RDL) Yet another advantage of the present invention is that incoming substrates with varying TSV heights can be successfully processed. Finally, while the present invention is explained in conjunction with the preferred embodiment of copper TSVs, it can work equally well with other conjunction with other TSV materials, such as, but not limited to tungsten and it's liners (Ti/TiN).
- While the present invention has been described with reference to what are presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadcast interpretation so as to encompass all such modifications and equivalent structures and functions.
Claims (20)
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US14/569,844 US20150097273A1 (en) | 2012-07-31 | 2014-12-15 | Method and structure of forming backside through silicon via connections |
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US13/562,927 US8709936B2 (en) | 2012-07-31 | 2012-07-31 | Method and structure of forming backside through silicon via connections |
US14/153,145 US8970011B2 (en) | 2012-07-31 | 2014-01-13 | Method and structure of forming backside through silicon via connections |
US14/569,844 US20150097273A1 (en) | 2012-07-31 | 2014-12-15 | Method and structure of forming backside through silicon via connections |
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US14/153,145 Active US8970011B2 (en) | 2012-07-31 | 2014-01-13 | Method and structure of forming backside through silicon via connections |
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US8940637B2 (en) * | 2012-07-05 | 2015-01-27 | Globalfoundries Singapore Pte. Ltd. | Method for forming through silicon via with wafer backside protection |
US8709936B2 (en) * | 2012-07-31 | 2014-04-29 | International Business Machines Corporation | Method and structure of forming backside through silicon via connections |
KR20140073163A (en) * | 2012-12-06 | 2014-06-16 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
US9627250B2 (en) * | 2013-03-12 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for back end of line semiconductor device processing |
US20150048496A1 (en) * | 2013-08-13 | 2015-02-19 | Macrotech Technology Inc. | Fabrication process and structure to form bumps aligned on tsv on chip backside |
US9443764B2 (en) * | 2013-10-11 | 2016-09-13 | GlobalFoundries, Inc. | Method of eliminating poor reveal of through silicon vias |
US9786580B2 (en) * | 2013-11-15 | 2017-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-alignment for redistribution layer |
KR20150073473A (en) * | 2013-12-23 | 2015-07-01 | 에스케이하이닉스 주식회사 | Semiconductor device and method for manufacturing the same |
KR102177702B1 (en) | 2014-02-03 | 2020-11-11 | 삼성전자주식회사 | Via Structures and Semiconductor Devices Having a Via plug |
US9472518B2 (en) * | 2014-04-04 | 2016-10-18 | Micron Technology, Inc. | Semiconductor structures including carrier wafers and methods of using such semiconductor structures |
US9831281B2 (en) | 2015-05-01 | 2017-11-28 | Sensors Unlimited, Inc. | Electrical interconnects for photodiode arrays and readout interface circuits in focal plane array assemblies |
US9837309B2 (en) | 2015-11-19 | 2017-12-05 | International Business Machines Corporation | Semiconductor via structure with lower electrical resistance |
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Also Published As
Publication number | Publication date |
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US8709936B2 (en) | 2014-04-29 |
US20140124954A1 (en) | 2014-05-08 |
US8970011B2 (en) | 2015-03-03 |
US20140035109A1 (en) | 2014-02-06 |
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