WO2014015820A1 - 一种mos器件的钝化层形成方法以及一种mos器件 - Google Patents

一种mos器件的钝化层形成方法以及一种mos器件 Download PDF

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WO2014015820A1
WO2014015820A1 PCT/CN2013/080149 CN2013080149W WO2014015820A1 WO 2014015820 A1 WO2014015820 A1 WO 2014015820A1 CN 2013080149 W CN2013080149 W CN 2013080149W WO 2014015820 A1 WO2014015820 A1 WO 2014015820A1
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teos
psg
thickness
mos device
forming
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PCT/CN2013/080149
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English (en)
French (fr)
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王者伟
陈雪磊
刘斌斌
高留春
赵宏星
黄国民
蒋龙
焦骥斌
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无锡华润上华科技有限公司
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Priority to US14/412,445 priority Critical patent/US9559032B2/en
Priority to EP13822224.5A priority patent/EP2879172A4/en
Publication of WO2014015820A1 publication Critical patent/WO2014015820A1/zh

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    • H01L23/3157—Partial encapsulation or coating
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Definitions

  • the invention belongs to the field of semiconductor device manufacturing, and in particular to a method for forming a passivation layer of a MOS device and an MOS device. Background technique
  • the DMOS product includes a substrate 1, a dielectric 2, a metal 3, and a passivation layer 4.
  • the passivation layer 4 is a 10000A silicon nitride layer.
  • high-voltage DMOS products require HTRB testing (high-temperature/reverse high-voltage reliability testing) and HTGB testing (high-temperature high-voltage (gate) reliability testing), which vary in their requirements.
  • Some low-end products only require 168 hours of testing, while some high-end products require 1,000 hours of testing.
  • the present invention needs to provide a novel passivation layer forming method and MOS device to improve the passivation layer cracking problem.
  • the present invention provides a method of forming a passivation layer of a MOS device, the method comprising: forming a substrate;
  • a nitrogen silicon compound is formed on the PSG.
  • the thickness of the TEOS is 9000A-11000A
  • the thickness of the PSG is 2700A-3300A
  • the nitrogen silicon compound may be SiON
  • the thickness of the SiON is 2700A-3300A
  • the nitrogen silicon compound may also be SiN.
  • the thickness of the TEOS is 10000A
  • the thickness of the PSG is 3000A
  • the thickness of the SiON is 300 ⁇ .
  • TEOS is formed by chemical vapor deposition
  • PSG SiON or TEOS
  • PSG SiN.
  • the MOS device is a CMOS device or a DMOS device.
  • the present invention also provides a MOS device including a substrate, a dielectric formed on a portion of the substrate, a metal formed on the dielectric and the substrate, and a passivation layer formed on the metal, wherein the passivation Layers include:
  • a nitrogen silicon compound formed on the PSG is A nitrogen silicon compound formed on the PSG.
  • the thickness of the TEOS is
  • the thickness of the PSG is 2700A-3300A
  • the nitrogen silicon compound may be SiON
  • the thickness of the SiON is 2700A-3300A
  • the nitrogen silicon compound may also be SiN.
  • the TEOS has a thickness of 10000 A
  • the PSG has a thickness of 3000 A
  • the SiON has a thickness of 300 ⁇ .
  • TEOS, PSG, SiON or TEOS, PSG, SiN are formed by chemical vapor deposition.
  • the MOS device is a CMOS device or a DMOS device.
  • the stress of the top silicon oxynitride is less than that of the original silicon nitride, thereby effectively improving the cracking of the passivation layer.
  • FIG. 1 is a schematic structural view of a DMOS product according to the prior art
  • FIG. 2 is a method of forming a passivation layer of a MOS device in accordance with an exemplary embodiment of the present invention
  • FIG. 3 is a schematic structural view of a MOS device in accordance with an exemplary embodiment of the present invention. detailed description
  • the method includes the following steps:
  • the substrate may be, for example, ⁇ 100 crystal orientation> and a single crystal silicon having a resistance of 15 to 25 ohms.
  • the medium can be, for example, an oxide layer, such as a silicon oxide layer.
  • S3 Patterning the medium to expose a portion of the substrate.
  • the metal can be, for example, aluminum.
  • the thickness of the TEOS is from 9000A to 11000A. More preferably, the TEOS has a thickness of 1000 ⁇ .
  • the PSG has a thickness of 2700A-3300A. More preferably, the thickness of the PSG is 300 ⁇ ⁇ .
  • the thickness of the SiON is 3000A. More preferably, the SiON has a thickness of 3000A. In addition, SiON can be replaced with SiN.
  • TEOS, PSG, SiON are formed by chemical vapor deposition.
  • the above MOS device is a CMOS device or a DMOS device.
  • the MOS device includes a substrate 1, a medium formed on a portion of the substrate. 2.
  • Phosphosilicate glass PSG 42 formed on TEOS 41;
  • the thickness of the TEOS 41 is 9000A-11000A
  • the thickness of the PSG 42 is 9000A-11000A
  • SiON 43 has a thickness of 270 ⁇ -330 ⁇ .
  • the thickness of TEOS 41 10000A, PSG 42 of 3000A thickness, the thickness of SiON 43 is 3000A o
  • TEOS 41, PSG 42, SiON 43 are formed by chemical vapor deposition.
  • the MOS device described above may be a CMOS device or a DMOS device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

提供了一种MOS器件的钝化层（4'）形成方法以及一种MOS器件。所述MOS器件的钝化层（4'）形成方法包括：形成衬底（1）；在衬底（1）上形成介质（2）；图案化介质（2）以露出部分衬底；在露出的衬底部分和介质（2）上形成金属（3）；在金属（3）上形成正硅酸乙酯TEOS（41）；在TEOS（41）上形成磷硅玻璃PSG（42）；以及在PSG（42）上形成氮氧化合物（43）。由此，可以改善钝化层（4'）开裂的问题。

Description

一种 MOS器件的钝化层形成方法以及一种 M0S器件 技术领域
本发明属于半导体器件制造领域，尤其涉及一种 M0S器件的钝化层 形成方法以及一种 M0S器件。 背景技术
如图 1所示，示出了现有技术的 DM0S产品的结构。 该 DM0S产品 包括衬底 1、 介质 2、 金属 3和钝化层 4。 其中该钝化层 4为 10000A的氮 化硅层。
通常，高压 DMOS产品需要做 HTRB测试（高温 /反向高压可靠性测 试）和 HTGB测试（高温高压（栅极）可靠性测试） ，因其应用不同， 其要求也不同。一些低端产品只要求通过 168小时的测试，而一些高端产 品则需要通过 1000小时的测试。 在实际生产中发现，很多产品在 500小 时以上的考核中，由于在进行盐酸浸泡（即针孔实验）后，有大量的铝被 侵蚀，钝化层 4存在开裂现象，从而很容易发生漏电问题。 发明内容
有鉴于此，本发明需要提供一种新的钝化层形成方法和 MOS器件， 以改善钝化层开裂问题。
本发明提供了一种 MOS器件的钝化层形成方法，所述方法包括： 形成衬底；
在衬底上形成介质；
图案化介质以露出部分衬底；
在露出的衬底部分和介质上形成金属；
在金属上形成正硅酸乙酯 TEOS；
在 TEOS上形成磷硅玻璃 PSG；以及
在 PSG上形成氮硅化合物。
优选地 ,在本发明的上述方法中，所述 TEOS的厚度为 9000A-11000A , 所述 PSG的厚度为 2700A-3300A ,所述氮硅化合物可为 SiON ,所述 SiON 的厚度为 2700A-3300A ,另外，所述氮硅化合物还可为 SiN。
优选地，在本发明的上述方法中，所述 TEOS的厚度为 10000A ,所 述 PSG的厚度为 3000A ,所述 SiON的厚度为 300θΑ。
优选地，在本发明的上述方法中，以化学气相淀积方式形成 TEOS、
PSG、 SiON或 TEOS、 PSG、 SiN。
优选地，在本发明的上述方法中，所述 MOS器件为 CMOS器件或 DMOS器件。
本发明还提供一种 MOS器件，所述 MOS器件包括衬底、 形成在部 分衬底上的介质、 形成在介质和衬底上的金属以及形成在金属上的钝化 层，其中所述钝化层包括：
形成在金属上的正硅酸乙酯 TEOS；
形成在 TEOS上的磷硅玻璃 PSG；以及
形成在 PSG上的氮硅化合物。
优选地， 在本发明的上述 MOS 器件中， 所述 TEOS 的厚度为
9000A-1 1000A ,所述 PSG的厚度为 2700A-3300A ,所述氮硅化合物可为 SiON ,所述 SiON的厚度为 2700A-3300A ,另外，所述氮硅化合物还可为 SiN。
优选地，在本发明的上述 MOS器件中，所述 TEOS的厚度为 10000A , 所述 PSG的厚度为 3000A ,所述 SiON的厚度为 300θΑ。
优选地，在本发明的上述 MOS 器件中，以化学气相淀积方式形成 TEOS、 PSG、 SiON或 TEOS、 PSG、 SiN。
优选地，在本发明的上述 MOS器件中，所述 MOS器件为 CMOS器 件或 DMOS器件。
利用本发明，由于底层的 TEOS和 PSG可以有效缓解顶层的应力， 同时顶层氮氧化硅的应力比原来的氮化硅应力小，从而有效改善钝化层开 裂问题。
利用本发明，可以有效降低产品报废率，提高生成效率。 附图说明
图 1为根据现有技术的 DMOS产品的结构示意图；
图 2为根据本发明的示意性实施例的 MOS器件的钝化层形成方法； 以及
图 3为根据本发明的示意性实施例的 MOS器件的结构示意图。 具体实施方式
下面将结合附图详细描述本发明的优选实施例，在附图中相同的参考 标号表示相同的元件。
图 2为根据本发明的示意性实施例的 MOS器件的钝化层形成方法。 如图所示，该方法包括以下步骤：
S1 :形成衬底。 衬底可以例如为<100晶向 > ,电阻 15〜25欧姆的单晶 硅。
S2:在衬底上形成介质。 介质可以例如为氧化层，例如为氧化硅层。 S3:图案化介质以露出部分衬底。
S4:在露出的衬底部分和介质上形成金属。 金属可以例如为铝。
S5:在金属上形成正硅酸乙酯 TEOS。 优选地， TEOS 的厚度为 9000A-11000A。 更优选地， TEOS的厚度为 1000θΑ。
S6:在 TEOS 上形成磷硅玻璃 PSG。 优选地， PSG 的厚度为 2700A-3300A。 更优选地， PSG的厚度为 300θΑ。
S7:在 PSG上形成氮硅化合物。优选地， SiON的厚度为 3000A。更优 选地， SiON的厚度为 3000A。 另外， SiON可用 SiN替换。
优选地，以化学气相淀积方式形成 TEOS、 PSG、 SiON。
优选地，上述 MOS器件为 CMOS器件或 DMOS器件。
图 3为根据本发明的示意性实施例的 MOS器件的结构示意图。 在形 成钝化层过程的氮氧化合物可为 SiON或 SiN等，下面实施例中氮氧化合 物仅以 SiON为例，如图所示， MOS器件包括衬底 1、 形成在部分衬底上 的介质 2、 形成在介质和衬底上的金属 3以及形成在金属上的钝化层 4' , 其中所述钝化层 4'包括： 形成在金属 3上的正硅酸乙酯 TEOS 41；
形成在 TEOS 41上的磷硅玻璃 PSG 42；以及
形成在 PSG 42上的氮氧化硅 SiON 43。
优选地， TEOS 41 的厚度为 9000A-11000A , PSG 42 的厚度为
2700A-3300A , SiON 43的厚度为 270θΑ-330θΑ。
更优选地，TEOS 41的厚度为 10000A ,PSG 42的厚度为 3000A ,SiON 43的厚度为 3000Ao
优选地，以化学气相淀积方式形成 TEOS 41、 PSG 42、 SiON43。 优选地，上述 MOS器件可以为 CMOS器件或 DMOS器件。
鉴于这些教导，熟悉本领域的技术人员将容易想到本发明的其它实施 例、 组合和修改。 因此，当结合上述说明和附图进行阅读时，本发明仅仅 由权利要求限定。

Claims

权利要求
1.一种 MOS器件的钝化层形成方法， 其特征在于， 所述方法包括： 形成衬底；
在衬底上形成介质；
图案化介质以露出部分衬底；
在露出的衬底部分和介质上形成金属；
在金属上形成正硅酸乙酯 TEOS;
在 TEOS上形成磷硅玻璃 PSG; 以及
在 PSG上形成氮氧化合物。
2. 如权利要求 1 所述的方法， 其特征在于， 所述 TEOS 的厚度为 9000A-11000A, 所述 PSG的厚度为 2700A-3300A, 所述氮硅化合物可为 SiON, 所述 SiON的厚度为 2700A-3300A, 另外， 所述氮硅化合物还可为 SiN。
3. 如权利要求 2 所述的方法， 其特征在于， 所述 TEOS 的厚度为 10000A, 所述 PSG的厚度为 3000A, 所述 SiON的厚度为 3000A。
4. 如权利要求 1 所述的方法， 其特征在于， 以化学气相淀积方式形 成 TEOS、 PSG, SiON或 TEOS、 PSG, SiN。
5. 如权利要求 1所述的方法， 其特征在于， 所述 MOS器件为 CMOS 器件或 DMOS器件。
6. 一种 MOS器件， 其特征在于， 所述 MOS器件包括衬底、 形成在 部分衬底上的介质、形成在介质和衬底上的金属以及形成在金属上的钝化 层， 其中所述钝化层包括：
形成在金属上的正硅酸乙酯 TEOS;
形成在 TEOS上的磷硅玻璃 PSG; 以及
7. 如权利要求 6所述的 MOS器件， 其特征在于， 所述 TEOS的厚度 为 9000A-11000A, 所述 PSG的厚度为 2700A-3300A, 所述氮硅化合物可 为 SiON, 所述 SiON的厚度为 2700A-3300A, 另外， 所述氮硅化合物还 可为 SiN。
8. 如权利要求 7所述的 MOS器件， 其特征在于， 所述 TEOS的厚度 为 10000A, 所述 PSG的厚度为 3000A, 所述 SiON的厚度为 3000A。
9. 如权利要求 6所述的 MOS器件， 其特征在于， 以化学气相淀积方 式形成 TEOS、 PSG, SiON或 TEOS、 PSG, SiN。
10. 如权利要求 6所述的 MOS器件， 其特征在于， 所述 MOS器件为 CMOS器件或 DMOS器件。
PCT/CN2013/080149 2012-07-26 2013-07-25 一种mos器件的钝化层形成方法以及一种mos器件 WO2014015820A1 (zh)

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