CN103578919A - 一种mos器件的钝化层形成方法以及一种mos器件 - Google Patents

一种mos器件的钝化层形成方法以及一种mos器件 Download PDF

Info

Publication number
CN103578919A
CN103578919A CN201210260811.6A CN201210260811A CN103578919A CN 103578919 A CN103578919 A CN 103578919A CN 201210260811 A CN201210260811 A CN 201210260811A CN 103578919 A CN103578919 A CN 103578919A
Authority
CN
China
Prior art keywords
psg
dusts
teos
thickness
mos device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201210260811.6A
Other languages
English (en)
Inventor
王者伟
陈雪磊
高留春
刘斌斌
赵宏星
黄国民
焦骥斌
蒋龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Corp
Original Assignee
CSMC Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Corp filed Critical CSMC Technologies Corp
Priority to CN201210260811.6A priority Critical patent/CN103578919A/zh
Priority to PCT/CN2013/080149 priority patent/WO2014015820A1/zh
Priority to US14/412,445 priority patent/US9559032B2/en
Priority to EP13822224.5A priority patent/EP2879172A4/en
Publication of CN103578919A publication Critical patent/CN103578919A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本发明提供一种MOS器件的钝化层形成方法以及一种MOS器件。所述MOS器件的钝化层形成方法包括:形成衬底;在衬底上形成介质;图案化介质以露出部分衬底;在露出的衬底部分和介质上形成金属;在金属上形成正硅酸乙酯TEOS;在TEOS上形成磷硅玻璃PSG;以及在PSG上形成氮氧化合物。利用本发明,可以改善钝化层开裂的问题。

Description

一种MOS器件的钝化层形成方法以及一种MOS器件
技术领域
本发明属于半导体器件制造领域,尤其涉及一种MOS器件的钝化层形成方法以及一种MOS器件。
背景技术
如图1所示,示出了现有技术的DMOS产品的结构。该DMOS产品包括衬底1、介质2、金属3和钝化层4。其中该钝化层4为10000埃的氮化硅层。
通常,高压DMOS产品需要做HTRB测试(高温/反向高压可靠性测试)和HTGB测试(高温高压(栅极)可靠性测试),因其应用不同,其要求也不同。一些低端产品只要求通过168小时的测试,而一些高端产品则需要通过1000小时的测试。在实际生产中发现,很多产品在500小时以上的考核中,由于在进行盐酸浸泡(即针孔实验)后,有大量的铝被侵蚀,钝化层4存在开裂现象,从而很容易发生漏电问题。
发明内容
有鉴于此,本发明需要提供一种新的钝化层形成方法和MOS器件,以改善钝化层开裂问题。
本发明提供了一种MOS器件的钝化层形成方法,所述方法包括:
形成衬底;
在衬底上形成介质;
图案化介质以露出部分衬底;
在露出的衬底部分和介质上形成金属;
在金属上形成正硅酸乙酯TEOS;
在TEOS上形成磷硅玻璃PSG;以及
在PSG上形成氮硅化合物。
优选地,在本发明的上述方法中,所述TEOS的厚度为9000埃-11000埃,所述PSG的厚度为2700埃-3300埃,所述氮硅化合物可为SiON,所述SiON的厚度为2700埃-3300埃,另外,所述氮硅化合物还可为SiN。
优选地,在本发明的上述方法中,所述TEOS的厚度为10000埃,所述PSG的厚度为3000埃,所述SiON的厚度为3000埃。
优选地,在本发明的上述方法中,以化学气相淀积方式形成TEOS、PSG、SiON或TEOS、PSG、SiN。
优选地,在本发明的上述方法中,所述MOS器件为CMOS器件或DMOS器件。
本发明还提供一种MOS器件,所述MOS器件包括衬底、形成在部分衬底上的介质、形成在介质和衬底上的金属以及形成在金属上的钝化层,其中所述钝化层包括:
形成在金属上的正硅酸乙酯TEOS;
形成在TEOS上的磷硅玻璃PSG;以及
形成在PSG上的氮硅化合物。
优选地,在本发明的上述MOS器件中,所述TEOS的厚度为9000埃-11000埃,所述PSG的厚度为2700埃-3300埃,所述氮硅化合物可为SiON,所述SiON的厚度为2700埃-3300埃,另外,所述氮硅化合物还可为SiN。
优选地,在本发明的上述MOS器件中,所述TEOS的厚度为10000埃,所述PSG的厚度为3000埃,所述SiON的厚度为3000埃。
优选地,在本发明的上述MOS器件中,以化学气相淀积方式形成TEOS、PSG、SiON或TEOS、PSG、SiN。
优选地,在本发明的上述MOS器件中,所述MOS器件为CMOS器件或DMOS器件。
利用本发明,由于底层的TEOS和PSG可以有效缓解顶层的应力,同时顶层氮氧化硅的应力比原来的氮化硅应力小,从而有效改善钝化层开裂问题。
利用本发明,可以有效降低产品报废率,提高生成效率。
附图说明
图1为根据现有技术的DMOS产品的结构示意图;
图2为根据本发明的示意性实施例的MOS器件的钝化层形成方法;以及
图3为根据本发明的示意性实施例的MOS器件的结构示意图。
具体实施方式
下面将结合附图详细描述本发明的优选实施例,在附图中相同的参考标号表示相同的元件。
图2为根据本发明的示意性实施例的MOS器件的钝化层形成方法。如图所示,该方法包括以下步骤:
S1:形成衬底。衬底可以例如为<100晶向>,电阻15~25欧姆的单晶硅。
S2:在衬底上形成介质。介质可以例如为氧化层,例如为氧化硅层。
S3:图案化介质以露出部分衬底。
S4:在露出的衬底部分和介质上形成金属。金属可以例如为铝。
S5:在金属上形成正硅酸乙酯TEOS。优选地,TEOS的厚度为9000埃-11000埃。更优选地,TEOS的厚度为10000埃。
S6:在TEOS上形成磷硅玻璃PSG。优选地,PSG的厚度为2700埃-3300埃。更优选地,PSG的厚度为3000埃。
S7:在PSG上形成氮硅化合物。优选地,SiON的厚度为3000埃。更优选地,SiON的厚度为3000埃。另外,SiON可用SiN替换。
优选地,以化学气相淀积方式形成TEOS、PSG、SiON。
优选地,上述MOS器件为CMOS器件或DMOS器件。
图3为根据本发明的示意性实施例的MOS器件的结构示意图。在形成钝化层过程的氮氧化合物可为SiON或SiN等,下面实施例中氮氧化合物仅以SiON为例,如图所示,MOS器件包括衬底1、形成在部分衬底上的介质2、形成在介质和衬底上的金属3以及形成在金属上的钝化层4’,其中所述钝化层4’包括:
形成在金属3上的正硅酸乙酯TEOS 41;
形成在TEOS 41上的磷硅玻璃PSG 42;以及
形成在PSG 42上的氮氧化硅SiON 43。
优选地,TEOS 41的厚度为9000埃-11000埃,PSG 42的厚度为2700埃-3300埃,SiON 43的厚度为2700埃-3300埃。
更优选地,TEOS 41的厚度为10000埃,PSG 42的厚度为3000埃,SiON 43的厚度为3000埃。
优选地,以化学气相淀积方式形成TEOS 41、PSG 42、SiON 43。
优选地,上述MOS器件可以为CMOS器件或DMOS器件。
鉴于这些教导,熟悉本领域的技术人员将容易想到本发明的其它实施例、组合和修改。因此,当结合上述说明和附图进行阅读时,本发明仅仅由权利要求限定。

Claims (10)

1.一种MOS器件的钝化层形成方法,其特征在于,所述方法包括:
形成衬底;
在衬底上形成介质;
图案化介质以露出部分衬底;
在露出的衬底部分和介质上形成金属;
在金属上形成正硅酸乙酯TEOS;
在TEOS上形成磷硅玻璃PSG;以及
在PSG上形成氮氧化合物。
2.如权利要求1所述的方法,其特征在于,所述TEOS的厚度为9000埃-11000埃,所述PSG的厚度为2700埃-3300埃,所述氮硅化合物可为SiON,所述SiON的厚度为2700埃-3300埃,另外,所述氮硅化合物还可为SiN。
3.如权利要求2所述的方法,其特征在于,所述TEOS的厚度为10000埃,所述PSG的厚度为3000埃,所述SiON的厚度为3000埃。
4.如权利要求1-3之一所述的方法,其特征在于,以化学气相淀积方式形成TEOS、PSG、SiON或TEOS、PSG、SiN。
5.如权利要求1-3之一所述的方法,其特征在于,所述MOS器件为CMOS器件或DMOS器件。
6.一种MOS器件,其特征在于,所述MOS器件包括衬底、形成在部分衬底上的介质、形成在介质和衬底上的金属以及形成在金属上的钝化层,其中所述钝化层包括:
形成在金属上的正硅酸乙酯TEOS;
形成在TEOS上的磷硅玻璃PSG;以及
形成在PSG上的氮硅化合物。
7.如权利要求6所述的MOS器件,其特征在于,所述TEOS的厚度为9000埃-11000埃,所述PSG的厚度为2700埃-3300埃,所述氮硅化合物可为SiON,所述SiON的厚度为2700埃-3300埃,另外,所述氮硅化合物还可为SiN。
8.如权利要求7所述的MOS器件,其特征在于,所述TEOS的厚度为10000埃,所述PSG的厚度为3000埃,所述SiON的厚度为3000埃。
9.如权利要求6-8之一所述的MOS器件,其特征在于,以化学气相淀积方式形成TEOS、PSG、SiON或TEOS、PSG、SiN。
10.如权利要求6-8之一所述的MOS器件,其特征在于,所述MOS器件为CMOS器件或DMOS器件。
CN201210260811.6A 2012-07-26 2012-07-26 一种mos器件的钝化层形成方法以及一种mos器件 Pending CN103578919A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201210260811.6A CN103578919A (zh) 2012-07-26 2012-07-26 一种mos器件的钝化层形成方法以及一种mos器件
PCT/CN2013/080149 WO2014015820A1 (zh) 2012-07-26 2013-07-25 一种mos器件的钝化层形成方法以及一种mos器件
US14/412,445 US9559032B2 (en) 2012-07-26 2013-07-25 Method for forming MOS device passivation layer and MOS device
EP13822224.5A EP2879172A4 (en) 2012-07-26 2013-07-25 METHOD FOR FORMING MOS DEVICE PASSIVATION LAYER AND MOS DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210260811.6A CN103578919A (zh) 2012-07-26 2012-07-26 一种mos器件的钝化层形成方法以及一种mos器件

Publications (1)

Publication Number Publication Date
CN103578919A true CN103578919A (zh) 2014-02-12

Family

ID=49996610

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210260811.6A Pending CN103578919A (zh) 2012-07-26 2012-07-26 一种mos器件的钝化层形成方法以及一种mos器件

Country Status (4)

Country Link
US (1) US9559032B2 (zh)
EP (1) EP2879172A4 (zh)
CN (1) CN103578919A (zh)
WO (1) WO2014015820A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1094847A (zh) * 1993-04-14 1994-11-09 松下电器产业株式会社 半导体器件及其制造方法
US5523595A (en) * 1990-08-21 1996-06-04 Ramtron International Corporation Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film
CN1302086A (zh) * 1999-12-30 2001-07-04 现代电子产业株式会社 具有电容器的半导体器件及其制造方法
US20020055214A1 (en) * 2000-11-09 2002-05-09 Trivedi Jigish D. Stacked local interconnect structure and method of fabricating same
US6867466B2 (en) * 2002-03-13 2005-03-15 Macronix International Co., Ltd. Memory device and method for forming a passivation layer thereon
CN101290912A (zh) * 2007-04-19 2008-10-22 松下电器产业株式会社 半导体装置及其制造方法
CN101330018A (zh) * 2007-06-21 2008-12-24 中芯国际集成电路制造(上海)有限公司 苯并环丁烯层沉积方法及凸点制作方法
CN101710580A (zh) * 2009-12-01 2010-05-19 杭州士兰集成电路有限公司 Bipolar电路的多层复合钝化层结构及其生成工艺方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0370178A (ja) * 1989-08-09 1991-03-26 Seiko Instr Inc 半導体装置
US5334554A (en) * 1992-01-24 1994-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Nitrogen plasma treatment to prevent field device leakage in VLSI processing
EP0627763B1 (en) * 1993-05-31 2004-12-15 STMicroelectronics S.r.l. Process for improving the adhesion between dielectric layers at their interface in semiconductor devices manufacture
US6127261A (en) * 1995-11-16 2000-10-03 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies
US6025279A (en) * 1998-05-29 2000-02-15 Taiwan Semiconductor Manufacturing Company Method of reducing nitride and oxide peeling after planarization using an anneal
US6087726A (en) * 1999-03-01 2000-07-11 Lsi Logic Corporation Metal interconnect stack for integrated circuit structure
US6300252B1 (en) * 1999-10-01 2001-10-09 Taiwan Semiconductor Manufacturing Company, Ltd Method for etching fuse windows in IC devices and devices made
US6709930B2 (en) * 2002-06-21 2004-03-23 Siliconix Incorporated Thicker oxide formation at the trench bottom by selective oxide deposition
US7109119B2 (en) * 2002-10-31 2006-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Scum solution for chemically amplified resist patterning in cu/low k dual damascene
US20060081965A1 (en) * 2004-10-15 2006-04-20 Ju-Ai Ruan Plasma treatment of an etch stop layer
KR20090044262A (ko) * 2007-10-31 2009-05-07 주식회사 동부하이텍 반도체 소자와 그의 제조방법
US9076798B2 (en) * 2009-05-11 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing structures for semiconductor substrates and methods of fabrication thereof
US8432038B2 (en) * 2009-06-12 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via structure and a process for forming the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523595A (en) * 1990-08-21 1996-06-04 Ramtron International Corporation Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film
CN1094847A (zh) * 1993-04-14 1994-11-09 松下电器产业株式会社 半导体器件及其制造方法
CN1302086A (zh) * 1999-12-30 2001-07-04 现代电子产业株式会社 具有电容器的半导体器件及其制造方法
US20020055214A1 (en) * 2000-11-09 2002-05-09 Trivedi Jigish D. Stacked local interconnect structure and method of fabricating same
US6867466B2 (en) * 2002-03-13 2005-03-15 Macronix International Co., Ltd. Memory device and method for forming a passivation layer thereon
CN101290912A (zh) * 2007-04-19 2008-10-22 松下电器产业株式会社 半导体装置及其制造方法
CN101330018A (zh) * 2007-06-21 2008-12-24 中芯国际集成电路制造(上海)有限公司 苯并环丁烯层沉积方法及凸点制作方法
CN101710580A (zh) * 2009-12-01 2010-05-19 杭州士兰集成电路有限公司 Bipolar电路的多层复合钝化层结构及其生成工艺方法

Also Published As

Publication number Publication date
US20150364397A1 (en) 2015-12-17
EP2879172A4 (en) 2016-03-02
US9559032B2 (en) 2017-01-31
EP2879172A1 (en) 2015-06-03
WO2014015820A1 (zh) 2014-01-30

Similar Documents

Publication Publication Date Title
CN102569238B (zh) 半导体装置及其制造方法
CN102280470B (zh) 半导体器件和半导体器件制造方法
US8853814B2 (en) Miniature thermoelectric energy harvester and fabrication method thereof
EP2048923A3 (en) Method of manufacturing silicon substrate with a conductive through-hole
CN205231039U (zh) 一种高耐压台面二极管芯片
CN103296190A (zh) 三维热电能量收集器及其制作方法
CN101281898A (zh) 栅介质层完整性的测试结构、其形成方法及其测试方法
CN110310997A (zh) 一种高电容密度的mis芯片电容
WO2011091959A3 (de) Verfahren zur lokalen hochdotierung und kontaktierung einer halbleiterstruktur, welche eine solarzelle oder eine vorstufe einer solarzelle ist
CN104485288A (zh) 一种超薄玻璃转接板的制作方法
CN103515417B (zh) 钝化结构及其形成方法
WO2020220665A1 (zh) 一种四颗二极管集成芯片的制造工艺
CN105304811A (zh) 具有斜面的衬底结构、磁阻传感器及其制作方法
CN103578919A (zh) 一种mos器件的钝化层形成方法以及一种mos器件
CN102169833A (zh) 一种低功耗二极管制造工艺
CN103822948A (zh) 半导体器件的测试方法
CN1964000A (zh) 一种去除硅片背面氮化硅的方法
CN108335988A (zh) 一种硅电容的制作方法
CN102637632B (zh) 一种薄膜晶体管阵列的制作方法和薄膜晶体管阵列
CN101752087B (zh) Pvdf有机聚合物薄膜电容器
CN205231072U (zh) 一种中低压台面二极管芯片
CN104952827A (zh) 一种焊盘结构及其制备方法
CN102818516A (zh) 耐高温硅应变计传感器芯片及其制作方法
CN106904839A (zh) 一种玻璃腐蚀的掩膜方法
CN209029385U (zh) 一种功率器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20140212

RJ01 Rejection of invention patent application after publication