201101424 六、發明說明： 【發明所屬之技術領域】 本發明是關於-種製作石夕貫通電極(thr〇ugh_siHc〇n喊 TSV)的方法’尤指—種於製作⑪貫通電極時同時維持層 電層厚度的製作方法。 ^ 【先前技術】 Ο 矽貝通電極(TSV)技術是一種新穎的半導體技術。矽貫通 電極技術主要在於解決晶片間互連的問題，屬於—種新的三 度空間立體封裝技術。#紅㈣貫通電極技術藉由三度空間 的堆疊、經由矽貫通電極創造出更符合輕、薄、短、小之市 場需求產品，提供微機電系統(MEMS)、光電及電子元件等 晶圓級封裝所需之封裝製程技術。 〇 ⑪貫通電極技術是在晶圓上以㈣或雷射的方式鑽孔， 再將V電材料如銅、多晶石夕、鶴等填入導孔(via)形成導電的 通道(即連接内、外部的接合線路）。最後賴晶圓或晶粒薄 化再加以堆豐、結合(bonding)，而成為三度空間的堆疊積體 "略(3D 1C)如此來，就可以去除打線連結(wire bonding) ^式。而改以蝕刻或雷射的方式鑽孔(Via)並導通電極，不僅 省去打線空間’也縮小了電路板的使用面積與封裝件的體 積由於採用石夕貫通電極技術的構震内部接合距離，即為薄 201101424 化後之晶圓或晶粒的厚度’相較於採取打線逹結的傳統堆疊 封裝，三度空間堆疊積體電路的内部連接路徑更短，相對可 使晶片間的傳輸速度更快、雜訊更小、效能更佳。尤其在中 央處裡器（CPU)與快取記憶體’以及記憶卡應用中的資料傳 、輸上，更能突顯矽貫通電極技術的短距離内部接合路徑所帶 來的效能優勢。此外，三度空間堆疊積體電路的封裝尺寸等 同於晶粒尺寸。在強調多功能、小尺寸的可攜式電子產品領 ^ 域，三度空間堆疊積體電路的小型化特性更是市場導入的首 要因素。 目前廣泛製作矽貫通電極的製程主要先於一半導體基底 表面完成所需的金氧半導體電晶體’例如一互補型金氧半導 體電晶體’然後形成貝穿層間介電層並連接金氧半導體電晶 體的接觸插塞。接著在層間介電層與半導體基底中作出填有 隔離用之介電層與導電用之銅金屬的矽貫通電極。在形成接 Ο觸插塞及矽貫通電極的過程當中需要多道化學機械研磨，每 一道化學機械研磨製程係用以％磨不同的材料。 需注思的疋，一般以化學機械研磨進行的研磨製程需倚 靠不同的移除率來將研磨製程停止於某個特定的材料層。由 於層間介電層與覆蓋於其上用來隔離矽貫通電極的介電層 都屬相同性質的介電材料，因此在以化學機械研磨製心別 去除這兩個材料層的時候容易因相同移除率而無法有效停 201101424 止研磨步驟。在此條件下，層間介電層的厚度將會變得難以 控制，且在大部分情況下容易流失過多的層間介電層而造成 層間介電層厚度不足的問題。 【發明内容】 因此本發明是揭露一種製作矽貫通電極的方法，以改良 目前製程中容易導致層間介電層過度流失的問題。 Ο 本發明較佳實施例是揭露一種製作矽貫通電極的方法， 包含有下列㈣H半導縣底；形歧少—金氧半導 體電晶體於該半導體基絲面；形成_介電層於該金氧半導 體電晶體上；於該介電層中形成連接該金氧半導體電晶體的 接觸插塞開Π;形成—第―導電層於該介電層上並填入該接 觸插塞開口中；進行—㈣製程，於該導電層、該介電層及 該半導體基底巾形成-㈣導孔m導電層於該穿 〇石夕導孔中並覆蓋部分該導電層表面；以及進行一平坦化製 程，以去除部分該第二導電層直到該第一導電層表面。 .?. ·. 【實施方式】 睛參照第1 @至第6圖，第1圖至第6圖為本發明較佳 實施例製作-石夕貫通電極之方法示意圖。如第i圖所示，首 先提供-半導體基底12，例如一由單晶石夕(monocrystalline silicon)、砷化鎵(ganium arsenide，GaAs)或其他習知技藝所 6 201101424 4 熟知之半導體材質所構成的基底。然後依據標準金氧半導體 電晶體製程於半導體基底12表®形成至少一金氧半導體電 晶體14，例如一 P型金氧半導體(PMOS)電晶體、N型金氧 半導體(NMOS)電晶體或互補型金氧半導體(CMOS)電晶 體，或其他各式半導體元件。其中金氧半導體電晶體14可 各具有閘極、侧壁子、輕#雜源極沒極、源極/沒極區域及石夕 化金屬層等標準電晶體結構，在此不另加贅述。 〇 〇 然後形成一厚度為數千埃如約3000埃的層間介電層16 並覆蓋整個金氧半導體電晶體14。層間介電層16較佳由四 乙基氧矽烷(tetraethylorthosilicate，TEOS)及磷矽玻璃 (ph〇Sph〇silicateglass，pSG)所構成的複合材料層所構成，但 不侷限於此。層間介電層16亦可為BpsG、低介電係數(l〇w_k) ^料所構成，且層間介電層16與金氧半導體電晶體14之間 可選擇性地置入應力材料如提供拉伸應力或伸張應力的氣 化石夕材料、_停止層域切材料、襯層如薄氧化層、或 上述者之組合。 接著進行-圖案轉移製程，如糾用—圖案 ®未不）當作遮罩於層間介電層16 ^ 面並二lit鎢所構成的導電材料在層間介電 半導體使填滿接觸洞18的導電材料連接金氧 電曰曰體14並於層間介電層16上形成一導電層如，如 7 201101424 » 第2圖所示。其中，在形成導電層20之前亦可先選擇性形 成一由鈕(Ta)、氮化钽(tantalum，TaN)、鈦(Ti)、氮化鈦(TiN) 或其組合所構成之黏著層（adhesive layer)。導電層20之導電 材料可為W以外的其他導電材料如鋁 '銅、或其合金。 如第3圖所示’隨後進行另一圖案轉移製程，例如形成 另一圖案化光阻層（圖未示）在導電層20表面，然後以此圖案 ^化光阻層當作遮罩進行單次或多次蝕刻製程，以於導電層 20、層間介電層16以及半導體基底丨2中形成一穿矽導孔22。 如第4圖所示，隨後形成一絕緣層24在穿矽導孔22的 侧壁與底部並同時覆蓋導電層20表面。絕緣層24較佳作為 後續石夕貫通電極與半導體基底12之間的隔絕，使矽貫通電 極與半導體基底12不至直接導通。在本實施例中’絕緣層 24可包含氧化物或氮化物等絕緣材料，且可由單層或複合材 〇料層所組成。 接者依序以化學氣相沈積（chemical vapor deposition， CVD)形成一阻障層26與一晶種層28於絕緣層24表面，然 後再以電鍍製程形成一由銅所構成的金屬層30於晶種層28 表面並填滿整個穿矽導孔22。其中阻障層26可由钽(Ta)、 氮化组(tantalum, TaN)、鈦(Ti)、氮化鈦(TiN)或其組合所構 成/、*T用來防止金屬層30中的銅離子向外遷移（migrati〇n) 201101424 而擴散至絕緣層24内，而晶插展 叫日日種層28則是與金屬層30中的 銅離子附著於絕緣層24上，w 4丨丨他成 上以利後續之鋼電鍍製程。應暸 解’金屬層3G可為銅以外的其他導電材料，且晶種層^為 選擇性存在且其材料會隨著金屬層3Q而改變。 Ο Ο 如第5圖所示’接著利用導電層2〇當作停止層來進行一 平坦化製程，例如以化學機械研磨製程去除部纽於導電層 20表面的金屬層30、晶種層28、阻障層％以及絕緣層％， 使填充於穿料孔22巾的金屬層3()表面與導電廣2〇齊平 並同時暴露出導電層2G表面。隨後如第6圖所示，進行另 一平坦化製程，例如再以化學機械研磨完全去除導電層2〇 並暴硌出设於其下的層間介電層16與設於接觸洞18中的導 電材料’以於層間介電層16中同時形成接觸插塞34與本發 明較佳實施例的矽貫通電極32。此外，亦可於導電層2〇上 選擇性形成一具有與導電層2〇不同移除率的停止層，此實 施例也屬本發明所涵蓋的範圍。 值得注意的是’本發明主要在形成穿矽導孔22前先保留 層間介電層16表面的鎢導電層20，然後於後續研磨銅金屬 層30的時候先將研磨製程停止在鎢導電層20表面，接著再 以另一道研磨製程以現場（in-situ)或非現場方式去除剩餘的 鎢導電層20。由於鎢導電層2〇1^設於其下方的層間介電層 16在研磨過程中會分別具有不同的移除率’因此以化學機械 201101424 * 研磨製程來去除導電層20的時候可有效控制研磨終點（end point)並進而控制層間介電層16的厚度，使研磨的過程中不 至流失過多的層間介電層16而導致厚度不足的問題。 最後於去除導電層20後進行半導體晶片的後段 (back-end-of-the-line，BEOL)製輕’例如可在層間介電層16 與矽貫通電極32上另形成複數個介電層（圖未示）並搭配金 ❹屬内連線與接觸墊製程，以完成複數個連接接觸插塞34的 金屬内連線結構與接觸墊。 以上所述僅為本發明之較佳實_，凡依本發明申請專 利範圍雜之均等變化與_，皆應屬本發明之涵蓋範圍 【圖武簡單說明】201101424 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for producing a stone-like through-electrode (thr〇ugh_siHc〇n shouting TSV), particularly when the 11-through electrode is fabricated while maintaining the layer current The method of making the layer thickness. ^ [Prior Art] 矽 矽 Beton Electrode (TSV) technology is a novel semiconductor technology.矽 Through electrode technology is mainly to solve the problem of interconnection between wafers, and belongs to a new three-dimensional space three-dimensional packaging technology. #红(四) Through-electrode technology provides three-dimensional space stacking, through the through-electrode to create products that are more suitable for light, thin, short, and small market demand, providing wafer level for micro-electromechanical systems (MEMS), optoelectronics and electronic components. The packaging process technology required for packaging. 〇11 through-electrode technology is to drill holes on the wafer by (4) or laser, and then fill the V-electric materials such as copper, polycrystalline stone, crane, etc. into the vias to form conductive channels (ie, within the connection). , external joint line). Finally, the wafer or the grain is thinned and then piled up and bonded, and the stacked body of the three-dimensional space is <3D 1C. Thus, the wire bonding type can be removed. By etching or lasering the Via and turning on the electrode, not only does the wiring space be omitted, but also the area of the board and the volume of the package are reduced. The internal joint distance of the structure is determined by the Shishi through electrode technology. , that is, the thickness of the wafer or the die after the thin 201101424' is smaller than the conventional stacked package adopting the wire-bonding junction, and the internal connection path of the three-dimensional space-stacked integrated circuit is shorter, and the transmission speed between the wafers can be relatively Faster, less noise, and better performance. Especially in the central office (CPU) and cache memory and the data transmission and transmission in the memory card application, it can highlight the performance advantages of the short-distance internal bonding path of the through-electrode technology. In addition, the package size of the three-dimensional space-stacked integrated circuit is equal to the grain size. In the field of portable electronic products that emphasize multi-function and small size, the miniaturization of three-dimensional space-stacked integrated circuits is the primary factor in market introduction. At present, the process of widely fabricating the through electrode is mainly performed on a surface of a semiconductor substrate to complete a desired MOS transistor, such as a complementary MOS transistor, and then forming a dielectric layer and connecting the MOS transistor. Contact plug. Next, a tantalum through electrode filled with a dielectric layer for isolation and a copper metal for conduction is formed in the interlayer dielectric layer and the semiconductor substrate. In the process of forming the contact plug and the through electrode, multiple chemical mechanical polishing is required, and each chemical mechanical polishing process is used to grind different materials. It is important to note that the grinding process, usually performed by chemical mechanical polishing, relies on different removal rates to stop the grinding process to a specific material layer. Since the interlayer dielectric layer and the dielectric layer covering the pass-through electrode for separating the same are the same dielectric materials, it is easy to remove the two material layers by chemical mechanical polishing. Except the rate, it is not possible to effectively stop the 201101424 grinding step. Under these conditions, the thickness of the interlayer dielectric layer becomes difficult to control, and in most cases, it is easy to lose too much interlayer dielectric layer to cause a problem of insufficient interlayer dielectric thickness. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a method of fabricating a ruthenium-through electrode to improve the problem of excessive loss of interlayer dielectric layers in current processes. BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the present invention is a method for fabricating a ruthenium-through electrode comprising the following (d) H-semiconductor bottom; a less-different-metal oxide semiconductor transistor on the semiconductor base surface; forming a dielectric layer in the gold Forming a contact plug opening in the dielectric layer to form the MOS transistor; forming a first conductive layer on the dielectric layer and filling the contact plug opening; (4) a process for forming a conductive layer, a dielectric layer, and a semiconductor substrate to form a conductive layer in the via hole and covering a portion of the surface of the conductive layer; and performing a planarization process, Removing a portion of the second conductive layer up to the surface of the first conductive layer. [Embodiment] The eye is referred to in the first to sixth figures, and the first to sixth figures are schematic views showing a method of fabricating a stone-through electrode according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 12 is first provided, for example, a semiconductor material known as monocrystalline silicon, arsenic arsenide (GaAs) or other known art. The base. Forming at least one MOS transistor 14 on the surface of the semiconductor substrate 12 according to a standard MOS transistor process, such as a P-type metal oxide semiconductor (PMOS) transistor, an N-type metal oxide semiconductor (NMOS) transistor, or a complementary Type of metal oxide semiconductor (CMOS) transistor, or other various types of semiconductor components. The MOS semiconductor transistors 14 may each have a standard transistor structure such as a gate, a sidewall, a light source, a source/no-polar region, and a Sihua metal layer, and are not described herein. Then, an interlayer dielectric layer 16 having a thickness of several thousand angstroms, for example, about 3,000 angstroms is formed and covers the entire oxynitride transistor 14. The interlayer dielectric layer 16 is preferably composed of a composite material layer composed of tetraethylorthosilicate (TEOS) and ph〇Sph〇silicate glass (pSG), but is not limited thereto. The interlayer dielectric layer 16 may also be composed of a BpsG and a low dielectric constant (l〇w_k), and a stress material such as a pull may be selectively interposed between the interlayer dielectric layer 16 and the MOS transistor 14. A gasification stone material of a tensile stress or a tensile stress, a stop layer cutting material, a lining layer such as a thin oxide layer, or a combination thereof. Then, a pattern transfer process, such as etch-pattern® is used, as a conductive material composed of a dielectric layer of the interlayer dielectric layer and two layers of tungsten, and the interlayer dielectric semiconductor fills the conductive hole of the contact hole 18. The material is connected to the MOS body 14 and a conductive layer is formed on the interlayer dielectric layer 16, for example, as shown in Fig. 2, 201101424. Wherein, before the formation of the conductive layer 20, an adhesive layer composed of a button (Ta), tantalum (Tatal), titanium (Ti), titanium nitride (TiN) or a combination thereof may be selectively formed ( Adhesive layer). The conductive material of the conductive layer 20 may be other conductive materials other than W such as aluminum 'copper, or an alloy thereof. As shown in FIG. 3, another pattern transfer process is subsequently performed, for example, another patterned photoresist layer (not shown) is formed on the surface of the conductive layer 20, and then the photoresist layer is used as a mask as a mask. The etching process is performed one or more times to form a through via hole 22 in the conductive layer 20, the interlayer dielectric layer 16, and the semiconductor substrate 2. As shown in Fig. 4, an insulating layer 24 is then formed to pass through the sidewalls and the bottom of the via 22 while covering the surface of the conductive layer 20. The insulating layer 24 is preferably used as a barrier between the subsequent through-electrode electrode and the semiconductor substrate 12 so that the 矽-through electrode and the semiconductor substrate 12 are not directly electrically connected. In the present embodiment, the insulating layer 24 may comprise an insulating material such as an oxide or a nitride, and may be composed of a single layer or a composite material layer. Then, a barrier layer 26 and a seed layer 28 are formed on the surface of the insulating layer 24 by chemical vapor deposition (CVD), and then a metal layer 30 made of copper is formed by an electroplating process. The seed layer 28 is surfaced and fills the entire through-via via 22 . The barrier layer 26 may be composed of tantalum (Ta), tantalum (TaN), titanium (Ti), titanium nitride (TiN) or a combination thereof, and *T is used to prevent copper ions in the metal layer 30. The outward migration (migrati〇n) 201101424 is diffused into the insulating layer 24, and the crystal growth layer 28 is attached to the insulating layer 24 with the copper ions in the metal layer 30. The following steel electroplating process. It should be understood that the metal layer 3G may be other conductive materials other than copper, and the seed layer is selectively present and its material may vary with the metal layer 3Q. Ο Ο As shown in FIG. 5, a planarization process is then performed using the conductive layer 2 as a stop layer, for example, a metal layer 30, a seed layer 28, which is removed from the surface of the conductive layer 20 by a chemical mechanical polishing process. The barrier layer % and the insulating layer % make the surface of the metal layer 3 () filled in the through-hole 22 flush with the conductive layer and simultaneously expose the surface of the conductive layer 2G. Then, as shown in FIG. 6, another planarization process is performed, for example, the conductive layer 2 is completely removed by chemical mechanical polishing, and the interlayer dielectric layer 16 disposed underneath and the conductive layer provided in the contact hole 18 are violently discharged. The material is used to simultaneously form the contact plug 34 and the tantalum through electrode 32 of the preferred embodiment of the present invention in the interlayer dielectric layer 16. Further, a stop layer having a different removal rate from the conductive layer 2 can be selectively formed on the conductive layer 2, and this embodiment is also within the scope of the present invention. It should be noted that the present invention mainly retains the tungsten conductive layer 20 on the surface of the interlayer dielectric layer 16 before forming the via hole 22, and then stops the polishing process on the tungsten conductive layer 20 after subsequently grinding the copper metal layer 30. The surface, followed by another polishing process, removes the remaining tungsten conductive layer 20 in an in-situ or off-site manner. Since the inter-layer dielectric layer 16 provided under the tungsten conductive layer 2?1 has different removal rates during the grinding process, the polishing layer can be effectively controlled by the chemical mechanical 201101424* polishing process to remove the conductive layer 20. The end point and thus the thickness of the interlayer dielectric layer 16 are such that excessive interlayer dielectric layer 16 is not lost during the polishing process, resulting in insufficient thickness. Finally, after the conductive layer 20 is removed, a back-end-of-the-line (BEOL) light is formed. For example, a plurality of dielectric layers may be formed on the interlayer dielectric layer 16 and the germanium through electrode 32. The figure is not shown) and is matched with the metal interconnect and contact pad process to complete a plurality of metal interconnect structures and contact pads connecting the contact plugs 34. The above is only the preferred embodiment of the present invention, and all the equivalent variations and _ of the patent application scope of the present invention should be covered by the present invention.
〇 法示意圖。 【主要元件符號說明】 12 爭導體基底 16 層間介電層 20 導電層 24 絕緣層 28 晶種層 14 金氧半導體電晶體 接觸洞 22 穿矽導孔 26 阻障層 30 金屬層 201101424 34 接觸插塞 32 矽貫通電極〇 Schematic diagram. [Main component symbol description] 12 Competition conductor substrate 16 Interlayer dielectric layer 20 Conductive layer 24 Insulation layer 28 Seed layer 14 Gold oxide semiconductor transistor contact hole 22 Through via hole 26 Barrier layer 30 Metal layer 201101424 34 Contact plug 32 矽 through electrode