TWI503981B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI503981B
TWI503981B TW102111827A TW102111827A TWI503981B TW I503981 B TWI503981 B TW I503981B TW 102111827 A TW102111827 A TW 102111827A TW 102111827 A TW102111827 A TW 102111827A TW I503981 B TWI503981 B TW I503981B
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contact plug
source
top surface
gate
etch stop
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TW201344918A (zh
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Ming Fa Chen
yu young Wang
Sen Bor Jan
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Taiwan Semiconductor Mfg Co Ltd
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    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

半導體裝置
本發明係有關於半導體裝置,且特別是有關於一種含貫穿孔之半導體裝置。
由於各種電子元件(例如電晶體、二極體、電阻器、電容器等)的積體密度不斷增加,半導體工業已經歷持續快速的成長。大部分而言,積體密度的增加是依靠重複地縮減最小元件尺寸,使更多的元件能被整合至單位面積內。
上述積體密度的增加本質上仍是二維(2D)的,積體元件所佔體積基本上是在半導體晶圓的表面上。雖然微影製程的顯著進步亦使得二維(2D)電路的製造具有顯著的改良,但二維所能達到的密度仍有其物理限制。
隨著裝置數量的增加及裝置之間的內連線數量及長度顯著增加,亦伴隨了許多其他額外的限制。當內連線數量及長度增加時,迅號延遲效應(RC delay)及功率均會增加。
在眾多欲解決上述限制的方案中,3維積體電路(3DIC)及晶片堆疊技術最為廣泛使用。在3DIC及晶片疊堆技術中,通常使用矽穿孔(through silicon vias,TSVs)來連接各晶片。矽穿孔有時又可稱為貫穿孔(through substrate vias)。在此種技術中,矽穿孔係用以連接晶片上之積體電路及至晶片背 端。此外,矽穿孔亦可用於提供一較短的接地路徑(grounding path)將積體電路中之接地端連接至晶片背端。
本發明實施例係提供一種半導體裝置,包括:一半導體基材;一金氧半導體電晶體,包含:一閘極電極於此半導體基材上;一源極/汲極區於此閘極電極之一側;一源極/汲極接觸插塞,包含一下部部分及一上部部分於此下部部分上,其中此源極/汲極接觸插塞位於此源極/汲極區上並與其電性連接;一閘極接觸插塞位於此閘極電極上並與其電性連接,其中此閘極接觸插塞之一頂面與此源極/汲極接觸插塞之此上部部分之一頂面齊平;以及一貫穿孔延伸進入此半導體基材中,其中此貫穿孔之一頂面係實質上與此閘極接觸插塞及此閘極電極之間的一接面齊平。
本發明實施例亦提供一種半導體裝置,包括:一半導體基材;一金氧半導體電晶體,包含:一閘極電極於此半導體基材上;一源極/汲極區於此閘極電極之一側;一源極/汲極接觸插塞,包含一下部部分及一上部部分於此下部部分上,其中此源極/汲極區接觸插塞係位於此源極/汲極區上並與其電性連接;一閘極接觸插塞位於此閘極電極上並與其電性連接,其中此閘極接觸插塞之一頂面與此源極/汲極接觸插塞之此上部部分之一頂面齊平;一第一通孔及一第一金屬線於此第一通孔上,其中此第一通孔及此第一金屬線形成一第一雙鑲嵌結構,其中此第一通孔之一底面係與此閘極接觸插塞之一頂面相接觸;以及一貫穿孔延伸進入此半導體基材中,其中此貫穿孔之一頂面係 實質上與此第一金屬線之一頂面齊平。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
10‧‧‧晶圓
20‧‧‧基材
22‧‧‧絕緣區
22A‧‧‧淺溝槽隔離區
24‧‧‧MOS裝置
25‧‧‧閘極介電質
26‧‧‧閘極電極
27‧‧‧閘極間隔物
28‧‧‧源極/汲極區
30‧‧‧層間介電層
32‧‧‧接觸插塞
38‧‧‧化學機械研磨停止層
40‧‧‧光阻
42‧‧‧TSV開口
44‧‧‧絕緣層
46‧‧‧擴散阻障層
48‧‧‧金屬材料
50‧‧‧TSV
52‧‧‧接觸蝕刻停止層
54‧‧‧層間介電層
56‧‧‧接觸插塞
58‧‧‧接觸插塞
58’‧‧‧接觸插塞
60‧‧‧蝕刻停止層
62‧‧‧通孔
63‧‧‧擴散阻障層
64‧‧‧金屬線
66‧‧‧介電層
68‧‧‧蝕刻停止層
70‧‧‧重分佈線/墊
72‧‧‧電連接器
第1~9圖顯示依照本發明某些實施例之貫穿孔之製造方法於各種中間階段之剖面圖。
第10圖顯示依照本發明某些其他實施例之貫穿孔及金氧半導體電晶體裝置之剖面圖。
第11圖顯示第10圖所示結構於中間製程時的剖面圖。
第12及13圖顯示依照本發明某些更其他實施例之貫穿孔及金氧半導體電晶體裝置於各種中間階段之剖面圖。
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。值得注意的是,這些實施例提供許多可行之發明概念並可實施於各種特定情況。然而,在此所討論之這些特定實施例僅用於舉例說明,但非用於限定本發明之範圍。
在此,係提供依照本發明各實施例之貫穿孔及其製造方法,並顯示貫穿孔於製造時的中間階段及可能的實施例變化。在本說明書所舉例的各種實施例及圖示中,類似元件係以相同參考標號表示。
參見第1圖,首先提供晶圓10。晶圓10包含基材 20,其可包含矽、鍺化矽、碳化矽、砷化鍺、III-V半導體化合物材料及、或其類似物。基材20可為塊材(bulk substrate)或絕緣體上覆半導體(SOI)之基材。絕緣區22可形成於基材20中。絕緣區22可例如是淺溝槽隔離(STI)區。
金氧半導體(MOS)裝置(電晶體)24形成於基材20之頂面。MOS裝置24包含閘極介電質25、閘極電極26及閘極間隔物27,其中閘極間隔物27位於閘極介電質25及閘極電極26之側壁上。源極及汲極區28(此後稱為源極/汲極區)可為基材之一部分,並依照所對應的MOS裝置的導電型態摻有P型或N型雜質。源極/汲極區28亦可包含應力源,以施予應力至MOS裝置24之通道區,其中應力源可為鍺化矽應力源或碳化矽應力源。雖然圖中未顯示,源極/汲極矽化物可形成於源極/汲極區28的頂部及/或閘極電極26的頂部。閘極電極26可為金屬閘極,其可由金屬或金屬合金形成,或亦可由多晶矽、金屬矽化物或其類似物形成。閘極電極26係形成於層間介電層(ILD)30中。層間介電層30可由氧化物形成,例如磷矽玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜磷矽玻璃(BPSG)、四乙基矽氧烷(TEOS)氧化物或其類似物。在某些實施例中,可使用前閘極製程來形成閘極電極26,雖然亦可使用後閘極製程。閘極電極26之頂面係可與層間介電層30之頂面齊平。
接觸插塞32係形成於層間介電層30中,與源極/汲極區28重疊並電性連接。在某些實施例中,接觸插塞32之頂面、閘極電極26之頂面、及/或層間介電層30之頂面係相互齊平。
參見第2圖,化學機械研磨(CMP)停止層38係形成於層間介電層30、閘極電極26及接觸插塞32上。化學機械研磨停止層38可包含氮化矽、碳氧化矽或其類似物。光阻40係形成於化學機械研磨停止層38上,並經圖案化。MOS裝置24可受光阻40的剩餘部分保護。接著,可進行圖案化製程,蝕刻化學機械研磨停止層38、層間介電層30及基材20,以形成貫穿孔(此後稱為TSV)開口42。在某些實施例中,TSV開口42延伸進入多個淺溝槽隔離區22之其中一者(標記為22A),以使淺溝槽隔離區22的剩餘部分環繞TSV開口42。在蝕刻期間,淺溝槽隔離區22A可用以作為蝕刻停止層。或者,TSV開口42不會穿越任何的淺溝槽隔離區22。TSV開口42停在基材20之頂面及底面之間的任一水平。
參見第3圖,光阻40係透過例如灰燼步驟予以移除。接著,參見第4圖,絕緣層44係形成於化學機械研磨停止層38之頂面上,並延伸進入TSV開口42中。絕緣層44可為實質上順應的膜層,其中絕緣層44的水平部分及垂直部分具有相同的厚度。絕緣層44可包含氧化矽、氮化矽、碳化矽、氮氧化矽、前述之組合或前述之多層組合。接著,毯覆式形成擴散阻障層46以覆蓋TSV開口42的側壁及底部。此擴散阻障層46亦可作為黏著層。擴散阻障層46可包含鈦、氮化鈦、鉭、氮化鉭或前述之組合,且可由例如物理氣相沉積形成。接著,可毯覆式沉積一薄的晶種層(未顯示)於擴散阻障層46上。此晶種層可包含銅或銅合金,或亦可包含如鎢、銀、金、鋁、或前述之組合等金屬。有某些實施例中,晶種層係可透過物理氣相沉積形成。在 其他實施例中,晶種層亦可使用其他方法形成,例如電鍍或無電電鍍。
接著,以金屬材料填充TSV開口42,並因此形成TSV 50於TSV開口42中。在多個實施例中,金屬材料48包含銅或銅合金,或亦可包含如鋁、銀、金、或前述之組合等金屬,且可由例如電鍍或無電電鍍形成。金屬材料48係填充至金屬材料48之頂面高於化學機械研磨停止層38之頂面。
第5圖顯示以化學機械研磨步驟移除過剩的金屬材料48。在某些實施例中,化學機械研磨製程使用實質上不會損傷化學機械研磨停止層38之研磨漿,並因此使化學機械研磨停止於化學機械研磨停止層38。接替,進行更一步的化學機械研磨,例如,使用會損傷化學機械研磨停止層38的研磨漿進久研磨。因此,在某些實施例中,係暴露出接觸插塞32及閘極電極26的頂面。在所示的結構中,TSV 50的頂面係與接觸插塞32之頂面及層間介電層30之頂面齊平,並可能與閘極電極26之頂面齊平。
參見第6圖,形成接觸蝕刻停止層(CESL)52及層間介電層54。在某些實施例中,接觸蝕刻停止層(CESL)52係由氮化矽或其他介電材料形成。層間介電層54可包含碳氧化矽、四乙基矽氧烷(TEOS)氧化物及/或其類似物。
接著,第7圖顯示為形成閘極觸插塞56、源極/汲極接觸插塞58。源極/汲極接觸插塞58與接觸插塞32重疊且連接。閘極接觸插塞56與閘極電極26重疊並連接,且有時可包含多晶矽。此外,TSV接觸插塞58’係形成於TSV 50上,與TSV 50 重疊並相連接,以用於與TSV 50電性連接。接觸插塞56、58及58’係形成於層間介電層54中,其中該接觸插塞56係與閘極電極26具有物理接觸並電性連接。源極/汲極接觸插塞58係與接觸插塞32具有物理接觸並電性連接。TSV接觸插塞58’可穿透接觸蝕刻停止層52,以與TSV 50相接觸。形成接觸插塞56、58及58之製程可包含:於層間介電層54及接觸蝕刻停止層52中形成開口;以黏著/阻障層及如鎢或銅等金屬材料填充該開口;及進行化學機械研磨。
可觀察到的是,每一層接觸插塞32及對應於其上的接觸插塞58係結合形成源極/汲極接觸插塞。既然接觸插塞32及接觸插塞58由不同步驟形成,可在接觸插塞32及接觸插塞58之間觀察到接面(interface)。此外,接觸插塞32及接觸插塞58之邊緣可能不是連續及光滑。
在隨後的製程中,如第8圖所示,形成蝕刻停止層60、通孔62及金屬線64。金屬線64係可通稱為底金屬層M1。通孔62及金屬線64係形成於介電層66中,其中介電層66可由介電常數低於約3.0(或低於2.5)之低介電常數介電材料形成。介電層66亦可稱為金屬間介電層(IMD)。
在某些實施例中,通孔62及金屬線64係形成於雙鑲嵌結構,並因此在通孔62及對應設置於其上之金屬線64之間無明顯的接面。雙鑲嵌結構可包含擴散阻障層63(例如鈦/氮化鈦/鉭/氮化鉭)及含銅材料於擴散阻障層63上。當通孔62及金屬線64形成雙鑲嵌結構時,擴散阻障層63係不會插設在通孔62及對應設置於其上之金屬線64之間。在其他實施例中,通孔62及 金屬線64亦可使用單鑲嵌製程形成。在更其他實施例中,係不會形成通孔62,而金屬線64係會與接觸插塞56及58接觸。在隨後的製程中,可形成更多的金屬層(未顯示)於金屬線64上。接著,可形成蝕刻停止層68,並可於更多的介電層中形成更多的金屬線及通孔(未顯示,以虛線表示),以電性連接TSV 50及接觸插塞56、58。
第9圖顯示形成與TSV 50相連之背端結構。在某些實施例中係由背端(如第8、9圖所示之向下面)研磨基材20,直至暴露出TSV 50。接著,形成重分佈線/墊70,以與TSV 50電性連接。電連接器72可形成於重分佈線/墊70上。電連接器72可為銲球、銅柱或包含銅柱及銲蓋。
第10至13圖顯示依照本發明其他實施例之TSV 50之製造方法。除非特別聲明,在這些實施例中的,使用與第1至9圖相同參考標號的元件係代表其相似元件,係由相似材料及製程形成。因此,第10至13圖中的相似元件的詳細討論係可參見關於第1至9圖之實施例之討論。
參見第10圖,TSV 50之頂面係與接觸插塞56及接觸插塞58齊平。除了TSV 50是在接觸插塞56、接觸插塞58之後及蝕刻停止層60之前形成,其餘製程係類似於第8圖之TSV 50之製造方法。例如,第11圖係顯示TSV 50之製造方法於中間階段之剖面圖。在某些實施例中,在形成層間介電層54、接觸插塞56及接觸插塞58之後,形成化學機械研磨38,並接著形成TSV開口42。接著,形成絕緣層、擴散阻障層及晶種層(未顯示)。隨後,以金屬材料填充TSV開口42之剩餘部分。絕緣層、 擴散阻障層、晶種層及金屬材料之形成方法及材料係可參見第4圖所示之實施例。在進行化學機械研磨之後,可得到如第10圖所示之TSV 50結構。接著,如第10圖所示,形成覆蓋的前端結構,包含蝕刻停止層60、通孔62及金屬線64。接著,進行背端研磨,以自基材背端暴露出TSV 50。接著,形成重分佈線/墊70及電連接器72。
第12及13圖顯示依照本發明更其他實施例之TSV 50之製造方法於各種中間製程之剖面圖。在這些實施例中,TSV 50係在形成金屬線64之後形成,使用類似於第2至5圖之方法。接著,形成蝕刻停止層68。因此,TSV 50之頂面係與金屬線64之頂面齊平,其可與形成於其上之通孔62形成雙鑲嵌結構。更多的金屬線、通孔及介電層,例如對應地類似於金屬線64、通孔62及介電層66,可形成於第12及13圖所示之結構上。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾。此外,本發明之範圍不限定於現有或未來所發展的特定程序、機器、製造、物質之組合、功能、方法或步驟,其實質上進行與依照本發明所述之實施例相同的功能或達成相同的結果。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。此外,每個申請專利範圍建構成一獨立的實施例,且各種申請專利範圍及實施例之組合皆介於本發明之範圍內。
10‧‧‧晶圓
20‧‧‧基材
22‧‧‧絕緣區
26‧‧‧閘極電極
28‧‧‧源極/汲極區
30‧‧‧層間介電層
32‧‧‧接觸插塞
44‧‧‧絕緣層
46‧‧‧擴散阻障層
48‧‧‧金屬材料
50‧‧‧TSV
52‧‧‧接觸蝕刻停止層
54‧‧‧層間介電層
56‧‧‧接觸插塞
58‧‧‧接觸插塞
58’‧‧‧接觸插塞
60‧‧‧蝕刻停止層
62‧‧‧通孔
64‧‧‧金屬線
66‧‧‧介電層
68‧‧‧蝕刻停止層
70‧‧‧重分佈線/墊
72‧‧‧電連接器

Claims (10)

  1. 一種半導體裝置,包括:一半導體基材;一金氧半導體電晶體,包含:一閘極電極於該半導體基材上;及一源極/汲極區於該閘極電極之一側;一源極/汲極接觸插塞,包含一下部部分及一上部部分於該下部部分上,其中該源極/汲極接觸插塞位於該源極/汲極區上並與其電性連接;一閘極接觸插塞位於該閘極電極上並與其電性連接,其中該閘極接觸插塞之一頂面與該源極/汲極接觸插塞之該上部部分之一頂面齊平;以及一貫穿孔延伸進入該半導體基材中,其中該貫穿孔之一頂面係實質上與該閘極接觸插塞及該閘極電極之間的一接面齊平。
  2. 如申請專利範圍第1項所述之半導體裝置,更包含:一層間介電層於該半導體基材上,其中該閘極電極及該源極/汲極接觸插塞之該下部部分包含部分位於該層間介電層中;及一蝕刻停止層於該層間介電層上並與其接觸,其中該貫穿孔之該頂面與該蝕刻停止層相接觸。
  3. 如申請專利範圍第2項所述之半導體裝置,其中該閘極接觸插塞與該源極/汲極接觸插塞之該上部部分穿透該蝕刻停止層。
  4. 如申請專利範圍第1項所述之半導體裝置,更包含一通孔及一金屬線於該通孔上,其中該通孔及該金屬線形成一雙鑲嵌結構,且其中該通孔之一底面係與該閘極接觸插塞之一頂面相接觸。
  5. 如申請專利範圍第4項所述之半導體裝置,更包含:一層間介電層於該閘極介電層上,其中該源極/汲極接觸插塞之該上部部分包含一部分設置於該層間介電層中;及一蝕刻停止層於該層間介電層上,其中該通孔延伸進入該蝕刻停止層中。
  6. 如申請專利範圍第1項所述之半導體裝置,其中該源極/汲極接觸插塞之該上部部分及該下部部分具有一可觀察到的接面。
  7. 一種半導體裝置,包括:一半導體基材;一金氧半導體電晶體,包含:一閘極電極於該半導體基材上;及一源極/汲極區於該閘極電極之一側;一源極/汲極接觸插塞,包含一下部部分及一上部部分於該下部部分上,其中該源極/汲極區接觸插塞係位於該源極/汲極區上並與其電性連接;一閘極接觸插塞位於該閘極電極上並與其電性連接,其中該閘極接觸插塞之一頂面與該源極/汲極接觸插塞之該上部部分之一頂面齊平;一第一通孔及一第一金屬線於該第一通孔上,其中該第一 通孔及該第一金屬線形成一第一雙鑲嵌結構,其中該第一通孔之一底面係與該閘極接觸插塞之一頂面相接觸;以及一貫穿孔延伸進入該半導體基材中,其中該貫穿孔之一頂面係實質上與該第一金屬線之一頂面齊平。
  8. 如申請專利範圍第7項所述之半導體裝置,更包含:一層間介電層於半導體基材上,其中該閘極電極及該源極/汲極之下部部分包含部分於層間介電層中;及一蝕刻停止層於該層間介電層上並與其相接觸,其中該源極/汲極接觸插塞之該上部部分及該下部部分具有一接面,且該接面與該蝕刻停止層之一底面實質上齊平,其中該源極/汲極接觸插塞之該上部部分及該下部部延伸穿越該蝕刻停止層。
  9. 如申請專利範圍第7項所述之半導體裝置,其中該源極/汲極接觸插塞之該上部部分及該下部部分形成一可觀察到的接面。
  10. 如申請專利範圍第7項所述之半導體裝置,更包含:一蝕刻停止層於該閘極接觸插塞及該源極/汲極接觸插塞上,其中該蝕刻停止層之一底面係與該閘極接觸插塞及該源極/汲極接觸插塞之頂面實質上齊平。
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