TWI764681B - 半導體封裝及封裝組件及製造方法 - Google Patents

半導體封裝及封裝組件及製造方法

Info

Publication number
TWI764681B
TWI764681B TW110114335A TW110114335A TWI764681B TW I764681 B TWI764681 B TW I764681B TW 110114335 A TW110114335 A TW 110114335A TW 110114335 A TW110114335 A TW 110114335A TW I764681 B TWI764681 B TW I764681B
Authority
TW
Taiwan
Prior art keywords
wafer
bonding layer
bonding
layer
vias
Prior art date
Application number
TW110114335A
Other languages
English (en)
Other versions
TW202234536A (zh
Inventor
陳明發
史朝文
葉松峯
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Application granted granted Critical
Publication of TWI764681B publication Critical patent/TWI764681B/zh
Publication of TW202234536A publication Critical patent/TW202234536A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0383—Reworking, e.g. shaping
    • H01L2224/03845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2783—Reworking, e.g. shaping
    • H01L2224/27831—Reworking, e.g. shaping involving a chemical process, e.g. etching the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2783—Reworking, e.g. shaping
    • H01L2224/2784—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/2783—Reworking, e.g. shaping
    • H01L2224/27845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/80379—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying
    • H01L2224/8082—Diffusion bonding
    • H01L2224/8083—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

本發明的實施例提供一種封裝結構及製造方法，其中接 合介電材料層設置於晶圓的背側處，接合介電材料層設置於鄰接晶圓的前側處，且其中接合介電材料層彼此融合接合。

Description

半導體封裝及封裝組件及製造方法
本發明的實施例是有關於封裝及封裝組件及製造方法。
半導體元件用於多種電子應用中，諸如個人電腦、行動電話、數位攝影機以及其他電子設備。典型地藉由在半導體基底上方依序沈積絕緣層或介電層、導電材料層以及半導電材料層，以及使用微影術圖案化各種材料層以在其上形成電路組件及部件來製造半導體元件。典型地在單一半導體晶圓上製造數十或數百個積體電路。藉由沿切割道鋸割積體電路而使個別晶粒單體化。接著以多晶片模組形式或以其他類型的封裝形式分別地封裝個別晶粒。
半導體行業歸因於多種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度的持續改良而經歷快速增長。主要地，積體密度的此改良源自於最小特徵尺寸的反覆減小(例如使半導體製程節點向小於20奈米的節點縮小)，此允許將更多組件集成至給定區域中。隨著近來對小型化、較高速度及較大頻寬以及較低功耗及時延的需求已增長，已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。
隨著半導體技術進一步發展，堆疊半導體元件(例如三維積體電路(three dimensional integrated circuit；3DIC))已作為進一步減小半導體元件的物理尺寸的有效替代物出現。在堆疊半導體元件中，諸如邏輯、記憶體、處理器電路以及類似物的主動電路在不同半導體晶圓上製造。兩個或大於兩個半導體晶圓可安裝或堆疊於彼此的頂部上以進一步減小半導體元件的形式因數。堆疊封裝(package-on-package；POP)元件為一種類型的3DIC，其中晶粒經封裝且接著與另一或另一些封裝晶粒一起封裝。
一個實施例為一種方法，包含薄化第一晶圓以暴露出金屬通孔。在金屬通孔上方形成接合層，金屬通孔延伸穿過接合層。將第二晶圓定位至第一晶圓，其中第二晶圓的接合墊對準至第一晶圓的金屬通孔，且在於第二晶圓的接合墊與第一晶圓的金屬通孔之間不使用接合材料的情況下，使第二晶圓的接合墊與第一晶圓的金屬通孔接合。第一晶圓的接合層融合至第二晶圓的接合層。
另一實施例為一種封裝，包含第一元件、第二元件以及第三元件。第一元件可包含第一組通孔、第一主動元件以及第一內連線結構，第一組通孔自第一元件的前部橫穿第一內連線結構達至第一元件的背部，第一主動元件鄰接第一內連線結構。第二元件可包含第二組通孔、第二主動元件、第二內連線結構、第二前向接合層以及第二反向接合層，第二反向接合層在第二元件的背側上，第二反向接合層可包含第一介電材料，第二前向接合層接合至第一元件，其中第二組通孔自第二前向接合層橫穿第二反 向接合層。第三元件可包含第三組通孔、第三主動元件、第三內連線結構以及第三前向接合層，第三前向接合層可包含與第一介電材料相同的介電材料，其中第三組通孔自第三前向接合層橫穿第三元件達至第三元件的背側，其中第二反向接合層接合至第三前向接合層。
另一實施例為一種封裝組件，包含：第一晶圓，接合至第二晶圓，其中在接合界面處，第一晶圓的金屬通孔直接接合至第二晶圓的接合墊，且第一晶圓的第一接合層融合至第二晶圓的第二接合層，第一接合層安置於第一晶圓的背側處，第一晶圓的金屬通孔橫穿第一接合層，穿過半導體基底，且穿過第一晶圓的第一內連線。
100、100'、200、200a、200b、200c、200d、200n:晶圓
110、210:元件區
111、211:切割道
112、212:晶粒
115、215:基底
118:電晶體
120、220:通孔
121、221、246:障壁層
125、225、225a、225b:接觸墊
130、230:內連線結構
131:金屬特徵
132、235、240:介電層
150、310:釋放層
155:間隙填充材料
160、250:接合層
165:通孔延伸部
190、305、405:載板基底
219:通孔開口
245:接合墊通孔
255:接合墊
260:接合結構
265:反向接合層
300、300a、300b、300c、400、400a、400b、400c、400n:晶圓堆疊
500:封裝
505:下部部分
510:上部部分
515:連接件
530:重佈線結構
540:熱界面材料
550:熱耗散結構
560:切割技術
結合附圖閱讀以下詳細描述會最佳地理解本揭露的各態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，出於論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1及圖2、圖3a至圖3d以及圖4至圖10示出根據一些實施例的形成封裝的第一晶圓的製程中的中間步驟。
圖11至圖19示出根據一些實施例的形成封裝的第二晶圓的製程中的中間步驟。
圖20a、圖20b以及圖21至圖26示出根據一些實施例的晶圓堆疊配置。
圖27至圖30示出根據一些實施例的形成雙層晶圓堆疊的製程。
圖31及圖32示出根據一些實施例的使用雙層晶圓堆疊的製程。
圖33及圖34示出根據一些實施例的形成四層晶圓堆疊的製程。
圖35及圖36示出根據一些實施例的使用四層晶圓堆疊的製程。
圖37a至圖37d示出根據一些實施例的使用單層、雙層及/或四層堆疊的製程。
圖38a及圖38b示出根據一些實施例的使用單層、雙層及/或四層堆疊形成封裝的製程。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及佈置的特定實例以簡化本揭露。當然，這些特定實例僅為實例，且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或在第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標記及/或字母。此重複是出於簡單及清楚的目的，且本身並不規定所論述的各種實施例及/或配置之間的關係。
此外，為易於描述，可在本文中使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及其類似物的空間相對術語，以描述如諸圖中所示出的一個元件或特徵與另一(些) 元件或特徵的關係。除諸圖中所描繪的定向以外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
實施例提供一種多晶粒堆疊結構。在一些實施例中，單層、雙層以及四層晶圓結構的組合可貼附至元件晶圓，諸如控制器晶圓。多層結構中的每一者可含有主動元件及穿過晶圓的基底的穿孔。在將一個晶圓接合至另一晶圓之前，可將基底薄化以暴露出穿孔。接著可形成接合層以使得穿孔穿過接合層。穿孔可接合至下一晶圓的接合墊。多晶粒結構可經預製造且接著接合至另一晶圓，諸如控制器晶圓。
圖1至圖7示出形成及製備晶粒112的製程中的中間步驟。晶粒112中的一或多者可形成為邏輯晶粒，諸如中央處理單元(Central Processing Unit；CPU)晶粒、微控制單元(Micro Control Unit；MCU)晶粒、輸入輸出(input-output；IO)晶粒、基帶(BaseBand；BB)晶粒、應用程式處理器(Application processor；AP)晶粒、系統晶片(System on Chip；SoC)、系統積體晶片(System on Integrated Chip；SoIC)或類似物。晶粒112中的一或多者亦可為記憶體晶粒，諸如動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒或靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒或類似物。在所示出的實施例中，一或多個晶粒或晶粒堆疊可接合至晶粒112。
參考圖1，示出根據一些實施例的具有若干晶粒112的晶圓100的俯視圖。晶粒112可經配置以各自包含相同晶粒功能或 不同晶粒功能。晶粒112中的每一者之間為切割道111，所述切割道111經指派用於在後續製程中使晶粒112單體化。晶粒112可理解為封裝區域，且切割道111可理解為非封裝區域。在一些實施例中，無主動元件或被動元件形成於切割道111中，且因此在此類實施例中，切割道111不含主動元件或被動元件。
在圖2中，示出晶圓100的一部分的橫截面視圖。在所示出的部分中，第一晶粒112及第二晶粒112予以示出，且由切割道111分離。為簡單起見，已省略細節。應理解，關於晶粒112的圖示是出於說明目的，且不應被視為受限於特定配置。
晶粒112可包含具有形成於其中的一或多個主動元件或被動元件的基底115。基底115可由矽形成，但基底115亦可由其他第III族、第IV族及/或第V族元素形成，所述元素諸如矽、鍺、鎵、砷以及其組合。基底亦可呈絕緣層上矽(silicon-on-insulator；SOI)的形式。SOI基底可包括形成於絕緣層(例如埋入式氧化物及/或類似物)上方的半導體材料(例如矽、鍺及/或類似物)層，所述絕緣層形成於矽基底上。另外，可使用的其他基底包含多層基底、梯度基底(gradient substrates)、混合定向基底(hybrid orientation substrates)、其任何組合及/或類似物。
在所示出的實施例中，晶圓100包含晶粒112中的每一者的元件區110。元件區110可包含諸如電晶體118的嵌入式元件或諸如二極體的其他主動元件，以及可能存在的被動元件，諸如電容器、電感器、電阻器或類似物。在元件區110上方為內連線結構130，所述內連線結構130使元件互連，且將輸入/輸出信號路由至元件。
內連線結構130可包含介電層以及形成於介電層中的金屬線及通孔，所述細節出於簡單起見而未予以繪示。內連線結構130的介電層亦可稱為金屬間介電(Inter-Metal Dielectric；IMD)層。介電層中的一些或全部可由低k介電材料形成，所述低k介電材料具有低於約3.0或約2.5的介電常數(k值)。內連線結構130的介電層可由黑鑽石(Black Diamond，應用材料公司(Applied Materials)的註冊商標)、含碳低k介電材料、氫倍半矽氧烷(Hydrogen SilsesQuioxane；HSQ)、甲基倍半矽氧烷(Methyl SilsesQuioxane；MSQ)或類似物形成。根據本揭露的其他實施例，介電層中的一些或全部由非低k介電材料形成，所述非低k介電材料諸如氧化矽、碳化矽(SiC)、氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)或類似物。根據本揭露的一些實施例，形成內連線結構130的介電層包含沈積含成孔劑(porogen)介電材料，且接著執行固化製程以驅出成孔劑，且因此其餘介電層變為多孔的。可由碳化矽、氮化矽或類似物形成的蝕刻終止層可形成於IMD層之間。
內連線結構130的金屬線及通孔形成於內連線結構130的介電層中。因此，內連線結構130可包含經由內連線結構130的通孔互連的多個金屬層(處於相同層中的金屬線)。金屬線及通孔可由銅或銅合金形成，且其亦可由其他金屬形成。形成製程可包含單鑲嵌製程及雙鑲嵌製程。在單鑲嵌製程中，首先在內連線結構130的介電層中的一者中形成溝渠，隨後用導電材料填充溝渠。接著執行諸如CMP製程的平坦化製程，以移除導電材料的高於IMD層的頂部表面的過量部分，從而在溝渠中留下金屬線。在雙鑲嵌製程中，在IMD層中形成溝渠及通孔開口兩者，其中通孔 開口在溝渠之下且連接至溝渠。接著將導電材料填充至溝渠以及通孔開口中以分別形成金屬線及通孔。導電材料可包含擴散障壁及在擴散障壁上方的含銅金屬材料。擴散障壁可包含鈦、氮化鈦、鉭、氮化鉭或類似物。
根據本揭露的一些實施例，介電層132形成於內連線結構130上方。介電層132可由多個層形成。在一些實施例中，介電層132可由氧化矽、氮氧化矽、碳氧化矽或類似物形成。
對應於通孔120的通孔開口可形成為穿過介電層132且進入基底115中。在一些實施例中，通孔開口可暴露出內連線結構130的金屬特徵以用於耦接至元件區110中的主動元件及/或被動元件。對應於通孔120的通孔開口中的一或多者可不暴露出內連線結構130的金屬特徵，以使得隨後形成於通孔開口中的通孔材料不耦接至元件區110中的元件中的任一者，且可被視為虛設通孔。通孔開口可使用微影製程使用例如在介電層132上方形成及圖案化的光阻及/或硬式罩幕形成。非等向性蝕刻可用以形成穿過光阻及/或硬式罩幕的通孔開口。
通孔120及接觸墊125可形成於介電層132上方。通孔120及接觸墊125可藉由與上文所描述的形成內連線結構130的通孔及金屬線類似的製程形成，但可使用其他合適的製程。舉例而言，可將晶種層沈積於通孔開口中，且可藉由利用例如電鍍或化學鍍將導電材料沈積於通孔開口中的晶種層上而形成通孔。接觸墊125可同時或在後續類似製程中形成。通孔120及接觸墊125可由銅或銅合金形成，且其亦可由其他金屬形成。
在一些實施例中，晶粒112包括已在功能上經測試的一 或多個已知良好晶粒(known good die；KGD)。在一些實施例中，測試不合格的晶粒112可不經歷進一步處理，且可予以回收或捨棄。在其他實施例中，測試不合格的晶粒112可與KGD一起保留於晶圓100中經歷進一步處理，且在後續步驟中予以回收或捨棄。舉例而言，使用晶圓至晶圓接合製程的實施例將整個未單體化晶圓接合至晶圓100，而使用晶片至晶圓或晶片至晶片接合製程的實施例將單體化晶片接合至晶圓100，或將單體化晶片接合至晶圓100的單體化晶片。因此，在一些實施例中，僅為KGD的晶粒112經歷後續封裝處理，且不封裝CP測試不合格的晶粒。
圖3a、圖3b、圖3c以及圖3d示出用於在封裝製程中使用晶圓100及晶粒112的各種實施例。在圖3a及圖3b中，晶圓100保持完好且貼附至載板基底190，且在圖3c及圖3d中，晶圓100經單體化以釋放晶粒112。KGD可接著貼附至載板基底190。在圖3a及圖3c中，晶圓100及/或晶粒112經旋轉(亦即經翻轉且面向下貼附至載板基底190)。在圖3b及圖3d中，晶圓100及/或晶粒112保持面向上，且晶圓100及/或晶粒112的背側(非主動側)貼附至載板基底190。
一般而言，載板基底190在後續處理步驟期間向各種特徵(例如晶圓100)提供臨時機械及結構支撐。以此方式，減小或防止對晶粒112的損害。載板基底190可包括例如玻璃、陶瓷、塊狀矽以及類似物。釋放層150可用以使晶圓100及/或晶粒112貼附至載板基底190。在一些實施例中，載板基底190可實質上不含任何主動元件及/或功能電路系統。在一些實施例中，載板基底190可包括塊狀矽，且晶圓100及/或晶粒112可藉由介電釋放層 150貼附至載板基底190。在一些實施例中，載板基底190可包括支撐帶(support tape)。
釋放層150可為任何晶粒貼附膜或任何合適的黏著劑、環氧樹脂、紫外線(ultraviolet；UV)膠(其在暴露於UV輻射時損失其黏著劑特性)或類似物。釋放層150可使用沈積製程、旋塗、印刷製程、層壓製程或類似製程在載板基底190的表面上方或在晶圓100及/或晶粒112的表面上方形成。在其他實施例中，釋放層150可為熱型的，其中在將釋放層150暴露於合適的熱源之後，釋放層的黏著強度實質上減小。
在一些實施例中，使晶圓100及/或晶粒112貼附至載板基底190使用融合接合(fusion bonding)製程，其中晶圓100的絕緣層直接接合至介電釋放層150以形成絕緣層至絕緣層接合。下文將結合下文關於圖20a所描述的晶圓至晶圓接合來論述關於融合接合的其他細節。
在一些實施例中，例如圖3c及圖3d，例如藉由鋸割、雷射剝蝕或類似操作將晶圓100單體化為個別晶粒112。隨後，可藉由取放製程將晶粒定位於載板基底190上。可接著沈積間隙填充材料155以包封晶粒112且接著磨回，以使得間隙填充材料155的上部表面與晶粒112的上部表面齊平。間隙填充材料155可包括模製化合物，諸如環氧樹脂、樹脂、可模製聚合物、聚醯胺或類似物。模製化合物可在實質上為液體時予以施加，且接著可經由化學反應而固化，諸如以環氧樹脂或樹脂。在其他實施例中，模製化合物可為以凝膠或延展性固體形式施加的紫外線(ultraviolet；UV)固化聚合物或熱固化聚合物。在一些實施例中， 間隙填充材料155可包括使用任何合適的製程沈積的非聚合物如二氧化矽、氮化矽或類似物，諸如另一氧化物或氮化物。舉例而言，可藉由CVD、PECVD或ALD沈積製程、FCVD或旋塗玻璃(spin-on-glass)製程形成間隙填充材料155。為易於參考，所得結構可稱為晶圓100'，然而，應意識到，此晶圓100'實際上並非晶圓，而是可在後續描述中針對晶圓100以取代方式來使用。
在圖4至圖7中，根據一些實施例，例如，如在圖3a及圖3c中，晶圓100或晶圓100'面向下。在此類實施例中，可薄化晶圓100或晶圓100'的背側。儘管示出來自圖3a的結構，但應理解，實際上可取代圖3c中的結構(稱為晶圓100')。亦可取代圖3b及圖3d中的結構，然而，因這些結構定向為面向上，故在此類實施例中省略圖4至圖7中所示出的製程。在圖4中，晶圓100經薄化以減小晶圓100的厚度。薄化可藉由CMP製程、研磨、蝕刻或其他合適的製程來進行。薄化暴露出晶圓100及/或晶粒112中的通孔120，且亦減小晶圓100及/或晶粒112的厚度以提供較佳熱耗散且佔據較少豎直空間。在薄化之後，晶圓100及/或晶粒112的厚度可為約2微米至100微米，諸如厚度在約10微米與50微米之間。在一些實施例中，間隙填充材料155的頂部表面與晶圓100及/或晶粒112的上部表面(背側)在製程變化內實質上共面。
在其他實施例中，通孔120可在薄化晶圓100及/或晶粒112之後而非在薄化之前形成。在此類實施例中，可使用與上文已針對形成例如內連線結構130的通孔所描述的製程及材料類似的製程及材料形成通孔120。
圖5至圖7包含根據一些實施例的將接合層添加至圖4的薄化基底115的背部的製程。在圖5中，可藉由任何合適的製程(例如藉由回蝕製程)使用合適的濕式或乾式蝕刻製程使基底115凹陷。因此可暴露出通孔120的上部側壁。在一些實施例中，可使基底115凹陷0.8微米與約3微米之間的深度，但涵蓋且可使用其他尺寸。
在圖6中，接合層160可沈積於通孔120的暴露部分上方。接合層160可為任何合適的絕緣材料，諸如氧化物，諸如氧化矽；或氮化物，諸如氮化矽；或聚醯亞胺；或類似物。可使用任何合適的製程來沈積接合層160。舉例而言，可藉由CVD、PECVD或ALD沈積製程、FCVD或旋塗玻璃製程形成接合層160。
在圖7中，可諸如藉由CMP製程來使接合層160平坦化，藉此使通孔120的上部表面與接合層160齊平。接合層160的厚度可在約0.8微米與3微米之間，但涵蓋且可使用其他尺寸。
圖8至圖10包含根據一些實施例的將接合層添加至圖4的薄化基底115的背部的製程。在圖8中，接合層160沈積於基底115及通孔120上方。可使用與上文關於圖6所論述的製程及材料類似的製程及材料形成接合層160。接合層160的厚度可在約0.8微米與3微米之間，但涵蓋且可使用其他尺寸。
在圖9中，開口形成於對應於通孔120的接合層160中。可使用任何合適的技術(諸如藉由機械或雷射鑽孔或微影技術)形成開口。在一些實施例中，開口可具有比通孔120更大的寬度。
在圖10中，通孔延伸部165沈積於接合層160的開口中。通孔延伸部165可為與通孔120的材料相同的材料或不同的材 料。可藉由任何合適的技術(諸如藉由使用PVD、CVD、電鍍、化學鍍等)形成通孔延伸部165。在一些實施例中，在沈積通孔延伸部165之前，可在開口中及接合層160上方沈積晶種層及/或障壁層。通孔延伸部165的材料可在開口上方突出且超過接合層160。在沈積通孔延伸部165的材料之後，可使用諸如CMP的平坦化技術以使通孔延伸部165與接合層160齊平。在一些實施例中，通孔延伸部165可比通孔120更寬，從而形成焊墊區域。
在實施例中，在晶圓上晶圓或晶片上晶圓接合製程中，晶圓100及/或晶粒112可具有與其接合的晶圓或晶圓堆疊。在使用晶圓堆疊的實施例中，晶圓堆疊可單獨形成，且以預先形成的晶圓堆疊形式接合至晶圓100及/或晶粒112上。下文將描述這些實施例。
在圖11中，示出根據一些實施例的具有若干晶粒212的晶圓200的俯視圖。晶粒212可經配置以各自包含相同晶粒功能或不同晶粒功能。在一些實施例中，晶粒212可形成為邏輯晶粒，諸如CPU晶粒、MCU晶粒、IO晶粒、BB晶粒、AP晶粒、SoC、SoIC或類似物。在其他實施例中，晶粒212中的一或多者可為記憶體晶粒，諸如DRAM晶粒或SRAM晶粒或類似物。在所示出的實施例中，晶圓200中的多者可堆疊以形成記憶體元件堆疊。晶粒212中的每一者之間為切割道211，所述切割道211經指派用於在後續製程中使晶粒212單體化。晶粒212可理解為封裝區域，且切割道211可理解為非封裝區域。一般而言，無主動元件或被動元件形成於切割道211中，且因此，切割道211不含主動元件或被動元件。
在圖12中，示出晶圓200的一部分的橫截面視圖。在所示出的部分中，第一晶粒212及第二晶粒212予以示出，且由切割道211分離。為簡單起見，已省略細節。應理解，關於晶粒212的圖示是出於說明目的，且不應被視為受限於特定配置。
晶粒212可包含具有形成於其中的一或多個被動元件的基底215。基底215可由與上文關於基底115所論述的材料類似的材料形成，且不重複論述。
晶圓200包含晶粒212中的每一者的元件區210。元件區210可與元件區110類似，其中元件區210及元件區110可包含嵌入式元件，諸如電晶體；或其他主動元件，諸如二極體；以及可能存在的被動元件，諸如電容器、電感器、電阻器或類似物。在元件區210上方為內連線結構230，所述內連線結構230使元件互連，且將輸入/輸出信號路由至元件。內連線結構230可使用與上文所描述的內連線結構130類似的材料及製程形成。特定言之，內連線結構230可包含若干ILD層，所述ILD層包含最上部ILD層，所述最上部ILD層自身可包含諸如上文與介電層132一起描述的多個層。
在圖13中，通孔開口219可形成為穿過內連線結構230且進入基底215中。在一些實施例中，通孔開口可暴露出內連線結構230的金屬特徵以用於耦接至元件區210中的主動元件及/或被動元件。通孔開口219中的一或多者可不暴露出內連線結構230的金屬特徵，以使得隨後形成於通孔開口219中的通孔材料不耦接至元件區210中的元件中的任一者，且可被視為虛設通孔。通孔開口219可使用微影製程使用例如在內連線結構230的上部介 電層上方形成及圖案化的光阻及/或硬式罩幕形成。非等向性蝕刻可用以形成穿過光阻及/或硬式罩幕的通孔開口。通孔開口219可以任何合適的圖案形成於基底215中。
在圖14中，根據一些實施例，通孔220的材料可形成於內連線結構230上方。通孔220可藉由與上文所描述的形成內連線結構130的通孔類似的製程形成，但可使用其他合適的製程。舉例而言，晶種層可沈積於通孔開口219中，且可藉由例如電鍍、化學鍍、PVD、CVD或類似操作在通孔開口219中在晶種層上沈積導電材料來形成通孔220。在一些實施例中，可同時形成接觸墊225(參見圖16)。通孔220可由銅或銅合金形成，且其亦可由其他金屬形成。用於通孔220的材料可在通孔開口219上方突出，且覆蓋內連線結構230的部分。
在圖15中，平坦化或研磨製程可用以使通孔220的上部表面與內連線結構230的上部表面齊平。在圖16中，形成接觸墊225。接觸墊225a物理且電性耦接至通孔220，且接觸墊225b不物理耦接至通孔220，而是可物理且電性耦接至內連線結構230中的金屬線。如此，接觸墊225b亦可經由內連線結構230電性耦接至通孔220。可使用任何合適的製程形成接觸墊225。舉例而言，抗蝕劑層可經沈積及圖案化以形成對應於接觸墊225的開口。晶種層可沈積於開口中及抗蝕劑層上方。接著，接觸墊225可使用任何合適的製程進行沈積，且接著可視需要予以齊平。最後，可移除抗蝕劑層，此亦移除抗蝕劑層上方的晶種層及沈積於晶種層上的任何金屬。在另一實施例中，接觸墊225亦可藉由形成導電材料的毯覆式層來沈積且蝕刻以移除導電材料的將不保留的部 分。
在另一實施例中，介電層可沈積於以下各者上方：內連線結構230、形成於對應於接觸墊225的介電層中的開口、沈積於開口中的晶種層以及沈積於開口中的晶種層上的接觸墊225的材料。接著，平坦化製程可提供平坦上部表面。
在圖17中，介電層235沈積於接觸墊225上方。在一些實施例中，介電層235(或其子層)可對應於用以輔助形成接觸墊225的介電層。介電層235的厚度可比接觸墊225的厚度大0奈米與50奈米之間。換言之，在一些實施例中，介電層235可比接觸墊225更厚，而在其他實施例中，介電層235可具有與接觸墊225的上部表面齊平的上部表面。
亦在圖17中，介電層240可沈積於接觸墊225上方作為接合結構260(參見圖19)的部分。介電層235及介電層240可包含任何合適的介電材料，諸如氧化矽、氮化矽、氮氧化矽、碳氧化矽、氮碳氧化矽或類似物，且可使用任何合適的製程形成。舉例而言，介電層235及介電層240可藉由CVD、PECVD或ALD沈積製程、FCVD或旋塗玻璃製程形成。
在圖18中，形成接合墊通孔245。可使用與上文所描述的通孔220類似的製程及材料形成接合墊通孔245。在另一實施例中，接合墊通孔245可與接合墊255同時形成(參見圖19)。
在圖19中，接合層250沈積於介電層240上方。接合墊255形成於接合層250中。可使用上文關於接觸墊225所描述的材料及製程中的任一種來形成接合墊。在一些實施例中，在形成接合墊通孔245之前形成接合層250。接著，可藉由在對應於接合墊 255的接合層250中形成開口且接著在對應於接合墊通孔245的介電層240中形成開口而同時形成接合墊通孔245及接合墊255。接著，障壁層可同時沈積於接合墊通孔245及接合墊255兩者的開口中，隨後沈積接合墊255的導電材料。最後，可藉由使接合墊255及接合層250的上部表面齊平的平坦化或研磨製程移除任何過量導電材料。
在一些實施例中，接合層250可由任何合適的材料形成，且可在約0.8微米與約3微米之間，但可使用其他尺寸。在一些實施例中，接合層250可由以下各者形成：氧化物，諸如氧化矽；或氮化物，諸如氮化矽；或聚醯亞胺；或類似物。在一些實施例中，接合層250可由與用於形成接合層160的材料相同的材料形成。接合層250用以在晶圓至晶圓接合製程中與另一接合層250形成融合接合。類似製程亦可用以在接合層250與接合層160之間形成融合接合(參見圖7及圖9)。
在圖20a中，晶圓200翻轉且接合至例如圖7或圖10的晶圓100。所使用接合技術可為混合接合(hybrid bonding)技術，其中晶圓100的接合層160與晶圓200的接合層250藉由融合接合而融合在一起，且接合墊255藉由直接金屬至金屬接合而一起直接接合至通孔120而不使用介接接合材料，諸如焊料或其他共熔材料(eutectic material)。混合接合具有在兩個已接合連接件之間不需要焊料材料的益處。混合接合在兩個元件之間形成接合界面，所述接合界面包含第一元件中的金屬特徵與第二元件中的金屬特徵的直接金屬至金屬接合，以及第一元件中的絕緣材料與第二元件中的絕緣材料的融合接合(或介電質至介電質接合)。可使 用任何合適的混合接合製程。
在混合接合製程中，接合墊255及接合層250對準且與晶圓100的通孔120及接合層160接觸。隨後，可執行退火以將導電材料直接接合在一起且將絕緣材料融合接合在一起。退火促使接合墊255及通孔120中的金屬相互擴散以產生直接金屬至金屬接合。退火亦促使接合層250融合接合至接合層160，其中接合層250與接合層160藉由在兩個層之間形成化學鍵而處於直接接觸。舉例而言，接合層160及接合層250的絕緣材料中的一者中的原子(諸如氧原子)可與接合層160及接合層250中的另一者中的原子(諸如氫原子)形成化學鍵或共價鍵(諸如O-H鍵)。接合層160與接合層250之間的所得接合為絕緣層至絕緣層接合。可經由退火製程克服接合結構的表面的微小變化，同時壓力使結構保持在一起。在一些實施例中，可施加約1牛頓(Newton)至10牛頓的按壓力以將接合墊255及通孔120按壓在一起，且將接合層250及接合層160按壓在一起。其他實施例可不利用按壓力。混合接合製程可在約1標準大氣壓至約100標準大氣壓(諸如約5標準大氣壓)的環境中執行。材料在退火溫度下的膨脹可完成接合且實質上消除空隙。
視接合層160及接合層250的材料的韌性(robustness)而定，混合接合製程中的退火溫度可在約150℃與約400℃之間。在接合層160及接合層250兩者皆由諸如氧化物或氮氧化物的無機介電材料形成的實施例中，退火溫度可在約150℃與約400℃之間。用於混合接合製程的退火時間可在約0.5小時與5小時之間。
藉由形成專門用於將晶圓200接合至晶圓100的接合層 160及接合層250，可形成較佳融合接合。特定言之，接合層160及接合層250的厚度在約0.8微米與3微米之間或大於3微米提供充足的接合層厚度以允許化學鍵結出現。出於若干原因，0.8微米的最小目標厚度至關重要。所述厚度為兩個接合層160及250的層厚度變化提供一定容差。歸因於層厚度變化，當兩個接合層160與250配合在一起時，可觀測到兩個層之間的一些空隙。在約0.8微米的最小厚度下，接合層160及接合層250可在退火時各自豎直膨脹，從而有助於填充此類空隙。最小0.8微米厚度亦為接合層160與接合層250之間的接合形成提供充足機會。換言之，在退火製程期間，化學鍵或共價鍵可形成於接合層160中的材料與接合層250中的材料之間。具有約0.8微米的最小厚度提供足夠的接合材料，以使得接合層160及接合層250中的每一者中的局部接合可斷裂且重新形成至相對的接合層160及250的交叉接合(crossbonds)。最小0.8微米厚度亦提供充足材料以經受住若干退火循環。如上文所提及且在下文後續論述中，在不同結構於退火製程中接合在一起之後，後續結構(例如晶圓200或晶圓堆疊300或晶圓堆疊400)亦可在後續退火製程中接合。如上文所論述，每一退火製程可在0.5小時與5小時之間。如此，接合層160及接合層250必須經受住若干退火製程。接合層160及接合層250具有約0.8微米的最小厚度提供合適的韌性來經受住這些退火循環。應注意，視接合層160及接合層250的材料而定，一些實施例涵蓋其他厚度，包含小於0.8微米的厚度。亦應理解，總厚度的變化可導致接合層160及接合層250的厚度在一些區域中小於0.8微米。
接合墊255及通孔120的已接合導電材料可具有可辨識 的界面。亦即，即使在接合之後，吾人亦可能夠觀測到界面且判定接合墊255及通孔120單獨形成且接合在一起。類似地，接合層250及接合層160的接合絕緣材料亦可具有可識別的界面。
圖20a包含接合界面的放大(擴大)部分。在此放大部分中，將障壁層221示出為環繞通孔220。類似地，將障壁層121示出為環繞通孔120，且將障壁層246示出為環繞接合墊通孔245。
圖20b示出諸如圖3b及圖3d中所提供的混合接合製程，其中底部結構不面向下而是面向上。特定言之，圖20b包含圖3d中所示出的結構作為底部結構。圖20b的放大部分示出在混合接合製程之後的接合墊至接合墊金屬至金屬接合以及接合層250與介電層132的融合接合。放大部分亦示出包含內連線結構130中的金屬線及通孔的金屬特徵131，一些通孔120可電性且物理耦接至內連線結構130中的金屬特徵131，而其他通孔可並不如此。儘管示出圖3d中的結構，但放大部分將可適用於圖3b或圖3d中的結構。
在圖21中，使用任何合適的製程來薄化晶圓200。薄化可藉由CMP製程、研磨、蝕刻或其他合適的製程來進行。薄化暴露出晶粒212中的通孔220，且亦減小晶粒212的厚度以提供較佳熱耗散且佔據較小空間。在薄化之後，晶圓200及晶粒212的厚度可為約2微米至500微米，例如厚度在約10微米與50微米之間。在一些實施例中，晶圓200基底215的頂部表面與通孔220的頂部表面彼此齊平。
在圖22至圖24中，根據實施例，晶圓200準備藉由添加反向接合層265(圖24)來接收與其接合的另一晶圓。在一些 實施例中，諸如圖22中所示出，晶圓200的基底215可凹陷以暴露出通孔220的上部側壁。此製程可與上文關於使圖5的基底115凹陷所描述的製程類似。特定言之，基底可凹陷0.8微米至約3微米的深度，或換言之，通孔220可自基底215突出0.8微米至約3微米。在圖23中，反向接合層265可沈積於暴露通孔220上方。可使用與上文關於圖6的接合層160所描述的製程及材料類似的製程及材料來沈積反向接合層265。在圖24中，反向接合層265可藉由CMP或研磨製程來平坦化，以使反向接合層265的上部表面與通孔220的上部表面齊平。此製程可與上文關於圖7的接合層160及通孔120所描述的製程類似。
在其他實施例中，基底215可不凹陷，且與上文關於圖8所描述的接合層160類似，反向接合層265可沈積於基底215及暴露通孔220上方。接著，與上文關於圖9所描述的製程類似，可在反向接合層265中形成開口。接著，可在開口中形成通孔延伸部，且與上文關於圖10所描述的製程類似，通孔延伸部的上部表面與反向接合層265的上部表面齊平。
在圖25中，根據一些實施例，晶圓200變為晶圓200a，且另一晶圓200b接合至晶圓200a。晶圓200b可使用諸如上文關於圖20a所描述的混合接合技術接合至晶圓200a。藉由每一後續混合接合技術，已使用混合接合技術接合的結構可使其接合強度隨著執行接合退火而增加。如此，在一些實施例中，不同結構之間的接合強度可不同。
在圖26中，可對晶圓200b重複諸如上文關於圖21至圖24所描述的薄化製程及反向接合層265的形成，且多達晶圓200n 的額外晶圓200可使用如上文關於圖20a所描述的混合接合技術進行堆疊及接合。晶圓200的總數目可在約1與16之間或大於16。在一些實施例中，可按最小接合退火時間(諸如在30分鐘與60分鐘之間)接合每一晶圓200，直至接合最末晶圓200n為止，其中接合退火時間增加，藉此增加已接合結構的接合強度，同時減少總處理時間。在一些實施例中，首先接合晶圓之間的接合強度將大於隨後接合的晶圓。舉例而言，晶圓200a與晶圓200b之間的接合強度可最大，接著為晶圓200b與晶圓200c之間的接合強度，以此類推。
圖27至圖30示出根據一些實施例的形成可用以貼附至晶圓100的雙層晶圓堆疊300的製程。在圖27中，圖19的晶圓200藉由釋放層310貼附至載板基底305作為晶圓200a。載板基底305及釋放層310可由與上文關於圖3a、圖3b、圖3c以及圖3d所描述的載板基底190及釋放層150類似的材料形成。在圖28中，可執行上文關於圖21至圖24所描述的製程以薄化晶圓200a，且形成晶圓200a的反向接合層265。
在圖29中，藉由混合接合製程將第二晶圓200b接合至第一晶圓200a，諸如上文關於圖20a所描述。在圖30中，可移除載板基底305，藉此形成雙層晶圓堆疊300。可藉由將UV輻射施加至釋放層310、機械研磨製程、回蝕製程、加熱製程、其組合或類似操作來移除載板基底305。
在圖31中，雙層晶圓堆疊300接合至例如圖10的晶圓100。可使用諸如上文關於圖20a所描述的混合接合製程將雙層晶圓堆疊300接合至晶圓100。
在圖32中，雙層晶圓堆疊300變為晶圓堆疊300a，且可將接合雙層晶圓堆疊300的製程重複所要次數以將總共n個雙層晶圓堆疊300接合至晶圓100。晶圓200的總數目為n的2倍。在接合每一額外雙層晶圓堆疊300之前，可處理先前雙層晶圓堆疊300以薄化雙層晶圓堆疊300的最上部晶圓200且形成反向接合層265，諸如上文關於圖21至圖24所描述。在一些實施例中，可按最小接合退火時間(諸如在30分鐘與60分鐘之間)接合每一晶圓堆疊300，直至接合最末晶圓堆疊300n為止，其中接合退火時間增加，藉此增加已接合結構的接合強度，同時減少總處理時間。在一些實施例中，每一雙層晶圓堆疊300之間的接合強度將大於隨後接合的晶圓堆疊。舉例而言，晶圓堆疊300a與晶圓堆疊300b之間的接合強度可最大，接著為晶圓堆疊300b與晶圓堆疊300c之間的接合強度，以此類推。另外，在一些實施例中，晶圓堆疊300內的個別晶圓200之間的接合強度大於晶圓堆疊300之間的接合強度。
在圖33中，根據一些實施例，四層晶圓堆疊400由包含晶圓200a、晶圓200b、晶圓200c以及晶圓200d的個別晶圓200形成。可藉由繼續將額外晶圓200添加至例如圖29的結構的製程來形成四層晶圓堆疊400。在接合每一額外晶圓200之前，可處理先前晶圓200以薄化晶圓200且形成反向接合層265，諸如上文關於圖21至圖24所描述。在一些實施例中，可按最小接合退火時間(諸如在30分鐘與60分鐘之間)接合每一晶圓200，直至接合最末晶圓200d為止，其中接合退火時間增加，藉此增加已接合結構的接合強度，同時減少總處理時間。
在圖34中，根據一些實施例，四層晶圓堆疊400由雙層晶圓堆疊300形成。可藉由將額外雙層晶圓堆疊300(參見圖30)添加至例如圖29的結構來形成圖34的四層晶圓堆疊400。在另一實施例中，例如圖30的雙層晶圓堆疊300可貼附至載板基底，隨後為另一雙層晶圓堆疊300或接合至第一雙層晶圓堆疊300的兩個晶圓200。在另一實施例中，雙層晶圓堆疊300可接合至晶圓200(例如圖28的結構)，隨後為另一晶圓200。在接合每一額外晶圓200或雙層晶圓堆疊300之前，可處理先前晶圓200或雙層晶圓堆疊300的上部晶圓200以薄化晶圓200且形成反向接合層265，諸如上文關於圖21至圖24所描述。
在圖35中，可移除載板基底405，藉此形成四層晶圓堆疊400。四層晶圓堆疊400接合至例如圖10的晶圓100。四層晶圓堆疊400可使用諸如上文關於圖20a所描述的混合接合製程接合至晶圓100。
在圖36中，四層晶圓堆疊400變為晶圓堆疊400a，且可將接合四層晶圓堆疊400的製程重複所要次數，以將總共n個四層晶圓堆疊400接合至晶圓100。晶圓200的總數目為n的4倍。在接合每一額外四層晶圓堆疊400之前，可處理先前四層晶圓堆疊400以薄化四層晶圓堆疊400的最上部晶圓200且形成反向接合層265，諸如上文關於圖21至圖24所描述。在一些實施例中，可按最小接合退火時間(諸如在30分鐘與60分鐘之間)接合每一晶圓堆疊400，直至接合最末晶圓堆疊400n為止，其中接合退火時間增加，藉此增加已接合結構的接合強度，同時減少總處理時間。在一些實施例中，每一四層晶圓堆疊400之間的接合強度 將大於隨後接合的晶圓堆疊400。舉例而言，晶圓堆疊400a與晶圓堆疊400b之間的接合強度可最大，接著為晶圓堆疊400b與晶圓堆疊400c之間的接合強度，以此類推。另外，在一些實施例中，每一晶圓堆疊400內的個別晶圓200之間的接合強度大於晶圓堆疊400之間的接合強度。
在圖37a、圖37b、圖37c以及圖37d中，呈任何數目及呈任何次序的晶圓200、雙層晶圓堆疊300及/或四層晶圓堆疊400的任何組合可接合至自圖3a及圖3b流程的晶圓100或自圖3c及圖3d流程的晶圓100'。應注意，在圖37b及圖37d中，介電層132可與接合層160同義。在一些實施例中，可修改晶圓100'以藉由以下操作在間隙填充材料155上方添加上部接合層160：使間隙填充材料155凹陷，且在移除間隙填充材料155之處沈積接合層160。在其他實施例中，可修改晶圓100'以藉由以下操作在間隙填充材料155上方添加上部接合層160：在間隙填充材料155上方及晶粒112上方沈積接合層160，在接合層160中形成暴露出接觸墊125的開口，以及使接觸墊125延伸穿過接合層160中的開口。上文關於圖5及圖6以及圖8至圖10描述這些製程，且可視需要根據所述實施例修改這些製程。
在一些實施例中，可按最小接合退火時間(諸如在30分鐘與60分鐘之間)接合每一晶圓200、雙層晶圓堆疊300或四層晶圓堆疊400，直至接合最末晶圓200或晶圓堆疊300或晶圓堆疊400為止，其中接合退火時間增加，藉此增加已接合結構的接合強度，同時減少總處理時間。
可由單一晶圓200、雙層晶圓堆疊300以及四層晶圓堆疊 400的組合判定晶圓200的總數目。舉例而言，晶圓200的總數目可在一個晶圓200與約二十個晶圓200之間。在接合每一額外晶圓200、雙層晶圓堆疊300或四層晶圓堆疊400之前，可處理先前晶圓200、雙層晶圓堆疊300或四層晶圓堆疊400以薄化最上部晶圓200且形成反向接合層265，諸如上文關於圖21至圖24所描述。
在一實施例中，每一晶圓200可為記憶體晶圓，且晶圓200的堆疊可構成記憶體立方體。記憶體立方體可包含例如八個晶圓200。在一些實施例中，可包含超過晶圓200的設計數目的一或多個額外晶圓200，以在晶圓200中的一或多者測試不良的情況下提供備用容量。舉例而言，在一實施例中，九個晶圓200可接合至晶圓100或晶圓100'，所述晶圓100或晶圓100'可為記憶體控制器。當判定九個晶圓200中的一者有缺陷時，記憶體控制器可經程式化以略過有缺陷的晶圓200而不損失整個記憶體/控制器組合的功能性。
在一些實施例中，晶圓200的不同層中的一或多者可具有不同功能性。
在圖38a中，在薄化最上部晶圓200(亦即晶圓200n)之後，移除載板基底190，使封裝500彼此單體化，且在晶圓100/100'的前側上形成連接件515。可以任何合適的次序執行這些製程。在一些實施例中，移除載板基底190，形成連接件515，且接著使封裝500單體化。在其他實施例中，在載板基底190上使封裝500單體化，接著移除載板基底190，且形成連接件515。下文更詳細地描述這些製程。
圖38a中亦示出視情況選用的熱界面材料(thermal interface material；TIM)540及熱耗散結構550，其在下文更詳細地予以描述。圖38a亦包含視情況選用的重佈線結構530，所述重佈線結構530可使用與上文關於內連線結構130所描述的材料及製程類似的材料及製程形成，所述材料及製程不重複論述。
可使用任何合適的切割技術560來使封裝500單體化。切割技術560可包含使用合適的蝕刻劑的乾式蝕刻、濕式蝕刻、非等向性蝕刻或電漿蝕刻。切割技術560可包含雷射，所述雷射進行多次穿經以使封裝500彼此雷射分割。切割技術560可包含機械製程，諸如經設定以切割至所要深度的鋸。亦可使用上述切割技術560的組合。單體化經由非封裝區(封裝500區域之外，參見例如圖1的切割道111及圖11的切割道211)進行。單體化切割穿過經處理晶圓堆疊，向下達至釋放層150。在一些實施例中，單體化可繼續穿過釋放層150，且可繼續進入或穿過載板基底190。
連接件515形成於晶圓100的前側上。連接件515可使用任何合適的製程來形成，且包括各種配置。在一些實施例中，連接件515可為受控塌陷晶粒連接(controlled collapse chip connection；C4)凸塊、微凸塊、焊球或類似物。舉例而言，開口(未示出)可在沈積於晶圓100的前側上的鈍化層中形成，開口暴露出金屬特徵，諸如晶圓100的接觸墊125或視情況選用的重佈線結構530的金屬線。連接件515形成於開口中。在一些實施例中，凸塊下金屬(under bump metallurgy；UBM)層可在連接件515形成之前形成於開口中。在所示出的實施例中，連接件515具有包括導電材料的下部部分505(較接近於晶圓100)及包括焊 料材料的上部部分510(較遠離晶圓100)。下部部分505及上部部分510亦可分別稱為導電柱505及焊蓋510。
連接件515可藉由通孔120/220、接合墊通孔245以及內連線結構130、內連線結構230及/或內連線結構530耦接至晶圓100的導電特徵，且亦耦接至晶圓200a至200n中的各種晶圓。
視情況選用的熱界面材料(thermal interface material，TIM)540形成於封裝500上方。TIM 540為具有良好熱導率的材料，所述熱導率可大於約5瓦特/(米．克耳文)，且可等於或高於約50瓦特/(米．克耳文)或100瓦特/(米．克耳文)。視情況選用的熱耗散結構550可由TIM 540貼附，所述TIM 540亦可具有黏著品質。熱耗散結構550具有高熱導率，且可使用金屬、金屬合金或類似物形成。舉例而言，熱耗散結構550可包括金屬，諸如Al、Cu、Ni、Co以及類似物，或其合金。熱耗散結構550亦可由選自由以下各者組成的群組的複合材料形成：碳化矽、氮化鋁、石墨以及類似物。熱耗散結構550可用以經由接合的晶圓100/100'以及晶圓200中的每一者耗散熱量。晶圓100/100'的通孔120(穿孔)及晶圓200的通孔220(穿孔)可有效耗散由元件區110(參見圖2)及/或元件區210(參見圖12)產生的熱量。若通孔120(穿孔)與通孔220(穿孔)對準(諸如所示出)，則熱耗散效率可增加。然而，實施例亦涵蓋：視元件區110及元件區210的設計以及內連線結構130及內連線結構230中的金屬線及通孔的佈線而定，視需要可不對準或可省略通孔120及通孔220。
除晶圓100/100'面向上以使得晶圓的背側面向下(諸如在圖37b及圖37d中所示出)之外，圖38b與圖38a類似。在此類 實施例中，可移除載板基底190，且薄化晶圓100的基底115以暴露出通孔120。接著，可形成重佈線結構530以視需要在晶圓100/100'的背部或封裝500的前部處路由通孔120。重佈線結構530可使用與上文關於圖2所描述的內連線結構130類似的製程及材料形成。接著可使封裝500單體化，形成連接件515，形成TIM 540，且以與上文關於圖38a所描述的方式類似的方式施以熱耗散結構550。
圖38a及圖38b亦提供示出來自圖37a、圖37b、圖37c以及圖37d的晶圓100及晶圓100'兩者的晶圓100/100'的組合視圖。特定言之，間隙填充材料155示出於圖38a及圖38b的左半部分(跟隨圖37c及圖37d)上，而間隙填充材料155在圖38a及圖38b的右半部分(跟隨圖37a及圖37b)上不使用。
實施例包含晶圓至晶圓混合接合堆疊製程，以在形成具有多個功能的封裝元件中提供較大靈活性。為達成晶圓至晶圓的高品質接合，接合層可形成於鄰接片件上以在接合層之間提供融合接合，此比其他接合製程更不易於失效。晶圓的金屬特徵可藉由提供大於鄰接金屬特徵的目標接觸區域(例如接觸墊)而靈活對準，所述鄰接金屬特徵可為例如穿孔的一部分。另外，諸如穿孔的金屬特徵可用以貫穿整個封裝結構路由信號及/或耗散熱量。
一個實施例為一種方法，包含薄化第一晶圓以暴露出金屬通孔。在金屬通孔上方形成接合層，金屬通孔延伸穿過接合層。將第二晶圓定位至第一晶圓，其中第二晶圓的接合墊對準至第一晶圓的金屬通孔，且在於第二晶圓的接合墊與第一晶圓的金屬通孔之間不使用接合材料的情況下，使第二晶圓的接合墊與第一晶 圓的金屬通孔接合。第一晶圓的接合層融合至第二晶圓的接合層。在一實施例中，形成接合層可包含：使環繞金屬通孔的第一材料凹陷；沈積對應於接合層的第二材料；以及使第二材料平坦化，以使第二材料的上部表面與金屬通孔的上部表面齊平。在一實施例中，形成接合層可包含：在金屬通孔上方沈積接合層；在接合層中形成開口，開口對應於金屬通孔；在開口中沈積金屬通孔延伸部，金屬通孔延伸部物理耦接至金屬通孔；以及使金屬通孔延伸部平坦化，以使接合層的上部表面與金屬通孔延伸部的上部表面齊平。在一實施例中，第一晶圓及第二晶圓一同形成第一晶圓堆疊，且方法可更包含：將第一晶圓堆疊定位至第三晶圓，其中第一晶圓的接合墊對準至第三晶圓的金屬特徵；在於第一晶圓的接合墊與第三晶圓的金屬特徵之間不使用接合材料的情況下，使第一晶圓的接合墊與第三晶圓的金屬特徵接合；以及使第一晶圓的接合層融合至第三晶圓的接合層。在一實施例中，第一晶圓可包含用於控制第一晶圓堆疊中的元件的控制器。在一實施例中，第一晶圓面向下且第三晶圓面向上，第三晶圓的表面接合至第一晶圓的表面。在一實施例中，方法可包含：自第一晶圓及第二晶圓使堆疊元件封裝單體化。在一實施例中，第一晶圓及第二晶圓一同形成第一晶圓堆疊，且方法可更包含：形成可包含雙層晶圓堆疊的第二晶圓堆疊；薄化第二晶圓，以暴露出第一晶圓堆疊的第二金屬通孔；在第二金屬通孔上方形成第二接合層，第二金屬通孔延伸穿過第二接合層；將第二晶圓堆疊定位至第一晶圓堆疊，其中第二晶圓堆疊的接合墊對準至第二金屬通孔；在於第二晶圓堆疊的接合墊與第一晶圓堆疊的第二金屬通孔之間不使 用接合材料的情況下，使第二晶圓堆疊的接合墊與第一晶圓堆疊的第二金屬通孔接合；以及使第二接合層融合至第二晶圓堆疊的接合層，以形成第一四級晶圓堆疊。在一實施例中，方法包含：將第一四級晶圓堆疊定位至第三晶圓，其中第一四級晶圓堆疊的接合墊對準至第三晶圓的金屬特徵；在於第一四級晶圓堆疊的接合墊與第三晶圓的金屬特徵之間不使用接合材料的情況下，使第一四級晶圓堆疊的接合墊接合至第三晶圓的金屬特徵；以及使第一四級晶圓堆疊的接合層融合至第三晶圓的接合層。在一實施例中，第一四級晶圓堆疊中的晶圓中的每一者面向下。在一實施例中，第一晶圓的接合層的厚度為0.8微米與3微米之間。
另一實施例為一種封裝，包含第一元件、第二元件以及第三元件。第一元件可包含第一組通孔、第一主動元件以及第一內連線結構，第一組通孔自第一元件的前部橫穿第一內連線結構達至第一元件的背部，第一主動元件鄰接第一內連線結構。第二元件可包含第二組通孔、第二主動元件、第二內連線結構、第二前向接合層以及第二反向接合層，第二反向接合層在第二元件的背側上，第二反向接合層可包含第一介電材料，第二前向接合層接合至第一元件，其中第二組通孔自第二前向接合層橫穿第二反向接合層。第三元件可包含第三組通孔、第三主動元件、第三內連線結構以及第三前向接合層，第三前向接合層可包含與第一介電材料相同的介電材料，其中第三組通孔自第三前向接合層橫穿第三元件達至第三元件的背側，其中第二反向接合層接合至第三前向接合層。在一實施例中，第三前向接合層可包含一組接合墊通孔及一組接合墊，其中接合墊中的每一者具有與第二組通孔中 的對應通孔的界面。在一實施例中，封裝可包含：熱界面材料，安置於第三元件上，熱界面材料與第三組通孔接觸；以及熱耗散特徵，安置於熱界面材料上方。在一實施例中，第一元件由間隙填充材料側向環繞，其中第二前向接合層與間隙填充材料交疊。在一實施例中，第一元件更可包含電性耦接至第一組通孔的第一組接合墊，其中第一組接合墊直接接合至安置於第二前向接合層上的第二接合墊。在一實施例中，第二前向接合層及第二反向接合層各自的厚度在0.8微米與3微米之間。
另一實施例為一種封裝組件，包含：第一晶圓，接合至第二晶圓，其中在接合界面處，第一晶圓的金屬通孔直接接合至第二晶圓的接合墊，且第一晶圓的第一接合層融合至第二晶圓的第二接合層，第一接合層安置於第一晶圓的背側處，第一晶圓的金屬通孔橫穿第一接合層，穿過半導體基底，且穿過第一晶圓的第一內連線。在一實施例中，封裝組件可包含：第三晶圓；第三晶圓的第四接合層接合至第二晶圓的第三接合層；以及第四晶圓，第四晶圓的第六接合層接合至第三晶圓的第五接合層。在一實施例中，第一晶圓、第二晶圓、第三晶圓以及第四晶圓中的每一者面向下。在一實施例中，第二晶圓的接合墊經由第二接合層藉由接合墊通孔耦接至第二晶圓的第二內連線。在一實施例中，第一接合層的第一介電材料與第二接合層的第二介電材料相同，且第一接合層及第二接合層各自的厚度在0.8微米與3微米之間。
前文概述若干實施例的特徵，以使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實施本文中所引 入實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100、200:晶圓
115、215:基底
120、220:通孔
121、221、246:障壁層
225:接觸墊
230:內連線結構
235、240:介電層
160、250:接合層
190:載板基底
245:接合墊通孔
255:接合墊

Claims (10)

  1. 一種製造方法，包括：薄化第一晶圓，以暴露出金屬通孔；在所述金屬通孔上方形成接合層，所述金屬通孔延伸穿過所述接合層；將第二晶圓定位至所述第一晶圓，其中所述第二晶圓的接合墊對準至所述第一晶圓的所述金屬通孔；在於所述第二晶圓的所述接合墊與所述第一晶圓的所述金屬通孔之間不使用接合材料的情況下，使所述第二晶圓的所述接合墊與所述第一晶圓的所述金屬通孔接合；以及使所述第一晶圓的所述接合層融合至所述第二晶圓的接合層，使所述第一晶圓的所述接合層及所述第二晶圓的所述接合層中之間形成化學鍵。
  2. 如請求項1所述的製造方法，其中形成所述接合層包括：使環繞所述金屬通孔的第一材料凹陷；沈積對應於所述接合層的第二材料；以及使所述第二材料平坦化，以使所述第二材料的上部表面與所述金屬通孔的上部表面齊平。
  3. 如請求項1所述的製造方法，其中形成所述接合層包括：在所述金屬通孔上方沈積所述接合層；在所述接合層中形成開口，所述開口對應於所述金屬通孔；在所述開口中沈積金屬通孔延伸部，所述金屬通孔延伸部物 理耦接至所述金屬通孔；以及使所述金屬通孔延伸部平坦化，以使所述接合層的上部表面與所述金屬通孔延伸部的上部表面齊平。
  4. 如請求項1所述的製造方法，其中所述第一晶圓及所述第二晶圓一同形成第一晶圓堆疊，所述方法更包括：將所述第一晶圓堆疊定位至第三晶圓，其中所述第一晶圓的接合墊對準至所述第三晶圓的金屬特徵；在於所述第一晶圓的所述接合墊與所述第三晶圓的所述金屬特徵之間不使用接合材料的情況下，使所述第一晶圓的所述接合墊與所述第三晶圓的所述金屬特徵接合；以及使所述第一晶圓的接合層融合至所述第三晶圓的接合層。
  5. 如請求項1所述的製造方法，其中所述第一晶圓及所述第二晶圓一同形成第一晶圓堆疊，所述方法更包括：形成包括雙層晶圓堆疊的第二晶圓堆疊；薄化所述第二晶圓，以暴露出所述第一晶圓堆疊的第二金屬通孔；在所述第二金屬通孔上方形成第二接合層，所述第二金屬通孔延伸穿過所述第二接合層；將所述第二晶圓堆疊定位至所述第一晶圓堆疊，其中所述第二晶圓堆疊的接合墊對準至所述第二金屬通孔；在於所述第二晶圓堆疊的所述接合墊與所述第一晶圓堆疊的所述第二金屬通孔之間不使用接合材料的情況下，使所述第二晶圓堆疊的所述接合墊與所述第一晶圓堆疊的所述第二金屬通孔接合；以及 使所述第二接合層融合至所述第二晶圓堆疊的接合層，以形成第一四級晶圓堆疊。
  6. 一種半導體封裝，包括：第一元件，所述第一元件包括第一組通孔、第一主動元件以及第一內連線結構，所述第一組通孔自所述第一元件的前部橫穿所述第一內連線結構達至所述第一元件的背部，所述第一主動元件鄰接所述第一內連線結構；第二元件，所述第二元件包括第二組通孔、第二主動元件、第二內連線結構、第二前向接合層以及第二反向接合層，所述第二反向接合層在所述第二元件的背側上，所述第二反向接合層包括第一介電材料，所述第二前向接合層接合至所述第一元件，其中所述第二組通孔自所述第二前向接合層橫穿所述第二反向接合層；以及第三元件，所述第三元件包括第三組通孔、第三主動元件、第三內連線結構以及第三前向接合層，所述第三前向接合層包括與所述第一介電材料相同的介電材料，其中所述第三組通孔自所述第三前向接合層橫穿所述第三元件達至所述第三元件的背側，其中所述第二反向接合層接合至所述第三前向接合層，且所述第二反向接合層與所述第三前向接合層直接接觸。
  7. 如請求項6所述的半導體封裝，其中所述第一元件由間隙填充材料側向環繞，其中所述第二前向接合層與所述間隙填充材料交疊。
  8. 一種封裝組件，包括：第一晶圓，接合至第二晶圓，其中在接合界面處，所述第一 晶圓的金屬通孔直接接合至所述第二晶圓的接合墊，且所述第一晶圓的第一接合層融合至所述第二晶圓的第二接合層，其中所述第一晶圓的所述第一接合層及所述第二晶圓的所述第二接合層之間形成化學鍵，所述第一接合層安置於所述第一晶圓的背側處，所述第一晶圓的所述金屬通孔橫穿所述第一接合層，穿過半導體基底，且穿過所述第一晶圓的第一內連線。
  9. 如請求項8所述的封裝組件，其中所述第二晶圓的所述接合墊經由所述第二接合層藉由接合墊通孔耦接至所述第二晶圓的第二內連線。
  10. 如請求項8所述的封裝組件，其中所述第一接合層的第一介電材料與所述第二接合層的第二介電材料相同；且其中所述第一接合層及所述第二接合層各自的厚度在0.8微米與3微米之間。
TW110114335A 2021-02-26 2021-04-21 半導體封裝及封裝組件及製造方法 TWI764681B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/186,984 2021-02-26
US17/186,984 US11715723B2 (en) 2021-02-26 2021-02-26 Wafer on wafer bonding structure

Publications (2)

Publication Number Publication Date
TWI764681B true TWI764681B (zh) 2022-05-11
TW202234536A TW202234536A (zh) 2022-09-01

Family

ID=82594290

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110114335A TWI764681B (zh) 2021-02-26 2021-04-21 半導體封裝及封裝組件及製造方法

Country Status (5)

Country Link
US (2) US11715723B2 (zh)
KR (1) KR102598745B1 (zh)
CN (1) CN114975384A (zh)
DE (1) DE102021105570A1 (zh)
TW (1) TWI764681B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11876077B2 (en) * 2021-03-12 2024-01-16 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
US20230026052A1 (en) * 2021-07-22 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition bonding layer for joining two semiconductor devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003071604A1 (fr) * 2002-02-22 2003-08-28 Toray Engineering Co., Ltd. Procede de liaison de semi-conducteurs et semi-conducteur multicouches ainsi fabrique
US20110171781A1 (en) * 2007-08-01 2011-07-14 Samsung Electronics Co., Ltd. Method of fabricating a 3-d device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012114214A (ja) 2010-11-24 2012-06-14 Elpida Memory Inc 半導体装置及びその製造方法
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
JP5357241B2 (ja) 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10319701B2 (en) 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10163750B2 (en) * 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
DE102019125790B4 (de) * 2019-05-31 2022-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltkreis-package und verfahren
US11069608B2 (en) 2019-08-22 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US11410984B1 (en) * 2021-10-08 2022-08-09 Silicon Genesis Corporation Three dimensional integrated circuit with lateral connection layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003071604A1 (fr) * 2002-02-22 2003-08-28 Toray Engineering Co., Ltd. Procede de liaison de semi-conducteurs et semi-conducteur multicouches ainsi fabrique
US20110171781A1 (en) * 2007-08-01 2011-07-14 Samsung Electronics Co., Ltd. Method of fabricating a 3-d device

Also Published As

Publication number Publication date
KR20220122428A (ko) 2022-09-02
KR102598745B1 (ko) 2023-11-03
TW202234536A (zh) 2022-09-01
US11715723B2 (en) 2023-08-01
CN114975384A (zh) 2022-08-30
US20220384314A1 (en) 2022-12-01
US20220278074A1 (en) 2022-09-01
DE102021105570A1 (de) 2022-09-01

Similar Documents

Publication Publication Date Title
US11854785B2 (en) Package structure for heat dissipation
US11581281B2 (en) Packaged semiconductor device and method of forming thereof
TWI664685B (zh) 具有無矽基底的中介層的封裝及其形成方法
TWI783269B (zh) 封裝、半導體封裝及其形成方法
TW201911476A (zh) 半導體封裝及其形成方法
KR20200002557A (ko) 반도체 디바이스 패키지 및 방법
TW202123413A (zh) 具有接合結構的裝置及封裝及形成接合結構的方法
KR102356282B1 (ko) 집적 회로 패키지 및 방법
US20220384314A1 (en) Die on die bonding structure
TWI777437B (zh) 半導體封裝體及其製造方法
US20240021554A1 (en) Integrated circuit package and method of forming thereof
TWI735353B (zh) 積體電路封裝及其製作方法
KR20220102542A (ko) 반도체 패키지 및 반도체 패키지 제조 방법
TWI822153B (zh) 封裝結構及其形成方法
TWI842343B (zh) 裝置封裝、半導體封裝及封裝方法
US20240055371A1 (en) Integrated circuit packages and methods of forming the same
TW202407951A (zh) 積體電路封裝及其製造方法
TW202407821A (zh) 積體電路封裝及其形成方法
CN117116873A (zh) 集成电路封装件及其形成方法
CN116646313A (zh) 半导体封装件及其形成方法