CN108346588A - 一种晶圆级系统封装方法以及封装结构 - Google Patents

一种晶圆级系统封装方法以及封装结构 Download PDF

Info

Publication number
CN108346588A
CN108346588A CN201810070261.9A CN201810070261A CN108346588A CN 108346588 A CN108346588 A CN 108346588A CN 201810070261 A CN201810070261 A CN 201810070261A CN 108346588 A CN108346588 A CN 108346588A
Authority
CN
China
Prior art keywords
wafer
plug
chip
bonded together
panels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201810070261.9A
Other languages
English (en)
Other versions
CN108346588B (zh
Inventor
刘孟彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Core Integrated Circuit Ningbo Co Ltd
Original Assignee
China Core Integrated Circuit Ningbo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Core Integrated Circuit Ningbo Co Ltd filed Critical China Core Integrated Circuit Ningbo Co Ltd
Priority to PCT/CN2018/093770 priority Critical patent/WO2019062241A1/zh
Publication of CN108346588A publication Critical patent/CN108346588A/zh
Priority to US16/176,098 priority patent/US10756056B2/en
Application granted granted Critical
Publication of CN108346588B publication Critical patent/CN108346588B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明提供一种晶圆级系统封装方法以及封装结构，所述方法用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，包括：将需要接合在一起的两片所述晶圆相接合；在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造的优势，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率和良率。由本发明的晶圆级系统封装方法制备获得的封装结构同样具有更高的性能和良率。

Description

一种晶圆级系统封装方法以及封装结构
技术领域
本发明涉及半导体技术领域，具体而言涉及一种晶圆级系统封装方法以及封装结构。
背景技术
系统封装(System in Package，简称SiP)将多个不同功能的有源元件，以及无源元件、微机电系统(MEMS)、光学元件等其他元件，组合到一个单元中，形成一个可提供多种功能的系统或子系统，允许异质IC集成，是最好的封装集成技术。相比于片上系统(SystemOn Chip，简称SoC)封装，SiP集成相对简单，设计周期和面市周期更短，成本较低，可以实现更复杂的系统。
与传统的SiP相比，晶圆级系统封装(wafer level package,简称WLP)是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
鉴于晶圆级系统封装的显著优势，如何能够更好的实现晶圆级系统封装一直是业界内研究的热点。
发明内容
鉴于晶圆级系统封装的显著优势，如何能够更好的实现晶圆级系统封装是本发明要解决的技术问题。
本发明一方面提供一种晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，包括：
将需要接合在一起的两片所述晶圆相接合；
在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。
示例性地，将两片所述晶圆的正面与正面相对接合在一起，或者，将其中一个的正面与另一个的背面相对接合在一起，进行所述接合步骤之后，形成所述插塞之前，还包括：
对其中一个背面朝外的晶圆背面进行减薄工艺。
示例性地，将所述两片晶圆的背面与背面相对接合在一起，进行所述接合步骤之前，还包括：
对其中一个晶圆的背面进行减薄工艺。
示例性地，所述形成插塞的步骤包括：
在接合在一起的两片所述晶圆的其中至少一个晶圆内形成通孔；
在所述通孔中填充导电材料形成所述插塞，与对应的所述芯片电连接。
示例性地，所述插塞形成在对应芯片的上方；
或者，所述插塞形成在对应芯片的一侧，在形成所述插塞之前，还包括，形成互连线，与对应的芯片电连接，以及与对应芯片一侧的插塞电连接。
示例性地，在形成所述插塞之后，还包括：
形成再分布互连结构，电连接所述插塞。
示例性地，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
示例性地，所述方法用于将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
示例性地，所述方法用于将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
示例性地，所述方法还包括：
继续将新的所述晶圆与已经接合在一起的晶圆的其中一个接合，
所述需要接合在一起的两个晶圆中，其中一个为新的晶圆，另一个为已经接合在一起的两个晶圆中的其中一个。
示例性地，两片晶圆通过熔融键合工艺、硅硅直接键合工艺或者粘接工艺相键合。
示例性地，所述减薄工艺为:机械研磨工艺、化学机械研磨或者刻蚀工艺中的至少一种。
本发明再一方面还提供一种晶圆级系统封装结构，包括：
至少两片形成有芯片的晶圆，沿垂直晶圆表面的方向堆叠接合在一起；
插塞，相互接合在一起的两片所述晶圆中的芯片，通过所述插塞电连接。
示例性地，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的正面相对接合在一起；
或者，其中一个的正面与另一个的背面相对接合在一起；
或者，其中一个的背面与另一个的背面相对接合在一起。
示例性地，所述插塞形成在对应芯片的上方；
或者，所述插塞形成在对应芯片的一侧，并且还形成有互连线，所述互连线与对应的芯片电连接，以及与对应芯片一侧的所述插塞电连接。
示例性地，还包括：
电连接所述插塞的再分布互连结构，位于所述插塞的顶部。
示例性地，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
示例性地，还包括：形成在相接合的所述晶圆的界面处的键合层。
本发明的封装方法在晶圆上完成封装制造并且将多个芯片集成在一起，因此实现了晶圆级封装和系统封装方法的结合，相比传统封装方式(先切割再进行封装和测试，而封装后至少增加原芯片20％的体积)，本申请将至少两片形成有芯片的晶圆沿上下堆叠的方法，堆叠接合在一起，也即实现芯片的上下堆叠封装，并在晶圆上完整封装后再切割成独立的多芯片模组，能够保持原芯片的大小，因此能够大幅减小封装结构的面积，通过插塞电连接相应芯片，电路布线的线路短，可有效减少电流损耗，因此优化了电性能，由于本发明的方法以晶圆形式的批量生产工艺进行制造，封装加工效率更高；另外，由于能够充分利用晶圆的制造设备，无需另建封装生产线，因此可明显的降低设备的需求；本发明的封装方法将形成有芯片的晶圆直接进入封装工序，中间环节大大减少，周期缩短很多，降低制造成本和工作量，提高了封装的效率和良率。由本发明的晶圆级系统封装方法制备获得的封装结构同样具有更高的性能和良率。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1E示出了本发明一个具体实施方式将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的方法依次实施所获得结构的剖面示意图；
图2A示出了本发明一个具体实施方式将一片晶圆的正面和另一片晶圆的背面接合所获得的结构的剖面示意图；
图2B示出了本发明一个具体实施方式将两片晶圆的背面相接合所获得的结构的剖面示意图；
图3A至图3C示出了本发明一个具体实施方式将三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的方法依次实施所获得结构的剖面示意图；
图4A示出了本发明另一个具体实施方式将三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起所获得结构的剖面示意图；
图4B示出了本发明再一个具体实施方式将三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起所获得结构的剖面示意图；
图5示出了本发明一个具体实施方式的晶圆级系统封装方法的流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细步骤和结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
鉴于晶圆级系统封装的显著优势，本发明提出一种改进了的晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，如图5所示，其主要包括以下步骤：
步骤S1，将需要接合在一起的两片所述晶圆相接合；
步骤S2，在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。
本发明的封装方法在晶圆上完成封装制造并且将多个芯片集成在一起，因此实现了晶圆级封装和系统封装方法的结合，相比传统封装方式(先切割再进行封装和测试，而封装后至少增加原芯片20％的体积)，本申请将至少两片形成有芯片的晶圆沿上下堆叠的方法，堆叠接合在一起，也即实现芯片的上下堆叠封装，并在晶圆上完整封装后再切割成独立的多芯片模组，能够保持原芯片的大小，因此能够大幅减小封装结构的面积，通过插塞电连接相应芯片，电路布线的线路短，可有效减少电流损耗，因此优化了电性能，由于本发明的方法以晶圆形式的批量生产工艺进行制造，封装加工效率更高；另外，由于能够充分利用晶圆的制造设备，无需另建封装生产线，因此可明显的降低设备的需求；本发明的封装方法将形成有芯片的晶圆直接进入封装工序，中间环节大大减少，周期缩短很多，降低制造成本和工作量，提高了封装的效率和良率。
实施例一
下面，参考图1A至图1E对本发明的晶圆级系统封装方法做详细描述，其中，图1A至图1E示出了本发明一个具体实施方式将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的方法依次实施所获得结构的剖面示意图。
作为示例，本发明的晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，例如，用于将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起，包括以下步骤：
首先，执行步骤一，如图1A所示，提供形成有第一芯片101的第一晶圆100和形成有第二芯片201的第二晶圆200，例如，在所述第一晶圆100的正面以内设置有彼此间隔的多个第一芯片101，在所述第二晶圆200的正面以内设置有彼此间隔的多个第二芯片201。
第一晶圆100和第二晶圆200为完成器件制作，分别形成有多个第一芯片101和多个第二芯片201的器件晶圆。该器件晶圆可以采用集成电路制作技术根据相应的布图设计进行制作，例如在半导体晶圆上通过沉积、刻蚀等工作形成诸如NMOS和/或PMOS等的器件，以及介质层和金属层构成的互连层和位于互连层之上的焊盘等结构，从而在半导体晶圆中制作呈阵列排布的第一芯片101和第二芯片201。
具体地，所述第一晶圆100、第二晶圆200均包括半导体衬底，半导体衬底可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
示例性地，在本发明中所涉及的芯片(例如所述第一芯片101、第二芯片201和后续提及的第三芯片)可以是任意一种半导体芯片，其可以包括存储器、逻辑电路、功率器件、双极器件、单独的MOS晶体管、微机电系统(MEMS)等有源器件，甚至也可以是发光二极管等光电器件，其也可以为无源器件，例如电阻、电容等。
芯片(例如所述第一芯片101、第二芯片201和后续提及的第三芯片)通过本领域技术人员熟知的适合的工艺形成在相应晶圆的正面，也即通过半导体工艺形成在半导体衬底上，在此为了简便，仅以一方框的形式简单示出了芯片(例如所述第一芯片101、第二芯片201和后续提到的第三芯片)，但可以想到的是本发明中所涉及的芯片的结构可以包括多个构成元件以及金属互连结构等等，其中，金属互连结构可以包括多层金属层以及电连接相邻金属层的接触孔，相邻的芯片之间可以由形成在晶圆的正面的介电层隔开，形成类似如图1A所示的每个所述第一芯片101和第二芯片201嵌入在相应晶圆的正面内的结构。
介电层可以是单层介电层也可以是由多层介电层组成，在一个示例中，介电层的材料可以是本领域技术人员熟知的任何适合的介电材料，包括但不限于SiO2、碳氟化合物(CF)、掺碳氧化硅(SiOC)或碳氮化硅(SiCN)等等。
值得一提的是，第一芯片101和第二芯片201还可以是形成在晶圆正面以内的多个不同结构的芯片，功能不同的芯片。
另外，本发明中晶圆的正面是指晶圆形成有芯片的一面，而所述背面则是指与所述正面相背的晶圆的表面，本发明中晶圆的正面以及背面在无特别说明的情况下均参照上述解释。
示例性地，第一芯片101和第二芯片201两者也可以是结构和功能相同的芯片。
接着，执行步骤二，将需要接合在一起的两片所述晶圆相接合。
示例性地，在进行接合之前，还可以选择性地对需要接合在一起的两片晶圆中的一个的背面进行减薄工艺，例如，对第一晶圆100或者对第二晶圆200的背面进行减薄工艺，以使减薄后的晶圆的厚度达到目标值。
值得一提的是，在本发明中，减薄后的晶圆的厚度例如在10μm至100μm之间，也可以根据技术节点的不同，对该厚度进行相应调整，在此不做具体限定。
在一个示例中，对其中一个晶圆(例如第一晶圆100或者第二晶圆200)的背面进行减薄工艺的步骤包括：提供支撑基底(未示出)，所述支撑基底可以是本领域技术人员熟知的任何适合的基底，例如半导体衬底、玻璃基底、陶瓷基底等，将所述支撑基底与待减薄的晶圆的正面进行接合，该接合可以使用任何适合的接合方式，例如临时键合或者粘接等，例如使用键合胶层将支撑基底和待减薄的晶圆的正面接合，键合胶层可以是但不限于是有机高分子材料或可紫外变性的有机材料；再对待减薄的晶圆的背面进行减薄工艺，最后将减薄后的晶圆与支撑基底分离，根据所使用的接合方式选择适合的去除方法，例如，高温或者紫外照射的方式，使键合胶层变性失去粘性，从而将支撑基底剥离。
在一个示例中，可以首先将第一晶圆100和第二晶圆200相接合，例如，如图1B所示，将所述第一晶圆100的正面和所述第二晶圆200的正面相接合；并在进行所述接合步骤之后，形成插塞之前，对其中一个晶圆(例如第一晶圆100或者第二晶圆200)背面进行减薄工艺，以使减薄后的晶圆的厚度达到目标值。
在另一个示例中，将所述两片晶圆中，其中一个的正面与另一个的背面相对接合在一起，例如，如图2A所示，将第一晶圆100的正面与第二晶圆200的背面相对接合在一起，然后，再选择性地对背面朝外的晶圆(例如第二晶圆200)的背面进行减薄工艺，以使减薄后的晶圆的厚度达到目标值。
在再一个示例中，将所述两片晶圆的背面与背面相对接合在一起，也即将需要接合的两片晶圆的背面与背面相对接合在一起，例如，如图2B所示，将第一晶圆100和第二晶圆200的背面相对接合在一起，并且在接合之前先选择性地对其中一个晶圆(例如第一晶圆100或者第二晶圆200)的背面进行减薄工艺以使减薄后的晶圆的厚度达到目标值。
值得一提地是，在本发明中，可以使用本领域技术人员熟知的任何适合的减薄方法对晶圆(第一晶圆100、第二晶圆200或者后续的第三晶圆等)进行减薄，例如所述减薄工艺为:机械研磨工艺、化学机械研磨或者刻蚀工艺中的至少一种，为避免重复，在后续的实施例中不再对减薄的方法进行赘述。
可以通过任何适合的方法实现所述第一晶圆100和所述第二晶圆200的接合，例如使用键合(bonding)工艺，其中，两片晶圆通过熔融键合工艺、硅硅直接键合工艺或者粘接工艺相键合，其中，较佳地使用熔融键合，特别是低温熔融键合工艺，以避免温度过高的键合工艺导致器件的失效，其中，低温熔融键合工艺的温度可以低于400℃，例如，低温熔融键合工艺的温度介于100～250℃之间。
在一个示例中，第一晶圆100和第二晶圆200还可以通过粘接工艺接合在一起，例如通过粘接层将第一晶圆和第二晶圆粘接在一起，示例性地，所述粘接层可以为有机薄膜，有机薄膜可以包括各种有机膜层，例如芯片连接薄膜(die attach film，DAF)、干膜(dryfilm)或光阻等。粘接层的厚度根据需要设置，并且粘接层的层数也不限于一层，而可以是两层或更多层。
其中，第二芯片201和第一芯片101的相对位置可以根据器件类型和尺寸进行合理的设置，例如，可以使所述第一芯片101和所述第二芯片201上下部分重叠，或者，所述第二芯片201设置在所述第一芯片101之外的区域，以使所述第二芯片201和第一芯片101完全错开，以便于后续插塞工艺的执行。
图1C示出了在将第一晶圆100和第二晶圆200接合之后，为了减小集成后器件的尺寸，还对所述第一晶圆100或所述第二晶圆200的背面进行减薄工艺，其中，所述减薄工艺可以应用于预定形成所述第一插塞和所述第二插塞的所述第一晶圆100或所述第二晶圆。例如，预定在所述第二晶圆200中形成第一插塞和第二插塞，则自所述第二晶圆200的背面对第二晶圆进行减薄至目标厚度，该目标厚度根据实际工艺需要而定，在此不做具体限定，或者，预定在所述第一晶圆中形成第一插塞和第二插塞，则自所述第一晶圆100的背面对第一晶圆100进行减薄至目标厚度，该目标厚度根据实际工艺需要而定。
接着，执行步骤三，形成插塞，与两片所述晶圆中的芯片电连接。
在一个示例中，形成所述插塞的方法包括：在接合在一起的两片所述晶圆的其中至少一个晶圆内形成通孔，例如，如图1D和图2A所示，在两片晶圆接合在一起时，从一侧晶圆的表面开始，蚀刻至少其中一个晶圆以形成通孔，该通孔用于形成与对应芯片电连接的插塞，可以在其中任意一个晶圆内形成通孔，或者，也可以在其中两个晶圆内均形成通孔，也即，通过从两个晶圆露出的表面开始蚀刻相应晶圆以形成通孔，在所述通孔中填充导电材料形成所述插塞，与对应的芯片电连接。
在一个示例中，可以在接合在一起的两片晶圆中的任意一个晶圆的表面内形成插塞，例如，如图1D和图2A所示，在所述第一晶圆100或者所述第二晶圆200中形成间隔设置的多个第一插塞1021和多个第二插塞1022，其中，所述多个第一芯片101中的至少一个电连接至少一个所述第一插塞1021，所述多个第二芯片201中的至少一个电连接至少一个所述第二插塞1022。
具体地，所述第一插塞1021用于实现第一芯片101和外部电路的电连接，所述第二插塞1022用于实现第二芯片201和外部电路的电连接，尽管图1D中仅示出了一个第一芯片101电连接一个所述第一插塞1021，一个第二芯片201电连接一个所述第二插塞1022的情况，但是对于其他的每个芯片电连接多个插塞的情况，也同样适用于本发明。
在本发明中所涉及的插塞(例如第一插塞1021、第二插塞1022和后续的第三插塞)可以是本领域技术人员熟知的任何适合的金属插塞或者硅通孔(TSV)，金属插塞的材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属，而硅通孔的材料可以包括掺杂的多晶硅或者未掺杂的多晶硅等。
可以使用本领域技术人员熟知的任何适合的方法形成第一插塞1021和第二插塞1022，在一个示例中，形成第一插塞和第二插塞的方法包括：可以首先在第二晶圆200的背面形成图案化的掩膜层(未示出)，较佳地，所述掩膜层使用光刻胶掩膜材料，在图案化的光刻胶掩膜材料中定义了预定形成的第一插塞和第二插塞的图案，然后以所述图案化的掩膜层为掩膜，刻蚀部分第二晶圆200，直到露出部分所述第一芯片以形成第一通孔，以及蚀刻部分所述第二晶圆200，直到露出部分所述第二芯片以形成第二通孔，该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺，其中较佳地使用干法刻蚀工艺。随后，将图案化的掩膜层去除，例如使用灰化的方法去除光刻胶掩膜材料，最后，形成导电材料(例如金属材料或多晶硅)填充第一通孔和第二通孔，以形成第一插塞和第二插塞，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述导电材料。
示例性地，所述第一插塞1021自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第一芯片101电连接，所述第二插塞1022自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第二芯片201电连接。
在此主要以在第二晶圆200中形成第一插塞1021和第二插塞1022的情况为例进行说明，但是可以想到的是也可以通过类似的方法在第一晶圆上形成第一插塞1021和第二插塞1022。
在一个示例中，在形成的插塞具有不同的深度时，可以通过多次执行光刻工艺的方法，形成所述插塞，包括：在其中一片晶圆上形成第一图形化的掩膜层，定义第一插塞的位置；以所述第一图形化的掩膜层为掩膜，刻蚀所述晶圆，形成具有第一深度的第一通孔；去除所述第一图形化的掩膜层；继续在形成有第一通孔的晶圆的表面形成第二图形化的掩膜层，定义第二插塞的位置；以所述第二图形化的掩膜层为掩膜，刻蚀所述晶圆，形成具有第二深度的第二通孔；去除所述第二图形化的掩膜层；在所述第一通孔和所述第二通孔中填充导电材料形成所述第一插塞和所述第二插塞。其中，第一深度和第二深度的大小可以根据实际工艺进行合理选择。
在一个示例中，还可以在接合在一起的两个晶圆内分别形成插塞，例如形成插塞的步骤包括：在其中一片晶圆(例如第一晶圆)上形成第一图形化的掩膜层，定义第一插塞的位置；以所述第一图形化的掩膜层为掩膜，刻蚀所述晶圆(例如第一晶圆)，形成第一通孔；去除所述第一图形化的掩膜层；在所述第一通孔中填充导电材料形成所述第一插塞，与对应的芯片电连接，其中该对应的芯片可以是第一晶圆上的第一芯片也可以是第二晶圆上的第二芯片；在另一片晶圆(例如第二晶圆)上形成第二图形化的掩膜层，定义第二插塞的位置；以所述第二图形化的掩膜层为掩膜，刻蚀所述晶圆(例如第二晶圆)，形成第二通孔；去除所述第二图形化的掩膜层；在所述第二通孔中填充导电材料形成所述第二插塞，与对应的芯片电连接。
示例性地，所述插塞形成在对应芯片的上方，例如，如图1D所示，第一插塞1021形成在对应的第一芯片101的上方，所述第二插塞1022形成在对应的第二芯片201的上方。
在一个示例中，还可以是，所述插塞形成在对应芯片的一侧，在形成所述插塞之前，还包括，形成互连线(未示出)，与对应的芯片电连接，以及与对应芯片一侧的插塞电连接，也即相对应的芯片和插塞之间通过互连线相连接，其中形成互连线的方法可以是本领域技术人员公知的任何适合的方法，在此不做赘述，其中，所述互连线可以包括若干层金属层以及连接相邻金属层的接触孔，其中，所述互连线的材料可以是任意适合的导电材料，例如金属材料，包括但不限于铜或者铝等。
接着，执行步骤四，形成再分布互连结构，电连接所述插塞。
示例性地，如图1E所示，在所述第一晶圆100或者所述第二晶圆200形成有所述第一插塞1021和所述第二插塞1022的表面形成彼此间隔的多个第一再分布互连结构103，其中，所述第一再分布互连结构103电连接至少一个所述第一插塞1021和/或至少一个所述第二插塞1022。
再布线互连结构(例如第一再分布互连结构103和后续的第二再分布互连结构等)可以是本领域技术人员熟知的任何适合的金属材料，所述金属材料可以包括但不限于Ag、Au、Cu、Pd、Cr、Mo、Ti、Ta、Sn、W和Al中的至少一种金属。
示例性地，所述第一再分布互连结构103可以包括再布线层和焊盘，或者，包括焊盘。
可以使用任何适合的方法形成所述第一再分布互连结构103，例如，形成金属材料层以覆盖第二晶圆200的背面，其中，可以使用物理气相沉积方法(PVD)、化学气相沉积方法(CVD)、溅射、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成所述金属材料层，再通过刻蚀的方法去除部分所述金属材料层，以形成间隔设置的多个第一再分布互连结构103。
尽管图1E中仅示出了第一再分布互连结构103电连接对应的插塞的情况，但是可以想到的是，为了实现更多的电连接方式，还可以使第一再分布互连结构103电连接至少一个第一插塞1021和至少一个第二插塞1022。
值得注意的是，还可以在第一再分布互连结构103上方形成金属互连线，以实现更多芯片的连接，其中，通常金属互连线包括由更多位于不同层的金属层构成，以及不同层的金属层通过设置在相邻层之间的插塞或金属插塞电连接。
在一个示例中，在形成所述第一再分布互连结构103之后，还包括以下步骤：形成层间介电层104，以覆盖所述第一再分布互连结构103以及所述第一晶圆100或者所述第二晶圆200的背面，例如形成层间介电层104，以覆盖所述第一再分布互连结构103以及所述第二晶圆200的背面。
层间介电层104可以使用例如SiO2、碳氟化合物(CF)、掺碳氧化硅(SiOC)、或碳氮化硅(SiCN)等。或者，也可以使用在碳氟化合物(CF)上形成了SiCN薄膜的膜等。碳氟化合物以氟(F)和碳(C)为主要成分。碳氟化合物也可以使用具有非晶体(非结晶性)构造的物质。层间介电层104还可以使用例如掺碳氧化硅(SiOC)等多孔质构造。
可以使用化学气相沉积法、物理气相沉积法、原子层沉积法等方法形成所述层间介电层104。
其中，所述层间介电层104的顶面可以和所述第一再分布互连结构103的顶面齐平，或者，所述层间介电层104的顶面高于所述第一再分布互连结构103的顶面。
还可选择性地对层间介电层104的表面进行平坦化，以获得平坦的表面，所述平坦化的方法可以是化学机械研磨或者其他适合的方法。
至此，完成了对本发明的两片晶圆相接合的方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对晶圆进行切割工艺，以将集成在晶圆上的多个芯片分割为各自独立的单元，例如每个单元均包括至少一个第一芯片和至少一个第二芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于实际集成的芯片的功能。
实施例二
上述步骤示出了将第一晶圆和第二晶圆两个形成有芯片的晶圆相接合集成在一起所需的主要工艺步骤，而利用本发明的方法还可以将更多的晶圆集成在一起，以实现更多个芯片的封装。本发明的封装方法还可以用于将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
下面，参考图1A至图1E、图2A、图3A至图3C以及图4A至图4B对将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起的封装方法进行描述。
首先，如图3A所示，提供第三晶圆300。
在一个示例中，还可以提供至少一个形成有第三芯片301的第三晶圆300，在每个所述第三晶圆的正面以内设置有彼此间隔的多个第三芯片301。
第三晶圆300为完成器件制作，分别形成有多个第三芯片301的器件晶圆。该器件晶圆可以采用集成电路制作技术根据相应的布图设计进行制作，例如在半导体晶圆上通过沉积、刻蚀等工作形成诸如NMOS和/或PMOS等的器件，以及介质层和金属层构成的互连层和位于互连层之上的焊盘等结构，从而在半导体晶圆中制作呈阵列排布的第三芯片301。
具体地，所述第三晶圆300包括半导体衬底，所述半导体衬底的材料可以使用前述实施一中所示例的半导体材料中的任意一种或多种。
所述第三芯片301通过本领域技术人员熟知的适合的工艺形成在相应晶圆的正面，形成类似如图3A所示的每个所述第三芯片301嵌入在相应晶圆的正面内的结构。
值得一提的是，第三芯片301还可以是形成在晶圆正面以内的多个不同结构的芯片，功能不同的芯片。
示例性地，第三芯片301也可以是结构和功能相同的芯片。
接着，继续将新的所述晶圆与已经接合在一起的晶圆的其中一个接合，所述需要接合在一起的两个晶圆中，其中一个为新的晶圆，另一个为已经接合在一起的两个晶圆中的其中一个。
其中，新的晶圆是指需要继续接合的晶圆，示例性地，如图3B所示，所述新的晶圆是指一个第三晶圆300，将第三晶圆300和已经接合在一起的第一晶圆100和第二晶圆200的其中一个接合(例如图1E所示的结构)。
在此仅以将一个所述第三晶圆300与如图1E所示的已经接合在一起的两个晶圆中的第二晶圆200接合的方法进行说明，该方法同样适用于将第三晶圆300和如图1E所示的已经接合在一起的两个晶圆中的第一晶圆100相接合的情况，主要包括以下步骤A1至A3：
首先，执行步骤A1，将所述第三晶圆和形成有所述第一再分布互连结构103的表面相接合，其中，接合方法可以使用前述实施一中所提到的将第一晶圆和第二晶圆相接合的方法中的任意一种。
在一个示例中，为了实现熔融键合工艺，在接合之前，还包括在在所述第三晶圆300的正面形成键合层105的步骤。
其中，所述键合层105的材料包括氧化硅层，包括利用热化学气相沉积(thermalCVD)制造工艺或高密度等离子体(HDP)或者由正硅酸乙酯(TEOS)制造工艺形成的氧化硅的材料层，也可以是由热氧化工艺形成的氧化硅层，还可以是采用低工艺温度氧化方法(Lowprocess temperature oxide，LTO)制备的所述氧化硅层，工艺温度小于200℃。
在一个示例中，进行键合工艺，将所述键合层105和所述层间介电层104键合在一起，以实现第三晶圆300和第二晶圆的接合。
该键合工艺为熔融键合，特别是为低温熔融键合工艺，并且在键合过程中还可以施加压力，例如施加的键合压力为1～10N，其中，键合时间可以为10～60s。熔融键合过程中，形成Si-O键实现两片晶圆的互连。
在一个示例中，在接合之后，还可以自所述第三晶圆300的背面对所述第三晶圆300进行减薄至目标厚度。该目标厚度根据实际工艺需要而定，在此不做具体限定。
接着，执行步骤A2，在所述第三晶圆300中形成彼此间隔的多个第三插塞106，其中，部分所述第三插塞106与所述第一再分布互连结构103电连接，部分所述第三插塞106电连接所述第三芯片301。
所述第三插塞106自所述第三晶圆300的背面向正面延伸，每个所述第一再分布互连结构103电连接至少一个所述第三插塞106，每个所述第三芯片301电连接至少一个所述第三插塞106，其中，与所述第一再分布互连结构103电连接的第三插塞106贯穿所述第三晶圆以及所述键合层105。
值得一提的是，可以使用任何适合的方法形成所述第三插塞106，例如可以参考前述实施例一中第一插塞和第二插塞的形成方法形成该第三插塞。
随后，执行步骤A3，在所述第三晶圆300的背面形成第二再分布互连结构107。
具体地，该第二再分布互连结构可以包括再布线层和焊盘，或者包括焊盘，用于将第一芯片、第二芯片和第三芯片引出与外部电路实现连接，所述第二再分布互连结构107电连接所述第三插塞106。
可以使用任何适合的方法形成所述第二再分布互连结构107，第二再分布互连结构107的形成方法可以参考前述实施例一中第一再分布互连结构107的方法，在此不做赘述。
在一个示例中，还包括在所述第三晶圆的背面依次再接合多个晶圆的步骤，该多个晶圆中均形成有彼此间隔的多个芯片，可以包括步骤B1，形成层间介电层，以覆盖所述第二再分布互连结构，步骤B2，将正面设置有彼此间隔的多个芯片的另一新的晶圆与形成有层间介电层的表面相接合，示例性地，还可在该另一新的晶圆的正面形成键合层，利用键合工艺将该另一新的晶圆和形成有所述层间介电层的表面相接合，以实现更多晶圆的封装，步骤B3，自该另一新的晶圆的背面对该另一新的晶圆进行减薄至目标厚度，步骤B4，在该另一新的晶圆中形成彼此间隔的多个插塞，部分插塞电连接所述第二再分布互连结构，部分插塞电连接形成在该另一新的晶圆中的芯片，步骤B5，在该另一新的晶圆的背面形成再分布互连结构，该金属层至少电连接一个所述插塞。可以依次循环执行步骤B1至步骤B5，从而实现多于3个晶圆的接合以及封装。其中新的晶圆均是指需要继续与其它晶圆接合的晶圆。
在一个示例中，如图3C所示，形成钝化层108，以覆盖所述第二再分布互连结构107以及所述第三晶圆300的背面。
所述钝化层108的材料可以使用任何适合的绝缘材料，例如所述钝化层108使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层，可通过化学气相沉积、物理气相沉积或原子层沉积等沉积方法沉积形成所述钝化层108；还可以使用诸如包含聚乙烯苯酚、聚酰亚胺、或硅氧烷等的层的绝缘层等。聚乙烯苯酚、聚酰亚胺、或硅氧烷可有效地通过微滴排放法、印刷术或旋涂法形成。硅氧烷根据其结构可被分类成二氧化硅玻璃、烷基硅氧烷聚合物、烷基倍半硅氧烷(alkylsilsesquioxane)聚合物、倍半硅氧烷氢化物(silsesquioxanehydride)聚合物、烷基倍半硅氧烷氢化物(alkylsilsesquioxane hydride)聚合物等。此外，绝缘材料可用包括具有Si-N键的聚合物(聚硅氨烷)的材料形成。此外，可层叠这些膜以形成钝化层。
示例性地，所述钝化层108的顶面高于所述第二再分布互连结构107的顶面。所述钝化层的厚度可以是任意适合的厚度，在此不做具体限定。
示例性地，在沉积钝化层108后还可以选择性的对钝化层108的表面进行化学机械研磨，以获得平坦的表面。
在一个示例中，在将多于三个的晶圆封装在一起时，可以形成钝化层108，以覆盖位于顶层的再分布互连结构(该再分布互连结构包括焊盘)。
随后，继续如图3C所示，在每个所述第二再分布互连结构107上方的所述钝化层108中形成开口109，所述开口109露出部分所述第二再分布互连结构107，也即露出第二再分布互连结构107中包括的焊盘。
为了实现焊盘与外部电路的连接，需要露出焊盘表面的开口109，可以使用任何适合的方法形成所述开口109，在一个示例中，首先在钝化层108的表面形成图案化的掩膜层，例如光刻胶层，该图案化的掩膜层定义有开口的图案，然后再以该图案化的掩膜层为掩膜，刻蚀露出的钝化层108，直到露出第二再分布互连结构107的表面，以形成所述开口109，随后，将图案化的掩膜层去除，例如通过灰化或者湿法刻蚀的方法去除光刻胶材质的掩膜层。
在一个示例中，如图4A所示，还可以在对第三晶圆300的背面进行减薄之后，将第三晶圆300的背面和第二晶圆200接合，或者，将还可以在对第三晶圆300的背面进行减薄之后，将第三晶圆300的背面和第一晶圆100接合，可以使用与前述方法相同的接合方法以及形成插塞的方法也可以参照前述插塞的形成方法，在此不做赘述。
在一个示例中，如图4B所示，还可以将如图2A所示的结构和第三晶圆300相接合，其接合方法可以使用与前述方法相同的接合方法以及形成插塞的方法也可以参照前述插塞的形成方法，在此不做赘述。
至此，完成了对本发明的晶圆级系统封装方法的关键步骤的介绍，对于完整的方法还可能包括其他的步骤，例如封装完成后，还可以沿切割道对晶圆进行切割工艺，以将集成在晶圆上的多个芯片分割为各自独立的单元，例如每个单元均包括至少一个第一芯片和至少一个第二芯片和至少一个第三芯片，该单元形成一个可提供多种功能的系统或子系统，该功能取决于实际集成的芯片的功能。
综上所述，本发明的晶圆级系统封装方法，使用晶圆级封装和系统封装方法相结合，同时实现了多种芯片的集成和在晶圆上完成封装制造优势，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求，提高了封装的效率和良率。
实施例三
本发明再一方面还提供一种晶圆级系统封装结构，所述晶圆级系统封装结构基于前述封装方法制备获得。
下面参考图1E、图3C、图4A和图4B对本发明的封装结构进行解释和说明。
作为示例，本发明的封装结构包括至少两片形成有芯片的晶圆，沿垂直晶圆表面的方向堆叠接合在一起，例如，如图3C、图4A和图4B所示，包括第一晶圆100、第二晶圆200以及第三晶圆300，在所述第一晶圆100的正面设置有彼此间隔的多个第一芯片101，在所述第二晶圆200的正面设置有彼此间隔的多个第二芯片201，在所述第三晶圆300的正面设置有彼此间隔的多个第三芯片301。
在一个示例中，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的正面相对接合在一起，例如，如图1E和图3C所示、第一晶圆100的正面和第二晶圆200的正面相接合。
在一个示例中，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的背面相对接合在一起，例如，第一晶圆的正面和第二晶圆的背面相对接合在一起，或者，如图2A所示，第一晶圆100的背面和第二晶圆200的背面相对接合在一起。
在一个示例中，其中一个的背面与另一个的背面相对接合在一起，或者，如图2B所示，第一晶圆100的背面与第二晶圆200的背面相对接合在一起。
在一个示例中，本发明的封装结构还包括插塞，相互接合在一起的两片所述晶圆中的芯片，通过所述插塞电连接，例如如图3C所示，第一晶圆100和第二晶圆200相接合，第一插塞1021电连接所述第一晶圆100中的第一芯片101，第二插塞1022电连接所述第二晶圆200中的第二芯片201，而若干个第三插塞106电连接所述第三晶圆300中的第三芯片301，若干个第三插塞还进一步电连接所述第二芯片201，若干个第三插塞106还进一步电连接所述第一芯片101。
在一个示例中，所述插塞形成在对应芯片的上方，例如，在所述第二晶圆200中形成有间隔设置的多个第一插塞1021和多个第二插塞1022，其中，所述第一插塞1021形成在对应的第一芯片101的上方，所述第二插塞1022形成在对应的第二芯片201的上方。
具体地，所述第一插塞1021用于实现第一芯片101和外部电路的电连接，所述第二插塞1022用于实现第二芯片201和外部电路的电连接，尽管图3C中仅示出了一个第一芯片101电连接一个所述第一插塞1021，一个第二芯片201电连接一个所述第二插塞1022的情况，但是对于其他的每个芯片电连接多个插塞的情况，也同样适用于本发明。
示例性地，如图1E所示，所述第一插塞1021自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第一芯片101电连接，所述第二插塞1022自所述第二晶圆200的背面向所述正面延伸直到与其所对应的所述第二芯片201电连接。
在一个示例中，所述插塞形成在对应芯片的一侧，并且还形成有互连线，所述互连线与对应的芯片电连接，以及与对应芯片一侧的所述插塞电连接。其中，所述互连线可以包括若干层金属层以及连接相邻金属层的接触孔，其中，所述互连线的材料可以是任意适合的导电材料，例如金属材料，包括但不限于铜或者铝等。
示例性地，还包括电连接所述插塞的再分布互连结构，位于所述插塞的顶部。例如，在第一插塞1021和所述第二插塞1022的顶部形成有第一再分布互连结构103，其中，所述第一再分布互连结构103电连接至少一个所述第一插塞1021和/或至少一个所述第二插塞1022。
尽管图3C中仅示出了第一再分布互连结构103电连接对应插塞的情况，但是可以想到的是，为了实现更多的电连接方式，还可以使第一再分布互连结构103电连接至少一个第一插塞1021和至少一个第二插塞1022。
示例性地，所述第一再分布互连结构103可以包括再布线层和焊盘，或者，包括焊盘。
在一个示例中，还包括覆盖所述第一再分布互连结构103以及所述第一晶圆100或者所述第二晶圆200的背面的层间介电层104，例如层间介电层104覆盖所述第一再分布互连结构103以及所述第二晶圆200的背面。
其中，所述层间介电层104的顶面可以和所述第一再分布互连结构103的顶面齐平，或者，所述层间介电层104的顶面高于所述第一再分布互连结构103的顶面。
在一个示例中，还包括第三晶圆300，所述第三晶圆和形成有所述第一再分布互连结构的表面相接合，例如，将所述第三晶圆300和第二晶圆200背面相接合。
在一个示例中，还包括形成在相接合的所述晶圆的界面处的键合层105。
在一个示例中，所述键合层105和所述层间介电层104键合在一起，以实现第三晶圆300和第二晶圆200的接合。
示例性地，在所述第三晶圆300中形成有彼此间隔的多个第三插塞106，其中，部分所述第三插塞106与所述第一再分布互连结构103电连接，部分所述第三插塞106电连接所述第三芯片301。
所述第三插塞106所述第三晶圆300的背面向正面延伸，每个所述第一再分布互连结构103电连接至少一个所述第三插塞106，每个所述第三芯片301电连接至少一个所述第三插塞106。其中，与所述第一再分布互连结构103电连接的第三插塞106贯穿所述第三晶圆以及所述键合层105。
示例性地，在所述第三晶圆300的背面形成有第二再分布互连结构107。该第二再分布互连结构可以包括再布线层和焊盘，或者包括焊盘，用于将第一芯片、第二芯片和第三芯片引出与外部电路实现连接。
在一个示例中，覆盖形成有所述再分布互连结构的晶圆的表面的钝化层，例如，如图3C所示，还形成有覆盖所述第二再分布互连结构107以及所述第三晶圆300的所述背面的钝化层108。
在一个示例中，在将多于三个的晶圆封装在一起时，所述钝化层可以覆盖位于顶层的再分布互连结构(该再分布互连结构包括焊盘)。
示例性，在每个所述第二再分布互连结构107上方的所述钝化层108中形成有开口109，所述开口109露出部分所述第二再分布互连结构107。
本发明的晶圆级系统封装结构由于使用了前述的晶圆级系统封装方法制备获得，因而具有更好的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (18)

1.一种晶圆级系统封装方法，用于将至少两片形成有芯片的晶圆沿上下堆叠的方向，堆叠接合在一起，其特征在于，所述方法包括：
将需要接合在一起的两片所述晶圆相接合；
在所述接合之后，形成插塞，与两片所述晶圆中的芯片电连接。
2.如权利要求1所述的封装方法，其特征在于，
将两片所述晶圆的正面与正面相对接合在一起，或者，将其中一个的正面与另一个的背面相对接合在一起，进行所述接合步骤之后，形成所述插塞之前，还包括：
对其中一个背面朝外的晶圆背面进行减薄工艺。
3.如权利要求1所述的封装方法，其特征在于，将所述两片晶圆的背面与背面相对接合在一起，进行所述接合步骤之前，还包括：
对其中一个晶圆的背面进行减薄工艺。
4.如权利要求1所述的封装方法，其特征在于，所述形成插塞的步骤包括：
在接合在一起的两片所述晶圆的其中至少一个晶圆内形成通孔；
在所述通孔中填充导电材料形成所述插塞，与对应的所述芯片电连接。
5.如权利要求1所述的封装方法，其特征在于，所述插塞形成在对应芯片的上方；
或者，所述插塞形成在对应芯片的一侧，在形成所述插塞之前，还包括，形成互连线，与对应的芯片电连接，以及与对应芯片一侧的插塞电连接。
6.如权利要求1所述的封装方法，其特征在于，在形成所述插塞之后，还包括：
形成再分布互连结构，电连接所述插塞。
7.如权利要求6所述的封装方法，其特征在于，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
8.如权利要求1所述的封装方法，其特征在于，所述方法用于将两片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
9.如权利要求1所述的封装方法，其特征在于，所述方法用于将至少三片形成有芯片的晶圆沿上下堆叠方向堆叠接合在一起。
10.如权利要求9所述的封装方法，其特征在于，所述方法还包括：
继续将新的所述晶圆与已经接合在一起的晶圆的其中一个接合，
所述需要接合在一起的两个晶圆中，其中一个为新的晶圆，另一个为已经接合在一起的两个晶圆中的其中一个。
11.如权利要求1所述的封装方法，其特征在于，两片晶圆通过熔融键合工艺、硅硅直接键合工艺或者粘接工艺相键合。
12.如权利要求2或3所述的封装方法，其特征在于，所述减薄工艺为:机械研磨工艺、化学机械研磨或者刻蚀工艺中的至少一种。
13.一种晶圆级系统封装结构，其特征在于，包括：
至少两片形成有芯片的晶圆，沿垂直晶圆表面的方向堆叠接合在一起；
插塞，相互接合在一起的两片所述晶圆中的芯片，通过所述插塞电连接。
14.如权利要求13所述的晶圆级系统封装结构，其特征在于，相互接合在一起的两片所述晶圆，其中一个的正面与另一个的正面相对接合在一起；
或者，其中一个的正面与另一个的背面相对接合在一起；
或者，其中一个的背面与另一个的背面相对接合在一起。
15.如权利要求13所述的晶圆级系统封装结构，其特征在于，所述插塞形成在对应芯片的上方；
或者，所述插塞形成在对应芯片的一侧，并且还形成有互连线，所述互连线与对应的芯片电连接，以及与对应芯片一侧的所述插塞电连接。
16.如权利要求13所述的晶圆级系统封装结构，其特征在于，还包括：
电连接所述插塞的再分布互连结构，位于所述插塞的顶部。
17.如权利要求16所述的晶圆级系统封装结构，其特征在于，所述再分布互连结构包括：再布线层和焊盘，或者，包括焊盘。
18.如权利要求13所述的晶圆级系统封装结构，其特征在于，还包括：形成在相接合的所述晶圆的界面处的键合层。
CN201810070261.9A 2017-09-30 2018-01-24 一种晶圆级系统封装方法以及封装结构 Active CN108346588B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/093770 WO2019062241A1 (zh) 2017-09-30 2018-06-29 一种晶圆级系统封装方法以及封装结构
US16/176,098 US10756056B2 (en) 2017-09-30 2018-10-31 Methods and structures for wafer-level system in package

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201710917071 2017-09-30
CN201710919199 2017-09-30
CN2017109191991 2017-09-30
CN2017109170711 2017-09-30

Publications (2)

Publication Number Publication Date
CN108346588A true CN108346588A (zh) 2018-07-31
CN108346588B CN108346588B (zh) 2020-12-04

Family

ID=62925660

Family Applications (6)

Application Number Title Priority Date Filing Date
CN201810070260.4A Active CN108336037B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装结构和电子装置
CN201810069675.XA Active CN108335986B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装方法
CN201810070263.8A Active CN108346639B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装方法以及封装结构
CN201810070261.9A Active CN108346588B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装方法以及封装结构
CN201810416799.0A Active CN108666264B (zh) 2017-09-30 2018-05-03 晶圆级系统封装方法及封装结构
CN201810415667.6A Active CN108597998B (zh) 2017-09-30 2018-05-03 晶圆级系统封装方法及封装结构

Family Applications Before (3)

Application Number Title Priority Date Filing Date
CN201810070260.4A Active CN108336037B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装结构和电子装置
CN201810069675.XA Active CN108335986B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装方法
CN201810070263.8A Active CN108346639B (zh) 2017-09-30 2018-01-24 一种晶圆级系统封装方法以及封装结构

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN201810416799.0A Active CN108666264B (zh) 2017-09-30 2018-05-03 晶圆级系统封装方法及封装结构
CN201810415667.6A Active CN108597998B (zh) 2017-09-30 2018-05-03 晶圆级系统封装方法及封装结构

Country Status (5)

Country Link
US (3) US10811385B2 (zh)
JP (1) JP7027577B2 (zh)
KR (1) KR102400264B1 (zh)
CN (6) CN108336037B (zh)
WO (4) WO2019062241A1 (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109411473A (zh) * 2018-11-05 2019-03-01 长江存储科技有限责任公司 一种dram存储芯片及其制造方法
CN110875192A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875232A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110945660A (zh) * 2019-11-12 2020-03-31 深圳市汇顶科技股份有限公司 堆叠式的芯片、制造方法、图像传感器和电子设备
WO2020088205A1 (en) * 2018-11-01 2020-05-07 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
WO2020134589A1 (zh) * 2018-12-27 2020-07-02 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377392A (zh) * 2018-12-27 2020-07-07 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377394A (zh) * 2018-12-27 2020-07-07 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111505477A (zh) * 2020-04-29 2020-08-07 江苏七维测试技术有限公司 传感器晶圆级测试方法
CN112956023A (zh) * 2021-02-05 2021-06-11 长江存储科技有限责任公司 倒装芯片堆叠结构及其形成方法
CN113223999A (zh) * 2021-04-01 2021-08-06 光华临港工程应用技术研发(上海)有限公司 晶圆键合方法及晶圆键合结构

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108336037B (zh) 2017-09-30 2022-02-11 中芯集成电路（宁波）有限公司 一种晶圆级系统封装结构和电子装置
CN109003907B (zh) * 2018-08-06 2021-10-19 中芯集成电路（宁波）有限公司 封装方法
CN110875200B (zh) * 2018-09-04 2021-09-14 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875205B (zh) * 2018-09-04 2021-07-09 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875268A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
JP2021535613A (ja) 2018-09-04 2021-12-16 中芯集成電路（寧波）有限公司 ウェハレベルパッケージ方法及びパッケージ構造
CN110875231A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875193B (zh) * 2018-09-04 2021-08-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
JP7106753B2 (ja) * 2018-09-04 2022-07-26 中芯集成電路（寧波）有限公司 ウェハレベルパッケージング方法及びパッケージング構造
JP7102609B2 (ja) * 2018-09-04 2022-07-19 中芯集成電路（寧波）有限公司 ウェハレベルシステムパッケージング方法及びパッケージング構造
CN110875207B (zh) * 2018-09-04 2021-05-07 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN111128749A (zh) * 2018-10-31 2020-05-08 中芯集成电路（宁波）有限公司 使用可光刻键合材料的晶圆级封装方法
US10755979B2 (en) 2018-10-31 2020-08-25 Ningbo Semiconductor International Corporation Wafer-level packaging methods using a photolithographic bonding material
CN111128974A (zh) * 2018-11-01 2020-05-08 长鑫存储技术有限公司 晶圆堆叠方法与晶圆堆叠结构
CN111180382A (zh) * 2018-11-13 2020-05-19 中芯集成电路（宁波）有限公司 一种晶圆级器件集成方法及集成结构
CN111200702B (zh) * 2018-11-20 2022-03-15 中芯集成电路（宁波）有限公司 摄像组件及其封装方法、镜头模组、电子设备
US10680633B1 (en) * 2018-12-21 2020-06-09 Analog Devices International Unlimited Compnay Data acquisition system-in-package
CN109860064B (zh) * 2018-12-21 2021-04-06 中芯集成电路（宁波）有限公司 一种晶圆级系统封装方法以及封装结构
CN109659267B (zh) * 2018-12-21 2021-04-23 中芯集成电路（宁波）有限公司 半导体器件制作方法
CN111370431B (zh) * 2018-12-26 2023-04-18 中芯集成电路（宁波）有限公司 光电传感集成系统的封装方法
CN111377395B (zh) * 2018-12-27 2023-09-08 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377393B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377391B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN109585402A (zh) * 2018-12-28 2019-04-05 华进半导体封装先导技术研发中心有限公司 一种芯片扇出型封装结构及封装方法
CN111627939B (zh) * 2019-02-27 2023-04-18 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
CN110379767B (zh) * 2019-07-16 2022-02-08 中芯集成电路（宁波）有限公司 晶圆级封装芯片通孔互连的方法以及芯片的测试方法
CN110892521B (zh) * 2019-10-12 2021-01-29 长江存储科技有限责任公司 用于裸片对裸片进行键合的方法和结构
CN111180438B (zh) * 2019-12-31 2022-06-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及晶圆级封装结构
CN111162054B (zh) * 2019-12-31 2022-01-11 中芯集成电路（宁波）有限公司 一种晶圆级芯片封装方法及封装结构
CN111293078B (zh) * 2020-03-17 2022-05-27 浙江大学 一种转接板正反两面空腔嵌入芯片的方法
CN111524467B (zh) * 2020-06-11 2022-06-21 厦门通富微电子有限公司 一种显示装置及其制备方法
CN111725153A (zh) * 2020-06-16 2020-09-29 杰群电子科技（东莞）有限公司 一种无基板系统级封装结构、方法及电子产品
CN111952198B (zh) * 2020-08-25 2022-09-13 嘉兴启创科技咨询有限公司 一种半导体封装及其制备方法
US11335657B2 (en) * 2020-09-16 2022-05-17 International Business Machines Corporation Wafer scale supercomputer
CN112802760B (zh) * 2021-01-07 2022-05-06 湖南中科存储科技有限公司 一种多芯片半导体封装及其形成方法
WO2022161249A1 (zh) * 2021-01-29 2022-08-04 中芯集成电路（宁波）有限公司 一种晶圆级封装结构及其制造方法
CN113224005A (zh) * 2021-04-08 2021-08-06 深圳市德明利光电有限公司 一种芯片切割道工艺方法
CN113539855A (zh) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 一种系统级封装方法及封装结构
CN113539853B (zh) * 2021-07-16 2023-01-13 芯知微(上海)电子科技有限公司 一种晶圆级封装方法及其封装结构
US11637087B2 (en) * 2021-08-27 2023-04-25 Taiwan Semiconductor Manufacturing Company Limited Multi-chip device and method of formation
WO2023104095A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure of stacked chips thereof
CN116682743B (zh) * 2023-05-15 2024-01-23 珠海妙存科技有限公司 一种内存芯片封装方法、内存芯片以及集成电路系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740421A (zh) * 2008-11-17 2010-06-16 中芯国际集成电路制造(上海)有限公司 晶圆及制作方法、系统级封装结构及封装方法
CN104009014A (zh) * 2014-04-26 2014-08-27 华进半导体封装先导技术研发中心有限公司 集成无源器件晶圆级封装三维堆叠结构及制作方法
CN106449672A (zh) * 2015-08-04 2017-02-22 精材科技股份有限公司 感测晶片封装体及其制造方法

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5723907A (en) * 1996-06-25 1998-03-03 Micron Technology, Inc. Loc simm
US5811879A (en) * 1996-06-26 1998-09-22 Micron Technology, Inc. Stacked leads-over-chip multi-chip module
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US5998860A (en) * 1997-12-19 1999-12-07 Texas Instruments Incorporated Double sided single inline memory module
US6656827B1 (en) * 2002-10-17 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical performance enhanced wafer level chip scale package with ground
KR100497111B1 (ko) * 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
DE10334575B4 (de) * 2003-07-28 2007-10-04 Infineon Technologies Ag Elektronisches Bauteil und Nutzen sowie Verfahren zur Herstellung derselben
US7528494B2 (en) * 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
JP4979320B2 (ja) * 2006-09-28 2012-07-18 ルネサスエレクトロニクス株式会社 半導体ウェハおよびその製造方法、ならびに半導体装置の製造方法
US20080191310A1 (en) * 2007-02-12 2008-08-14 Weng-Jin Wu By-product removal for wafer bonding process
US7951647B2 (en) * 2008-06-17 2011-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Performing die-to-wafer stacking by filling gaps between dies
US8063475B2 (en) * 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
GB0821158D0 (en) * 2008-11-20 2008-12-24 Durham Scient Crystals Ltd Semiconductor device connection
CN101840871A (zh) * 2009-03-20 2010-09-22 昆山西钛微电子科技有限公司 晶圆级芯片尺寸封装法
JP5543125B2 (ja) * 2009-04-08 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置および半導体装置の製造方法
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8841777B2 (en) * 2010-01-12 2014-09-23 International Business Machines Corporation Bonded structure employing metal semiconductor alloy bonding
US9219023B2 (en) * 2010-01-19 2015-12-22 Globalfoundries Inc. 3D chip stack having encapsulated chip-in-chip
US8519538B2 (en) * 2010-04-28 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Laser etch via formation
JP2011243596A (ja) * 2010-05-14 2011-12-01 Panasonic Corp パッケージ部品の製造方法およびパッケージ部品
KR101692955B1 (ko) * 2010-10-06 2017-01-05 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
CN102024782B (zh) * 2010-10-12 2012-07-25 北京大学 三维垂直互联结构及其制作方法
US20120142136A1 (en) * 2010-12-01 2012-06-07 Honeywell International Inc. Wafer level packaging process for mems devices
US8674518B2 (en) * 2011-01-03 2014-03-18 Shu-Ming Chang Chip package and method for forming the same
JP5853389B2 (ja) * 2011-03-28 2016-02-09 ソニー株式会社 半導体装置及び半導体装置の製造方法。
US8575758B2 (en) * 2011-08-04 2013-11-05 Texas Instruments Incorporated Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
US9190391B2 (en) * 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US8772929B2 (en) * 2011-11-16 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package for three dimensional integrated circuit
KR101831938B1 (ko) * 2011-12-09 2018-02-23 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 이에 의해 제조된 팬 아웃 웨이퍼 레벨 패키지
CN202394963U (zh) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 多芯片晶圆级半导体封装构造
US8748232B2 (en) * 2012-01-03 2014-06-10 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via
TWI512851B (zh) * 2012-09-01 2015-12-11 Alpha & Omega Semiconductor 帶有厚底部基座的晶圓級封裝器件及其製備方法
KR20140147613A (ko) * 2013-06-20 2014-12-30 삼성전기주식회사 웨이퍼 레벨 반도체 패키지 및 그 제조방법
KR102111739B1 (ko) * 2013-07-23 2020-05-15 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9059039B2 (en) 2013-09-06 2015-06-16 International Business Machines Corporation Reducing wafer bonding misalignment by varying thermal treatment prior to bonding
US9570421B2 (en) * 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
TWI556381B (zh) * 2014-02-20 2016-11-01 矽品精密工業股份有限公司 半導體封裝件及其製法
KR102167599B1 (ko) * 2014-03-04 2020-10-19 에스케이하이닉스 주식회사 칩 스택 임베디드 패키지
CN103887279B (zh) * 2014-04-02 2017-02-01 华进半导体封装先导技术研发中心有限公司 三维扇出型晶圆级封装结构及制造工艺
US9449837B2 (en) * 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
CN204179071U (zh) * 2014-09-12 2015-02-25 苏州晶方半导体科技股份有限公司 晶圆级指纹识别芯片封装结构
US9502344B2 (en) * 2014-10-06 2016-11-22 Viagan Ltd. Wafer level packaging of electronic device
KR102352237B1 (ko) * 2014-10-23 2022-01-18 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 그의 구조
CN104392958A (zh) * 2014-11-23 2015-03-04 北京工业大学 晶圆级含硅通孔的半导体封装方法
CN104600058B (zh) * 2015-02-03 2017-02-22 华天科技（昆山）电子有限公司 多芯片半导体封装结构及制作方法
CN104835808A (zh) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 芯片封装方法及芯片封装结构
US10269767B2 (en) * 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
CN105140213B (zh) * 2015-09-24 2019-01-11 中芯长电半导体（江阴）有限公司 一种芯片封装结构及封装方法
CN205177812U (zh) * 2015-10-23 2016-04-20 宁波芯健半导体有限公司 侧壁及背面带有绝缘保护的芯片封装结构
US11037904B2 (en) * 2015-11-24 2021-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Singulation and bonding methods and structures formed thereby
US20170207194A1 (en) * 2016-01-19 2017-07-20 Xintec Inc. Chip package and method for forming the same
CN105621345B (zh) * 2016-03-11 2018-06-29 华天科技（昆山）电子有限公司 Mems芯片集成的封装结构及封装方法
CN105870024B (zh) * 2016-06-15 2018-07-27 通富微电子股份有限公司 系统级封装方法
CN105977222B (zh) * 2016-06-15 2019-09-17 苏州晶方半导体科技股份有限公司 半导体芯片封装结构及封装方法
CN105938804A (zh) * 2016-06-28 2016-09-14 中芯长电半导体（江阴）有限公司 一种晶圆级芯片封装方法及封装件
CN107068629B (zh) * 2017-04-24 2019-11-26 华天科技（昆山）电子有限公司 晶圆级芯片封装结构及其制作方法
CN107176586A (zh) * 2017-07-06 2017-09-19 苏州晶方半导体科技股份有限公司 一种mems芯片与asic的封装结构及封装方法
CN108336037B (zh) * 2017-09-30 2022-02-11 中芯集成电路（宁波）有限公司 一种晶圆级系统封装结构和电子装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740421A (zh) * 2008-11-17 2010-06-16 中芯国际集成电路制造(上海)有限公司 晶圆及制作方法、系统级封装结构及封装方法
CN104009014A (zh) * 2014-04-26 2014-08-27 华进半导体封装先导技术研发中心有限公司 集成无源器件晶圆级封装三维堆叠结构及制作方法
CN106449672A (zh) * 2015-08-04 2017-02-22 精材科技股份有限公司 感测晶片封装体及其制造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110875192A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
CN110875232A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
US11545468B2 (en) 2018-11-01 2023-01-03 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
WO2020088205A1 (en) * 2018-11-01 2020-05-07 Changxin Memory Technologies, Inc. Wafer stacking method and wafer stacking structure
CN109411473A (zh) * 2018-11-05 2019-03-01 长江存储科技有限责任公司 一种dram存储芯片及其制造方法
CN111377394B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377392A (zh) * 2018-12-27 2020-07-07 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377394A (zh) * 2018-12-27 2020-07-07 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
WO2020134589A1 (zh) * 2018-12-27 2020-07-02 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN111377392B (zh) * 2018-12-27 2023-08-25 中芯集成电路（宁波）有限公司上海分公司 Mems封装结构及其制作方法
CN110945660A (zh) * 2019-11-12 2020-03-31 深圳市汇顶科技股份有限公司 堆叠式的芯片、制造方法、图像传感器和电子设备
CN110945660B (zh) * 2019-11-12 2024-01-23 深圳市汇顶科技股份有限公司 堆叠式的芯片、制造方法、图像传感器和电子设备
CN111505477A (zh) * 2020-04-29 2020-08-07 江苏七维测试技术有限公司 传感器晶圆级测试方法
CN112956023A (zh) * 2021-02-05 2021-06-11 长江存储科技有限责任公司 倒装芯片堆叠结构及其形成方法
CN112956023B (zh) * 2021-02-05 2023-09-12 长江存储科技有限责任公司 倒装芯片堆叠结构及其形成方法
CN113223999A (zh) * 2021-04-01 2021-08-06 光华临港工程应用技术研发(上海)有限公司 晶圆键合方法及晶圆键合结构

Also Published As

Publication number Publication date
CN108597998A (zh) 2018-09-28
US20190115316A1 (en) 2019-04-18
CN108346639A (zh) 2018-07-31
WO2019062241A1 (zh) 2019-04-04
CN108346588B (zh) 2020-12-04
CN108666264A (zh) 2018-10-16
US20190103332A1 (en) 2019-04-04
US10756056B2 (en) 2020-08-25
KR20200106055A (ko) 2020-09-10
CN108336037A (zh) 2018-07-27
CN108335986B (zh) 2021-04-06
CN108346639B (zh) 2020-04-03
CN108666264B (zh) 2021-08-10
KR102400264B1 (ko) 2022-05-23
US10930617B2 (en) 2021-02-23
CN108335986A (zh) 2018-07-27
WO2019062238A1 (zh) 2019-04-04
WO2019062240A1 (zh) 2019-04-04
WO2019210617A1 (zh) 2019-11-07
US20190115314A1 (en) 2019-04-18
US10811385B2 (en) 2020-10-20
JP2021512506A (ja) 2021-05-13
CN108336037B (zh) 2022-02-11
CN108597998B (zh) 2022-04-08
JP7027577B2 (ja) 2022-03-01

Similar Documents

Publication Publication Date Title
CN108346588A (zh) 一种晶圆级系统封装方法以及封装结构
US8119500B2 (en) Wafer bonding
US8034713B2 (en) Method for stacking and interconnecting integrated circuits
CN110504247A (zh) 集成电路封装件及其形成方法
US8436448B2 (en) Through-silicon via with air gap
CN102446886B (zh) 3d集成电路结构及其形成方法
JP5182846B2 (ja) Ｍｅｍｓ素子のパッケージ及びその製造方法
CN106997855A (zh) 集成电路封装件及其形成方法
CN106688077A (zh) 用于三维集成电路(3d ic)集成的晶片转移的微机电系统(mems)接合释放结构及方法
CN103681606A (zh) 三维（3d）扇出封装机制
US11302662B2 (en) Semiconductor package with air gap and manufacturing method thereof
US20060226491A1 (en) Inverted multilayer semiconductor device assembly
CN107039249A (zh) 分割和接合方法及其形成的结构
CN109860064A (zh) 一种晶圆级系统封装方法以及封装结构
CN106463506A (zh) 用于金属栅极技术的p栅极到n栅极边界电阻的分路
CN111348613B (zh) 封装方法及封装结构
CN113611685B (zh) 半导体封装结构及其制备方法
TW202220223A (zh) 半導體元件中的片上電容器及其形成方法
CN106960813A (zh) 半导体结构及其制造方法
US10087072B2 (en) Microelectromechanical system structure including thermal stability layer whose material has higher growth temperature, and method for fabricating the same
CN103035566A (zh) 半导体器件的制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant