CN106688077A - 用于三维集成电路(3d ic)集成的晶片转移的微机电系统(mems)接合释放结构及方法 - Google Patents
用于三维集成电路(3d ic)集成的晶片转移的微机电系统(mems)接合释放结构及方法 Download PDFInfo
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Abstract
本发明提供一种用于制造具有两个或多于两个层的三维集成电路3D IC装置的微机电系统MEMS接合释放结构。所述MEMS接合释放结构包含可具有支柱或柱子结构的MEMS牺牲释放层,或替代地,用于接合及释放的连续牺牲层。
Description
技术领域
本文中所描述的各种实施例涉及三维集成电路(3D IC)装置,且更确切地说,涉及使用微机电机械系统(MEMS)接合释放结构进行的3D IC堆叠。
背景技术
通过在多个层中堆叠集成电路进行的三维电路集成允许电路设计者达成超出摩尔定律比例限制的经改善电力、性能、面积及成本(PPAC)的益处。已开发三维集成电路(3DIC)堆叠的各种方案(包含封装级硅(SiP)3D IC堆叠方案,例如电线接合、覆晶接合、硅穿孔(TSV)及硅插入件技术)以便在电路系统、层间链路及通孔中达成较高密度。在外观尺寸要求严格的装置中,需要具有多层堆叠的3D IC,例如智能电话及其它移动装置。除常规SiP3D IC堆叠方案之外,也已开发依序单体(sequential monolithic)3D IC(sM3DIC)技术。在sM3DIC中,将单一晶体半导体层依序集成且接合至已完成的下层互补金属氧化物半导体(CMOS)晶片上,且接着将上层CMOS建构于其上。
sM3DIC技术当前被视为有可能达成具有高层间链路/通孔密度(约大于1,000,000链路每平方毫米)的巨大PPAC益处。然而,sM3DIC技术当前面临需要在其可变得在商业上可行之前克服的若干重大过程集成挑战。举例来说,这些挑战可包含针对上层源极/汲极(S/D)欧姆接触、通道/井掺杂剂活化、S/D再结晶的低热预算/过程要求,及当通过后端过程(BEOL)完成的下层晶片进入前端过程(FEOL)时与铜互连件过程有关的可能的污染问题。
被称为平行单体3D IC(pM3DIC)的另一3D IC堆叠方案可能能够达成约100,000至1,000,000链路每平方毫米的层间链路/通孔密度。在pM3DIC中,使用晶片间(W2W)混合接合(金属间及氧化物间熔融接合)技术,其包含具有小于0.5μm的容许度的高精确度W2W对准过程,结合在移除块状硅之后具有小于5μm的厚度的极薄的上层晶片。高精确度W2W对准过程允许减小着陆垫大小,而极薄的上层晶片允许减小硅穿孔及穿氧化物层间通孔的大小,从而达成层间链路/通孔密度的增加。
即使pM3DIC方法当前被视为能够在更短的开发周期内提供中等程度的层间链路/通孔密度,但重大过程挑战仍可能存在。举例来说,虽然有可能通过使用现有晶片薄化技术(例如,机械晶片背磨,包含粗糙研磨及精细抛光,后接续化学机械抛光(CMP))将上层晶片薄化至5μm或小于5μm,但当晶片归因于在机械研磨过程期间在碰撞线(bumping line)中对CMOS装置的粒子诱发应力影响而薄化至25μm或小于25μm时,发现CMOS装置特性漂移。此外,通过现有机械晶片研磨及CMP技术,可能仍难以达成lμm或小于lμm的合理的总厚度变化(TTV)。
用于CMOS成像器的用于晶片薄化的另一种方法利用对P+蚀刻终止层的选择性湿式蚀刻。然而,此类方法可能对于获得合理的过程窗以控制精确及均匀层厚度、控制缺陷密度及管理剩余CMOS过程期间的硼掺杂扩散提出挑战。替代地,绝缘体上硅(SOI)晶片可提供可接受的解决方案以用于将晶片精确薄化至“内埋氧化物”(BOX)层,即,包含通过粗糙及精细研磨、后接续CMP且接着后接续进行Si及SiO2的选择性湿式蚀刻处理的硅(Si)层及二氧化硅(SiO2)层的层。SOI晶片可用作用于上层的开始晶片。然而,一旦经由碰撞线通过机械研磨处理晶片,晶片便可能实际上常常污染有例如金、银、锡或其它金属的重金属。在重金属污染的情况下,可能实际上不再在BEOL中处理晶片以添加额外背侧金属与精细间距金属层,从而就互连件组态而言损失3D集成灵活性。此外,例如晶片成本、材料利用及产量考虑因素的其它因素(例如)可能并不有利于pM3DIC集成。
发明内容
例示性实施例是关于用于晶片转移的微机电系统(MEMS)接合释放结构及其制造方法,以及三维集成电路装置及其通过使用用于晶片转移的MEMS接合释放结构进行的制造方法。
在实施例中,提供一种微机电系统(MEMS)接合释放结构,所述结构包括:载体晶片;所述载体晶片上的MEMS牺牲释放层;所述MEMS牺牲释放层上的半导体氧化物层;及所述半导体氧化物层上的有源半导体层。
在另一实施例中,提供一种制造微机电系统(MEMS)接合释放结构的方法,所述方法包括:提一载体晶片;在所述载体晶片上设置MEMS牺牲释放层;在所述MEMS牺牲释放层上设置半导体氧化物层;及在所述半导体氧化物层上设置有源半导体层。
在另一实施例中,提供一种三维集成电路装置,所述装置包括:衬底;包括一或多个金属层及一或多个层间介电质(ILD)层的一或多个集成电路的第一层;包括一或多个金属层及一或多个ILD层的一或多个集成电路的第二层;及接触一或多个集成电路的第二层中的ILD层中的至少一者的第一BOX层,其中移除所述第一BOX层的一或多个部分及一或多个集成电路的第二层中的ILD层中的所述至少一者的一或多个部分,以形成穿过所述第一BOX层及所述第二层中的ILD层中的所述至少一者的一或多个通孔。
在又一实施例中,提供一种制造三维集成电路装置的方法,所述方法包括:提供衬底;形成包括一或多个金属层及一或多个层间介电质(ILD)层的一或多个集成电路的第一层;形成包括一或多个金属层及一或多个ILD层的一或多个集成电路的第二层;形成接触一或多个集成电路的第二层中的ILD层中的至少一者的第一BOX层;及形成穿过所述第一BOX层及所述第二层中的ILD层中的所述至少一者的一或多个通孔。
附图说明
呈现附图以辅助描述实施例,且提供附图仅用于说明实施例而非对其进行限制。
图1为载体晶片及微机电系统(MEMS)牺牲释放层的截面图,所述图说明制造MEMS接合释放结构的初始步骤中的结构的实施例。
图2为载体晶片、MEMS牺牲释放层及氧化物层的截面图,所述图说明制造MEMS接合释放结构的第二步骤中的结构的实施例。
图3为载体晶片上的多个MEMS柱子或支柱的截面图,所述图说明制造MEMS接合释放结构的第三步骤中的结构的实施例。
图4A为转移衬底的实施例的截面图,所述转移衬底最初与如图1至3中所示的载体晶片分别提供,以用于制造MEMS接合释放结构。
图4B为在将转移衬底接合至载体衬底之前包括图3的结构的载体衬底的实施例的截面图。
图5A为在将图4A的转移衬底接合至载体衬底之前经翻转倒置的图4A的转移衬底的实施例的截面图。
图5B为准备好接受图5A的经翻转的转移衬底的接合的图4B的载体衬底的截面图。
图6为在将经翻转的转移衬底接合至载体衬底之后的经接合结构的实施例的截面图。
图7为展示当使转移衬底的另一部分不接触载体衬底时转移衬底的一部分与载体衬底分离的实施例的截面图。
图8为在转移衬底的一部分分离之后的MEMS支柱/柱子接合释放结构的截面图。
图9为已完成的MEMS支柱/柱子接合释放结构的一实施例的截面图。
图10A及10B分别为外部及内部MEMS柱子或支柱具有不同宽度的MEMS柱子/支柱接合释放结构的实施例的截面图及俯视图。
图11为具有连续的MEMS牺牲释放层的MEMS接合释放结构的替代性实施例的截面图。
图12为在将集成电路的一或多个额外层堆叠于第一层(层1)上之前制备的集成电路的层1的截面图。
图13为在将第二层(层2)堆叠于如图12中所示的集成电路的层1上之前在MEMS接合释放结构上制备的集成电路的层2的截面图,上文参看图1至11描述MEMS接合释放结构的实施例。
图14为说明在将如图12及13中所示的集成电路的层1及层2接合在一起之前层1及层2的对准的截面图。
图15为说明如图14中所示的集成电路的层1及层2的晶片间(W2W)接合的截面图。
图16为说明在移除MEMS接合释放结构的MEMS牺牲释放层之后的两层3D IC的实施例的截面图。
图17为在移除BOX层上的剩余的薄氧化物层以形成平滑顶表面之后的图16的3DIC的截面图。
图18为在于层2中的BOX层及BOX层正下方的层间介电质(ILD)层中形成通孔之后的图17的3D IC的截面图。
图19为在金属互连件形成为层2中的通孔之上的额外金属层的部分之后的图18的3D IC的截面图。
图20为在额外ILD层形成于通孔之上的额外金属层上之后的图19的3D IC的截面图。
图21为三层3D IC的实施例的截面图,其中通过使用MEMS接合释放结构而形成集成电路的层2及层1且将其组合在一起。
具体实施方式
在针对特定实施例的以下描述及相关图式中描述本发明的方面。可在不脱离本发明的范围的情况下设计出替代性实施例。另外,将不再详细地描述或将省略熟知元件以免混淆本发明的相关细节。
词“例示性”在本文中用以表示“充当实例、例子或说明”。本文中描述为“例示性”的任何实施例未必应解释为比其它实施例更佳或更有利。同样,术语“实施例”并不要求所有实施例包括所论述特征、优点或操作模式。
本文中使用的术语仅出于描述特定实施例的目的,且并不旨在限制所述实施例。如本文中所使用,除非上下文另外清楚地指示,否则单数形式“一”及“所述”旨在也包含复数形式。将进一步理解,术语“包括”或“包含”在于本文使用中时指定所陈述的特征、整数、步骤、操作、元件或组件的存在,但并不排除一或多个其它特征、整数、步骤、操作、元件、组件或其群组的存在或添加。此外,应理解,除非另外明确地陈述,否则词“或”具有与布林(Boolean)运算子“OR”相同的含义,即,其涵盖“……中任一者”及“两者”的可能性,且不限于“异或”(“XOR”)。
图1为载体晶片102及载体晶片102顶部上的微机电系统(MEMS)牺牲释放层104的截面图,所述图说明制造MEMS接合释放结构的初始步骤中的结构的实施例。在实施例中,载体晶片102包括硅晶片。MEMS牺牲释放层104可包括例如钼(Mo)、锗(Ge)、氧化锗(GeOx)、包含二氧化硅(SiO2)的氧化硅(SiOx)或其它类型的牺牲材料的材料。举例来说,在实施例中,可通过使用常规沉积过程(例如,化学气相沉积(CVD)、等离子增强化学气相沉积(PECVD)、物理气相沉积(PVD)过程)将MEMS牺牲释放层104设置于载体晶片102上。
图2为载体晶片102、载体晶片102顶部上的MEMS牺牲释放层104及MEMS牺牲释放层104顶部上的用于进行氧化物间熔融接合的氧化物层106的截面图,所述图说明制造MEMS接合释放结构的第二步骤中的结构的实施例。在实施例中,氧化物层106包括用于进行氧化物间接合的薄氧化物材料,例如二氧化硅(SiO2)。举例来说,在一实施例中,可通过使用例如CVD过程的常规沉积过程将氧化物层106设置于MEMS牺牲释放层104上。举例来说,在另一实施例中,可通过等离子增强化学气相沉积(PECVD)过程将氧化物层106设置于MEMS牺牲释放层104上。
图3为载体晶片102上具有多个MEMS柱子或支柱108a、108b、108c……的MEMS柱子/支柱接合释放结构的截面图,所述图说明制造MEMS接合释放结构的第三步骤中的结构的实施例。在实施例中,MEMS柱子或支柱108a、108b、108c……中的每一者包括载体晶片102顶部上的MEMS牺牲释放层104及MEMS牺牲释放层104顶部上的氧化物层106。举例来说,在实施例中,可通过图案化及蚀刻如图2中所示的连续的MEMS牺牲释放层104及氧化物层106而形成如图3中所示的MEMS柱子或支柱108a、108b、108c……。
尽管图3的截面图将多个MEMS柱子或支柱108a、108b、108c……展示为基本上彼此相同,具有基本上相等间距,但给定载体晶片上的MEMS柱子或支柱无需具有相同宽度,且邻近MEMS柱子或支柱之间的间距无需相同,如下文将参考如图10A及10B中所示的实施例加以描述。此外,在替代性实施例中,无需制造MEMS柱子或支柱,且可改为将MEMS牺牲释放层104形成为连续层,下文将参考如图11中所示的实施例加以描述。
图4A为最初与如图1至3中所示的载体晶片102分别提供的转移衬底200的实施例的截面图。在图4A中所示的实施例中,转移衬底200包括具有对置表面204及206的块状晶片202,及分别安置于块状晶片202的表面204及206上的两个半导体氧化物层208及210。在此实施例中,使两个半导体氧化物层208及210热氧化,且将其定位成包夹块状晶片202。替代地,在块状晶片202的表面204上仅设置一个半导体氧化物层208以用于说明。在实施例中,转移衬底200的块状晶片202包括硅晶片,而半导体氧化物层208及210中的每一者包括SiO2。举例来说,在实施例中,可通过使块状硅晶片202的表面热氧化而在块状硅晶片202上形成SiO2层208及210。
在实施例中,将掺杂剂植入至接触半导体氧化物层208的靠近块状晶片202的表面204的部分212。在实施例中,其中通过如图4A中所示的两个半导体氧化物层208及210包夹块状晶片202,可将掺杂剂植入仅应用于接触半导体层中的一者的靠近块状晶片的表面中的一者的部分,例如,接触半导体氧化物层208的靠近块状晶片202的表面204的部分212。举例来说,在实施例中,可将例如H+德耳塔植入的离子植入过程应用于靠近块状晶片202的表面204的部分212。图4B为载体衬底300的截面图,所述载体衬底包含载体晶片102及多个MEMS柱子或支柱108a、108b、108c……,在将图4A的转移衬底200翻转且接合至图4B的载体衬底300之前,每一MEMS柱子或支柱具有如图3中所示的MEMS牺牲释放层104及氧化物层106。
实际上,自转移衬底200的块状晶片202的顶表面204而非底表面206植入掺杂剂通常更容易,图4A中展示植入的初始定向,所述初始定向与如图4B中所示的MEMS柱子/支柱接合释放结构的初始定向一致。在实施例中,在将转移衬底200接合至载体衬底300之前,将转移衬底200翻转倒置,如图5A的截面图中所示,图5B中展示载体衬底300的截面图。
图6为在将经翻转的转移衬底200接合至载体衬底300之后的经接合结构的实施例的截面图,所述经接合结构为载体衬底300与转移衬底200的组合。在图6中所示的实施例中,接触块状晶片202(H+德耳塔植入应用于所述块状晶片)的表面204的半导体氧化物层208直接接合至MEMS柱子或支柱108a、108b、108c……中的每一者的氧化物层106。
图7为展示当使块状晶片202的经H+德耳塔植入部分212及块状晶片202的经H+德耳塔植入部分212的表面204上的半导体氧化物层208不接触载体衬底300时转移衬底200的一部分与载体衬底300的分离的实施例的截面图。在实施例中,与块状晶片202的经H+德耳塔植入部分212对置的块状晶片202的未经掺杂部分220及表面206上的半导体氧化物层210与块状晶片212的经H+德耳塔植入部分212分离。举例来说,可通过断裂达成块状晶片202的未经掺杂部分220与块状晶片202的经H+德耳塔植入部分212的分离。
图8为在转移衬底的块状晶片的未经掺杂部分与块状晶片202的经H+德耳塔植入部分212分离或断裂之后的MEMS支柱/柱子接合释放结构的截面图。如图8中所示,块状晶片202的经H+德耳塔植入部分212及块状晶片202的经H+德耳塔植入部分212的表面204上的半导体氧化物层208现在为MEMS柱子/支柱接合释放结构的集成部分,其也包含载体晶片102及多个MEMS柱子或支柱108a、108b、108c……,每一MEMS柱子或支柱具有MEMS牺牲释放层104及薄氧化物层106。
在实施例中,可包括SiO2层的半导体氧化物层208直接定位于MEMS柱子或支柱108a、108b、108c……中的每一者的薄氧化物层106上。在转移衬底200的块状晶片202包括硅且转移衬底200的半导体氧化物层208包括SiO2的一实施例中,块状晶片202的经H+德耳塔植入部分212及半导体氧化物层208一起形成绝缘体上硅(SOI)衬底400。此类SOI衬底400也可被视为3D IC的制造中的SiO2BOX层,下文将参考图13至21加以描述。
图9为在SOI衬底400经受晶片表面修整过程之后的已完成的MEMS支柱/柱子接合释放结构的实施例的截面图。在实施例中,修整过程可包含(例如)用以使块状晶片202的经H+德耳塔植入部分212的顶表面230平滑的接合后化学机械抛光(CMP)过程,所述情形起因于块状晶片的未经掺杂部分与如上文参考图7所描述的MEMS支柱/柱子接合释放结构的分离或断裂。举例来说,在另一实施例中,修整过程也可包含对于SOI衬底400的臭氧氧化处理。
图10A及10B分别为跨越半导体晶片的MEMS柱子/支柱接合释放结构的一实施例的侧视图/截面图及俯视图,其中MEMS柱子或支柱中的一些MEMS柱子或支柱可具有不同宽度。在图10A及10B中,将多个内部MEMS柱子或支柱108a、108b、108c……设置为与上文参考图9所描述的结构类似的MEMS柱子/支柱接合释放结构的部分。除内部MEMS柱子或支柱108a、108b、108c……之外,图10A及10B也展示环绕内部MEMS柱子或支柱108a、108b、108c……的多个外部MEMS柱子或支柱150a、150b……。在实施例中,外部MEMS柱子或支柱150a、150b……中的每一者具有比载体晶片102上的内部MEMS柱子或支柱108a、108b、108c……中的每一者的宽度大的宽度,以在牺牲层释放过程期间提供整个经接合晶片的足够的结构支撑。除具有不同宽度外,外部MEMS柱子或支柱150a、150b……具有与内部MEMS柱子或支柱108a、108b、108c……的两层结构相同的两层结构,包含MEMS牺牲释放层104及薄氧化物层106。在另一实施例中,也沿载体晶片102的外部周边设置密封环160。在一实施例中,密封环160也具有与内部及外部MEMS柱子或支柱的两层结构相同的两层结构,包含MEMS牺牲释放层104及薄氧化物层106。
图11为MEMS接合释放结构的替代性实施例的截面图。代替上文所描述的MEMS柱子或支柱,图11中所示的实施例中的MEMS接合释放结构包含载体晶片102上的连续的MEMS牺牲释放层504,以形成载体衬底500。在实施例中,将可通过H+德耳塔植入过程掺杂的包括半导体氧化物层208及块状晶片202的层的SOI衬底400接合至载体衬底500。举例来说,在实施例中,载体晶片102包括硅,而块状晶片202包括经H+德耳塔掺杂的硅。举例来说,在实施例中,跨越载体晶片102而连续安置的MEMS牺牲释放层504可包括例如Mo、Ge、GeOx或包含SiO2的SiOx的牺牲材料。在实施例中,SOI衬底400的半导体氧化物层208包括SiO2。
图12至21为说明用于通过使用一或多个MEMS接合释放结构堆叠集成电路的多个层而制造3D IC的过程的实施例的横截面图,MEMS接合释放结构的实施例在上文关于图1至11加以描述。图12为集成电路的第一层(层1)的截面图。可以常规方式制备可包括块状硅处置器或绝缘体上硅(SOI)衬底的用于层1的晶片1202。在图12中所示的实施例中,层1中的集成电路可包含一或多个金属层(Ml、M2、M3、M4层)1204、1206、1208及1210,以及一或多个层间介电质(ILD)层(ILD-0、ILD-1、ILD-2、ILD-3层)1212、1214、1216及1218。
也可穿过ILD层中的一或多者设置多个通孔,以用于达成金属层中的一些金属层或全部之间的电互连,包含(例如)如图12中所示的通孔(VI、V2、V3)1220、1222及1224。在一实施例中,在顶部金属层(M4层)1210上设置额外ILD层(ILD-4层)1230,以用于与集成电路的第二层(层2)进行氧化物接合,下文将参考图13加以描述。参考图12,在顶部ILD层1230中的顶部金属层(M4层)1210中的金属接点中的至少一些金属接点的顶部上设置例如接合衬垫1240及1242的多个接合衬垫,以用于与集成电路的第二层中的对应接合衬垫接合。
图13为在MEMS接合释放结构上制备的集成电路的第二层(层2)的截面图,上文参考图1至11描述MEMS接合释放结构的实施例。在图13中,提供如图10A中所示的MEMS柱子/支柱接合释放结构,所述MEMS柱子/支柱接合释放结构包括载体晶片102、多个内部MEMS柱子或支柱108a、108b、108c……、多个外部MEMS柱子或支柱150a、150b……及密封环160(各自具有MEMS牺牲释放层104及薄氧化物层106),及也被称为BOX层的可包括二氧化硅(SiO2)层及活性硅层的SOI衬底400。参考图13,在SOI衬底或BOX层400的顶部上设置多个金属层(Ml、M2、M3、M4层)1302、1304、1306及1308以及多个ILD层(ILD-0、ILD-1、ILD-2、ILD-3层)1310、1312、1314及1316。
与层1类似,集成电路的层2也可包含多个通孔(VI、V2、V3)1320、1322及1324,其穿过ILD层中的一或多者设置以用于达成金属层中的一些金属层或全部之间的电互连。此外,与层1类似,集成电路的层2也可包含顶部金属层(M4层)1308上的顶部ILD层(ILD-4层)1330以用于进行氧化物接合。此外,在顶部ILD层1330中在顶部金属层(M4层)1308中的金属接点中的至少一些金属接点的顶部上设置例如接合衬垫1340及1342的多个接合衬垫,以用于与集成电路的第一层(层1)中的对应接合衬垫接合。
图14为说明在将集成电路的层1及层2接合在一起之前层1及层2的对准的截面图。在图14中,将集成电路的层2自图13的截面图中的定向翻转倒置。在图14中,在将附接至MEMS柱子/支柱接合释放结构的BOX层400的集成电路的层2翻转倒置之后,使层2的接合衬垫1342及1340分别与层1的接合衬垫1240及1242对准。如图14中所示,给定层的每一接合衬垫的宽度无需与其它层的对应接合衬垫的宽度相同,只要对应衬垫彼此对准以使得一旦将衬垫彼此接合便建立足够良好的电连接(即,足够的接触区域)即可。
图15为说明集成电路的层2及层1的晶片间(W2W)接合的截面图。在图15中,在将层2接合至层1之后,层2的接合衬垫1342及1340分别直接接触层1的接合衬垫1240及1242,从而在对应接合衬垫之间建立电连接。此外,层1的顶部ILD层(ILD-4层)1230也直接接触层2的顶部ILD层(ILD-4层)1330,从而形成两层3D IC。
图16为说明在移除内部MEMS柱子或支柱108a、108b、108c……、外部MEMS柱子或支柱150a、150b……及密封环160中的每一者中的MEMS牺牲释放层104之后的两层3D IC的一实施例的截面图,从而使得内部及外部MEMS柱子或支柱及密封环中的每一者中的薄氧化物层106不接触BOX层400。在MEMS接合释放结构包含如图2中所示及上文所描述的多个MEMS柱子或支柱的一实施例中,在移除MEMS牺牲释放层104之后的薄氧化物层106将呈如图16中所示的BOX层400上的小突起的形式。可通过以湿式或乾式蚀刻化学方法进行的释放-蚀刻过程容易地移除MEMS牺牲释放层104。举例来说,将XeF2广泛用作用于Mo或Si牺牲层的乾式蚀刻释放化学方法。在移除MEMS牺牲释放层的情况下,载体晶片102被完全释放或自集成电路的层2拆离。
图17为在移除BOX层400上的剩余薄氧化物层106以形成BOX层400的平滑顶表面1702之后的图16的3D IC的截面图。可通过常规抛光过程(例如,在实施例中之后端过程(BEOL)中的化学机械抛光(CMP)过程)使BOX层400的顶表面1702平滑。图18为在穿过BOX层400及在BOX层400正下方的层2的ILD层(ILD-0层)1310设置多个通孔1802a、1802b、1802c……之后的图17的3D IC的截面图。可通过以常规方式移除BOX层400的指明部分及在BOX层400正下方的ILD层(ILD-0层)1310的对应部分形成通孔1802a、1802b、1802c。在通孔形成之后,对这些通孔填充金属(例如,Cu),后接续进行通常用于BEOL中的CMP过程。
图19为在将一或多个金属互连件1902a、1902b、1902c……形成为通孔1802a、1802b、1802c……之上的额外金属层(M5层)的部分之后的图18的3D IC的截面图。图20为在一实施例中在将一或多个额外ILD层(ILD-5、ILD-6层)2002及2004形成于M5层上之后的图19的3D IC的截面图。在另一实施例中,在ILD-5层2002的顶部上及ILD-6层2004内设置具有金属互连件2006a、2006b、2006c……的另一额外金属层(M6层)。在又一实施例中,在ILD-5层2002中设置多个通孔2008a、2008b、2008c……以允许达成M5与M6层的金属互连件之间的电连接。在一实施例中,在M6层的一或多个金属互连件的顶部上形成例如接合衬垫2010a及2010b的一或多个接合衬垫。
图21为三层3D IC的实施例的截面图,其中通过上文参考图12至20所描述的接合过程形成集成电路的层2及层1且将其组合在一起。在图21中所示的实施例中,以与上文所描述的形成层2且将层2接合至层1的方式相同的方式在层2的顶部上形成集成电路的额外层(层3)。举例来说,在图21中,在晶片间(W2W)混合接合过程中,将接合衬垫2110a及2110b设置于层3中且使其分别与层2的接合衬垫2010a及2010b对准。
在图21中,针对层3设置额外BOX层2120,所述额外BOX层2120通过上文所描述的MEMS接合释放结构的实施例中的二氧化硅(SiO2)层及活性硅层形成。此外,可在BOX层2120的顶部上设置一或多个金属层(M5、M6层)及一或多个ILD层(ILD-5、ILD-6层),且可在实施例中在M6层的顶部上设置一或多个接合衬垫2130a及2130b,以允许在W2W混合接合过程中将集成电路的额外层(图中未展示)接合至层3。可以类似方式堆叠集成电路的多个层以产生多层3D IC。
尽管上文所描述的实施例中的一些实施例涉及硅集成电路的处理,但本发明的原理也适用于基于其它材料的集成电路。在其它实施例中,上层晶片的半导体材料可能并非硅,例如硅锗(SiGe)、砷化镓(GaAs)、磷化铟(InP)、氮化镓(GaN)或其它半导体。此外,下层晶片可为例如绝缘衬底材料的非半导体。举例来说,用于平板显示器或感测器的玻璃、石英衬底或甚至玻璃面板可用作用于下层晶片的绝缘衬底材料。此外,根据本发明实施例的MEMS接合释放结构允许通过控制每一层的BOX层的厚度,而非通过例如粗糙及精细研磨的常规机械研磨过程,进行精确上层晶片薄化及厚度控制,从而达成极小的晶片总厚度变化(TTV)。
此外,通过避免对常规机械晶片研磨过程的需要,可避免归因于在机械晶片研磨期间引入的机械应力而产生的对上层中的电路元件的电性质的有害影响。此外,通过MEMS牺牲层释放过程,可达成多层3D IC装置的制造中的较高产量,这是因为通过蚀刻进行的MEMS牺牲层释放可比耗时的机械研磨过程更快。通过在3D IC装置的制造中使用根据本发明实施例的MEMS接合释放结构,可通过避免由于常规机械研磨过程产生的半导体材料的浪费及电路元件上的机械应力而达成较低的材料成本、较高的产量及较佳的材料利用。
虽然前述揭示内容描述说明性实施例,但应注意,可在不偏离所附权利要求书的范围的情况下在本文中进行各种改变及修改。除非另外明确地陈述,否则根据本文中所描述的实施例的方法及设备技术方案中的功能、步骤或动作无需按任何特定次序执行。此外,尽管可能以单数形式描述或请求元件,但除非明确地陈述对单数形式的限制,否则涵盖复数形式。
Claims (40)
1.一种微机电系统MEMS接合释放结构,其包括:
载体晶片;
所述载体晶片上的MEMS牺牲释放层;
所述MEMS牺牲释放层上的半导体氧化物层;及
所述半导体氧化物层上的有源半导体层。
2.根据权利要求1所述的结构,其中所述半导体氧化物层包括二氧化硅SiO2层。
3.根据权利要求2所述的结构,其中所述有源半导体层包括所述SiO2层上的活性硅层。
4.根据权利要求1所述的结构,其中所述MEMS牺牲释放层包括彼此间隔开的多个MEMS柱子。
5.根据权利要求4所述的结构,其中所述MEMS柱子中的每一者包括牺牲释放材料。
6.根据权利要求5所述的结构,其中所述牺牲释放材料包括选自由以下各者组成的群的材料:钼Mo、锗Ge、氧化锗GeOx及氧化硅SiOx。
7.根据权利要求5所述的结构,其中所述MEMS柱子中的每一者进一步包括所述牺牲释放材料上的氧化物材料,以用于将所述牺牲释放材料与所述半导体氧化物层接合。
8.根据权利要求4所述的结构,其中所述MEMS柱子包括所述载体晶片上的一或多个内部MEMS柱子及一或多个外部MEMS柱子,所述一或多个外部MEMS柱子至少部分地环绕所述一或多个内部MEMS柱子。
9.根据权利要求1所述的结构,其中所述MEMS牺牲释放层包括所述载体晶片上的连续牺牲释放层。
10.根据权利要求1所述的结构,其中所述半导体氧化物层及所述有源半导体层一起形成内埋氧化物BOX层。
11.一种制造微机电系统MEMS接合释放结构的方法,其包括:
提供载体晶片;
在所述载体晶片上设置MEMS牺牲释放层;
在所述MEMS牺牲释放层上设置半导体氧化物层;及
在所述半导体氧化物层上设置有源半导体层。
12.根据权利要求11所述的方法,其中设置所述MEMS牺牲释放层的所述步骤包括:
在所述载体晶片上沉积牺牲释放材料;及
在所述牺牲释放材料上沉积氧化物材料。
13.根据权利要求12所述的方法,其中沉积所述牺牲释放材料的所述步骤包括沉积选自由以下各者组成的群的材料的步骤:钼Mo、锗Ge、氧化锗GeOx及氧化硅SiOx。
14.根据权利要求12所述的方法,其中沉积所述牺牲释放材料的所述步骤包括通过化学气相沉积CVD、等离子增强化学气相沉积PECVD或物理气相沉积PVD沉积所述牺牲释放材料的步骤。
15.根据权利要求12所述的方法,其中沉积所述氧化物材料的所述步骤包括通过化学气相沉积CVD、等离子增强化学气相沉积PECVD或物理气相沉积PVD沉积所述氧化物材料的步骤。
16.根据权利要求11所述的方法,其进一步包括以下步骤:
提供转移衬底,所述转移衬底包括块状晶片及所述块状晶片的表面上的至少一半导体氧化物层;及
将H+德耳塔植入应用于接触所述半导体氧化物层的靠近所述块状晶片的所述表面的所述块状晶片的第一部分。
17.根据权利要求16所述的方法,其进一步包括将所述转移衬底接合至载体衬底,所述载体衬底包括所述载体晶片、所述MEMS牺牲释放层、所述半导体氧化物层及所述有源半导体层。
18.根据权利要求17所述的方法,其中将所述转移衬底接合至所述载体衬底的所述步骤包括将所述转移衬底的所述半导体氧化物层接合至所述MEMS牺牲释放层的步骤。
19.根据权利要求18所述的方法,其进一步包括:
将所述转移衬底的所述块状晶片的第二部分与所述载体衬底分离;及
使具有H+德耳塔植入的所述块状晶片的所述第一部分接触所述半导体氧化物层。
20.根据权利要求19所述的方法,其中所述转移衬底的所述半导体氧化物层包括二氧化硅SiO2,且其中所述转移衬底的所述块状晶片包括硅Si。
21.一种三维集成电路装置,其包括:
衬底;
一或多个集成电路的第一层,其包括一或多个金属层及一或多个层间介电质ILD层;
一或多个集成电路的第二层,其包括一或多个金属层及一或多个ILD层;及
第一内埋氧化物BOX层,其接触一或多个集成电路的所述第二层中的所述ILD层中的至少一者,其中所述第一BOX层的一或多个部分及一或多个集成电路的所述第二层中的所述ILD层中的所述至少一者的一或多个部分经移除,以形成穿过所述第一BOX层及所述第二层中的所述ILD层中的所述至少一者的一或多个通孔。
22.根据权利要求21所述的装置,其进一步包括所述一或多个通孔之上的一或多个金属互连件。
23.根据权利要求22所述的装置,其进一步包括所述金属互连件上的一或多个金属层及一或多个ILD层。
24.根据权利要求23所述的装置,其进一步包括所述一或多个金属层上的多个接合衬垫。
25.根据权利要求21所述的装置,其中所述第一BOX层包括硅Si层及二氧化硅SiO2层。
26.根据权利要求21所述的装置,其中一或多个集成电路的所述第一层进一步包括第一组一或多个接合衬垫,其中一或多个集成电路的所述第二层进一步包括第二组一或多个接合衬垫,且其中所述第一组中的所述接合衬垫中的至少一者连接至所述第二组中的所述接合衬垫中的至少一者。
27.根据权利要求21所述的装置,其进一步包括:
一或多个集成电路的一第三层,其包括一或多个金属层及一或多个ILD层;
第二BOX层,其接触一或多个集成电路的所述第三层中的所述ILD层中的至少一者,其中所述第二BOX层的一或多个部分及一或多个集成电路的所述第三层中的所述ILD层中的所述至少一者的一或多个部分经移除,以形成穿过所述第二BOX层及所述第三层中的所述ILD层中的所述至少一者的一或多个通孔。
28.根据权利要求27所述的装置,其中一或多个集成电路的所述第二层进一步包括第二组一或多个接合衬垫,其中一或多个集成电路的所述第三层进一步包括第三组一或多个接合衬垫,且其中所述第二组中的所述接合衬垫中的至少一者连接至所述第三组中的所述接合衬垫中的至少一者。
29.根据权利要求21所述的装置,其中所述衬底包括绝缘体上硅SOI衬底。
30.根据权利要求21所述的装置,其中所述衬底包括块状硅Si处置器。
31.一种制造三维集成电路装置的方法,其包括:
提供衬底;
形成一或多个集成电路的第一层,所述第一层包括一或多个金属层及一或多个层间介电质ILD层;
形成一或多个集成电路的第二层,所述第二层包括一或多个金属层及一或多个ILD层;
形成第一内埋氧化物BOX层,所述第一内埋氧化物BOX层接触一或多个集成电路的所述第二层中的所述ILD层中的至少一者;及
形成穿过所述第一BOX层及所述第二层中的所述ILD层中的所述至少一者的一或多个通孔。
32.根据权利要求31所述的方法,其中形成一或多个集成电路的所述第二层的所述步骤包括使一或多个集成电路的所述第二层中的一或多个接合衬垫与一或多个集成电路的所述第一层中的一或多个接合衬垫对准。
33.根据权利要求32所述的方法,其中形成一或多个集成电路的所述第二层的所述步骤进一步包括将一或多个集成电路的所述第二层中的所述一或多个接合衬垫与一或多个集成电路的所述第一层中的所述一或多个接合衬垫接合。
34.根据权利要求31所述的方法,其中形成一或多个集成电路的所述第二层的所述步骤包括在微机电系统MEMS接合释放结构上形成一或多个集成电路的所述第二层,所述MEMS接合释放结构包括载体晶片、所述载体晶片上的MEMS牺牲释放层及所述MEMS牺牲释放层上的所述第一BOX层。
35.根据权利要求34所述的方法,其进一步包括通过释放所述MEMS牺牲释放层而将所述载体晶片与一或多个集成电路的所述第二层分离。
36.根据权利要求35所述的方法,其进一步包括:
在所述一或多个通孔之上形成一或多个金属互连件;
在所述金属互连件上形成一或多个金属层及一或多个ILD层;及
在所述一或多个金属层上形成多个接合衬垫。
37.根据权利要求31所述的方法,其进一步包括:
形成一或多个集成电路的第三层,所述第三层包括一或多个金属层及一或多个ILD层;及
形成第二BOX层,所述第二BOX层接触一或多个集成电路的所述第三层中的所述ILD层中的至少一者。
38.根据权利要求37所述的方法,其进一步包括形成穿过所述第二BOX层及所述第三层中的所述ILD层中的所述至少一者的一或多个通孔。
39.根据权利要求37所述的方法,其中形成一或多个集成电路的所述第三层的所述步骤包括在微机电系统MEMS接合释放结构上形成一或多个集成电路的所述第三层,所述MEMS接合释放结构包括载体晶片、所述载体晶片上的MEMS牺牲释放层及所述MEMS牺牲释放层上的所述第二BOX层。
40.根据权利要求39所述的方法,其进一步包括通过释放所述MEMS牺牲释放层而将所述载体晶片与一或多个集成电路的所述第三层分离。
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US14/498,965 | 2014-09-26 | ||
PCT/US2015/048930 WO2016048649A1 (en) | 2014-09-26 | 2015-09-08 | Microelectromechanical system (mems) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3d ic) integration |
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CN (1) | CN106688077A (zh) |
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HK (1) | HK1232339A1 (zh) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110556290A (zh) * | 2018-06-01 | 2019-12-10 | 辛纳普蒂克斯公司 | 堆叠晶片集成电路 |
CN110660687A (zh) * | 2018-06-28 | 2020-01-07 | 台湾积体电路制造股份有限公司 | 接合支撑结构、多个半导体晶圆及其接合方法 |
CN111092067A (zh) * | 2018-10-24 | 2020-05-01 | 三星电子株式会社 | 半导体封装件 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3007224A1 (en) * | 2014-10-08 | 2016-04-13 | Nxp B.V. | Metallisation for semiconductor device |
US10049915B2 (en) * | 2015-01-09 | 2018-08-14 | Silicon Genesis Corporation | Three dimensional integrated circuit |
JP6784969B2 (ja) * | 2015-10-22 | 2020-11-18 | 天馬微電子有限公司 | 薄膜デバイスとその製造方法 |
FR3053159B1 (fr) * | 2016-06-23 | 2019-05-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d'une structure de transistors comportant une etape de bouchage |
US10438838B2 (en) * | 2016-09-01 | 2019-10-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and related method |
US10714446B2 (en) | 2017-03-30 | 2020-07-14 | Intel Corporation | Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such |
US11211328B2 (en) * | 2017-10-16 | 2021-12-28 | SK Hynix Inc. | Semiconductor memory device of three-dimensional structure |
DE102019102323A1 (de) * | 2018-02-02 | 2019-08-08 | Infineon Technologies Ag | Waferverbund und Verfahren zur Herstellung von Halbleiterbauteilen |
US10504873B1 (en) | 2018-06-25 | 2019-12-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | 3DIC structure with protective structure and method of fabricating the same and package |
US10796976B2 (en) | 2018-10-31 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
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US11195818B2 (en) | 2019-09-12 | 2021-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit |
US11063022B2 (en) * | 2019-09-17 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package and manufacturing method of reconstructed wafer |
US11158580B2 (en) | 2019-10-18 | 2021-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with backside power distribution network and frontside through silicon via |
US10910272B1 (en) * | 2019-10-22 | 2021-02-02 | Sandisk Technologies Llc | Reusable support substrate for formation and transfer of semiconductor devices and methods of using the same |
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US11088116B2 (en) * | 2019-11-25 | 2021-08-10 | Sandisk Technologies Llc | Bonded assembly containing horizontal and vertical bonding interfaces and methods of forming the same |
US11488939B2 (en) * | 2020-01-20 | 2022-11-01 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least one vertical bus |
US20240096798A1 (en) * | 2020-01-20 | 2024-03-21 | Monolithic 3D Inc. | 3d semiconductor devices and structures with electronic circuit units |
US11270988B2 (en) * | 2020-01-20 | 2022-03-08 | Monolithic 3D Inc. | 3D semiconductor device(s) and structure(s) with electronic control units |
US11315903B2 (en) * | 2020-03-05 | 2022-04-26 | Nanya Technology Corporation | Semiconductor device with connecting structure and method for fabricating the same |
US11127628B1 (en) * | 2020-03-16 | 2021-09-21 | Nanya Technology Corporation | Semiconductor device with connecting structure having a step-shaped conductive feature and method for fabricating the same |
US11715755B2 (en) * | 2020-06-15 | 2023-08-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for forming integrated high density MIM capacitor |
KR20220017175A (ko) * | 2020-08-04 | 2022-02-11 | 에스케이하이닉스 주식회사 | 웨이퍼 대 웨이퍼 본딩 구조를 갖는 반도체 장치 및 그 제조방법 |
US11817392B2 (en) * | 2020-09-28 | 2023-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit |
US11552055B2 (en) * | 2020-11-20 | 2023-01-10 | Qualcomm Incorporated | Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking, and related fabrication methods |
US11682652B2 (en) * | 2021-03-10 | 2023-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Notched wafer and bonding support structure to improve wafer stacking |
CN113912005B (zh) * | 2021-10-08 | 2023-02-03 | 天津大学 | 一种基于柔性铰链结构的xy全解耦微运动平台 |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010005059A1 (en) * | 1999-12-28 | 2001-06-28 | Fuji Xerox Co., Ltd. And Mitsumasa Koyanagi | Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor |
US20020171080A1 (en) * | 2001-05-18 | 2002-11-21 | Faris Sadeg M. | Thin films and production methods thereof |
US20070054455A1 (en) * | 2005-09-12 | 2007-03-08 | Texas Instruments Inc. | Method to obtain uniform nitrogen profile in gate dielectrics |
US20070135013A1 (en) * | 2001-09-12 | 2007-06-14 | Faris Sadeg M | Microchannel plate and method of manufacturing microchannel plate |
US20070254455A1 (en) * | 2006-04-28 | 2007-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit, manufacturing method thereof, and semiconductor device using semiconductor integrated circuit |
US20080291767A1 (en) * | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Multiple wafer level multiple port register file cell |
US20090294814A1 (en) * | 2008-06-03 | 2009-12-03 | International Business Machines Corporation | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof |
JP2010504649A (ja) * | 2006-09-20 | 2010-02-12 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法 |
US20120193752A1 (en) * | 2011-01-29 | 2012-08-02 | International Business Machines Corporation | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby |
US20130214423A1 (en) * | 2011-03-31 | 2013-08-22 | Soitec | Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices |
US8729673B1 (en) * | 2011-09-21 | 2014-05-20 | Sandia Corporation | Structured wafer for device processing |
US20140264770A1 (en) * | 2013-03-15 | 2014-09-18 | Sandia Corporation | Method of forming through substrate vias (tsvs) and singulating and releasing die having the tsvs from a mechanical support substrate |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6888608B2 (en) | 1995-09-06 | 2005-05-03 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US8330559B2 (en) | 2010-09-10 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level packaging |
EP2656388B1 (en) * | 2010-12-24 | 2020-04-15 | QUALCOMM Incorporated | Trap rich layer for semiconductor devices |
US8368152B2 (en) | 2011-04-18 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | MEMS device etch stop |
-
2014
- 2014-09-26 US US14/498,965 patent/US9922956B2/en not_active Expired - Fee Related
-
2015
- 2015-09-08 JP JP2017514278A patent/JP2017536248A/ja active Pending
- 2015-09-08 WO PCT/US2015/048930 patent/WO2016048649A1/en active Application Filing
- 2015-09-08 EP EP15767645.3A patent/EP3198634A1/en not_active Withdrawn
- 2015-09-08 BR BR112017006167A patent/BR112017006167A2/pt not_active Application Discontinuation
- 2015-09-08 KR KR1020177007903A patent/KR20170066354A/ko unknown
- 2015-09-08 CN CN201580048185.6A patent/CN106688077A/zh active Pending
- 2015-09-08 SG SG11201700918RA patent/SG11201700918RA/en unknown
- 2015-09-21 TW TW104131176A patent/TWI585820B/zh not_active IP Right Cessation
-
2017
- 2017-06-14 HK HK17105914.3A patent/HK1232339A1/zh unknown
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010005059A1 (en) * | 1999-12-28 | 2001-06-28 | Fuji Xerox Co., Ltd. And Mitsumasa Koyanagi | Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor |
US20020171080A1 (en) * | 2001-05-18 | 2002-11-21 | Faris Sadeg M. | Thin films and production methods thereof |
US20070135013A1 (en) * | 2001-09-12 | 2007-06-14 | Faris Sadeg M | Microchannel plate and method of manufacturing microchannel plate |
US20070054455A1 (en) * | 2005-09-12 | 2007-03-08 | Texas Instruments Inc. | Method to obtain uniform nitrogen profile in gate dielectrics |
US20070254455A1 (en) * | 2006-04-28 | 2007-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor integrated circuit, manufacturing method thereof, and semiconductor device using semiconductor integrated circuit |
US20110171813A1 (en) * | 2006-09-20 | 2011-07-14 | The Board Of Trustees Of The University Of Illinois | Release Strategies for Making Transferable Semiconductor Structures, Devices and Device Components |
JP2010504649A (ja) * | 2006-09-20 | 2010-02-12 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法 |
US20080291767A1 (en) * | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Multiple wafer level multiple port register file cell |
US20090294814A1 (en) * | 2008-06-03 | 2009-12-03 | International Business Machines Corporation | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof |
US20120193752A1 (en) * | 2011-01-29 | 2012-08-02 | International Business Machines Corporation | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby |
US20130214423A1 (en) * | 2011-03-31 | 2013-08-22 | Soitec | Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices |
US8729673B1 (en) * | 2011-09-21 | 2014-05-20 | Sandia Corporation | Structured wafer for device processing |
US20140264770A1 (en) * | 2013-03-15 | 2014-09-18 | Sandia Corporation | Method of forming through substrate vias (tsvs) and singulating and releasing die having the tsvs from a mechanical support substrate |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110556290A (zh) * | 2018-06-01 | 2019-12-10 | 辛纳普蒂克斯公司 | 堆叠晶片集成电路 |
CN110660687A (zh) * | 2018-06-28 | 2020-01-07 | 台湾积体电路制造股份有限公司 | 接合支撑结构、多个半导体晶圆及其接合方法 |
CN111092067A (zh) * | 2018-10-24 | 2020-05-01 | 三星电子株式会社 | 半导体封装件 |
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HK1232339A1 (zh) | 2018-01-05 |
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