FR3053159B1 - Procede de fabrication d'une structure de transistors comportant une etape de bouchage - Google Patents

Procede de fabrication d'une structure de transistors comportant une etape de bouchage Download PDF

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Publication number
FR3053159B1
FR3053159B1 FR1655842A FR1655842A FR3053159B1 FR 3053159 B1 FR3053159 B1 FR 3053159B1 FR 1655842 A FR1655842 A FR 1655842A FR 1655842 A FR1655842 A FR 1655842A FR 3053159 B1 FR3053159 B1 FR 3053159B1
Authority
FR
France
Prior art keywords
layer
semiconductor layer
transistor
transistors
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1655842A
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English (en)
Other versions
FR3053159A1 (fr
Inventor
Laurent Brunet
Nicolas Posseme
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Publication date
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Priority to FR1655842A priority Critical patent/FR3053159B1/fr
Priority to US15/625,852 priority patent/US10490451B2/en
Publication of FR3053159A1 publication Critical patent/FR3053159A1/fr
Application granted granted Critical
Publication of FR3053159B1 publication Critical patent/FR3053159B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8303—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

L'invention a pour objet un procédé de fabrication d'une structure de transistors réalisée de manière séquentielle, comprenant au moins les étapes suivantes : - la réalisation d'au moins un premier transistor à partir d'une première couche semiconductrice (102) pouvant être en silicium ; - l'encapsulation d'au moins ledit premier transistor par au moins une couche de premier diélectrique (107) définissant un premier ensemble ; - le collage d'une couche de second diélectrique (207) située à la surface d'une seconde couche semiconductrice (202) pouvant être en silicium, sur la couche de premier diélectrique (107) ; - le dépôt d'une couche de matériau planarisant (500) à la surface de ladite seconde couche semiconductrice; - la gravure sélective de ladite couche de matériau planarisant, jusqu'à ladite seconde couche semiconductrice ; - la réalisation d'au moins un second transistor à partir de ladite seconde couche semiconductrice.
FR1655842A 2016-06-23 2016-06-23 Procede de fabrication d'une structure de transistors comportant une etape de bouchage Active FR3053159B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1655842A FR3053159B1 (fr) 2016-06-23 2016-06-23 Procede de fabrication d'une structure de transistors comportant une etape de bouchage
US15/625,852 US10490451B2 (en) 2016-06-23 2017-06-16 Process for fabricating a transistor structure including a plugging step

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1655842 2016-06-23
FR1655842A FR3053159B1 (fr) 2016-06-23 2016-06-23 Procede de fabrication d'une structure de transistors comportant une etape de bouchage

Publications (2)

Publication Number Publication Date
FR3053159A1 FR3053159A1 (fr) 2017-12-29
FR3053159B1 true FR3053159B1 (fr) 2019-05-10

Family

ID=56557841

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1655842A Active FR3053159B1 (fr) 2016-06-23 2016-06-23 Procede de fabrication d'une structure de transistors comportant une etape de bouchage

Country Status (2)

Country Link
US (1) US10490451B2 (fr)
FR (1) FR3053159B1 (fr)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804259A (en) * 1996-11-07 1998-09-08 Applied Materials, Inc. Method and apparatus for depositing a multilayered low dielectric constant film
US6875687B1 (en) * 1999-10-18 2005-04-05 Applied Materials, Inc. Capping layer for extreme low dielectric constant films
JP4507503B2 (ja) * 2003-04-02 2010-07-21 セイコーエプソン株式会社 電気光学装置の製造方法及び半導体装置の製造方法
US8536629B2 (en) * 2009-02-24 2013-09-17 Nec Corporation Semiconductor device and method for manufacturing the same
CA2719927C (fr) * 2010-11-05 2014-04-29 Ibm Canada Limited - Ibm Canada Limitee Calcination au laser de polyimide pour la production de semiconducteurs
US8957458B2 (en) * 2011-03-24 2015-02-17 Zeno Semiconductor, Inc. Asymmetric semiconductor memory device having electrically floating body transistor
US9177890B2 (en) * 2013-03-07 2015-11-03 Qualcomm Incorporated Monolithic three dimensional integration of semiconductor integrated circuits
US9922956B2 (en) * 2014-09-26 2018-03-20 Qualcomm Incorporated Microelectromechanical system (MEMS) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3D IC) integration
US9337197B1 (en) * 2014-10-28 2016-05-10 Globalfoundries Inc. Semiconductor structure having FinFET ultra thin body and methods of fabrication thereof
US10199461B2 (en) * 2015-10-27 2019-02-05 Texas Instruments Incorporated Isolation of circuit elements using front side deep trench etch

Also Published As

Publication number Publication date
US20170372967A1 (en) 2017-12-28
US10490451B2 (en) 2019-11-26
FR3053159A1 (fr) 2017-12-29

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