CN106611790B - 垂直晶体管及其制备方法 - Google Patents

垂直晶体管及其制备方法 Download PDF

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CN106611790B
CN106611790B CN201510703700.1A CN201510703700A CN106611790B CN 106611790 B CN106611790 B CN 106611790B CN 201510703700 A CN201510703700 A CN 201510703700A CN 106611790 B CN106611790 B CN 106611790B
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dielectric layer
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CN106611790A (zh
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肖德元
张汝京
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Zing Semiconductor Corp
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Abstract

本发明提供一种垂直晶体管及其制备方法，包括：第一表面和与第一表面相对的第二表面；具有第一掺杂类型的漂移区域，所述漂移区域位于所述第一表面和所述第二表面之间；至少一个具有所述第一掺杂类型的源区，所述源区位于所述漂移区域和所述第一表面之间，相邻的所述源区之间设置有第一介质层；至少一个具有所述第一掺杂类型的漏区，所述漏区位于所述漂移区域和所述第二表面之间，相邻的所述漏区之间设置有栅极，所述栅极包括栅电极以及位于所述栅电极与所述漂移区域之间的栅介质层，所述栅电极与所述第二表面之间设置有第二介质层。本发明中，源区、漏区以及漂移区域均具有第一掺杂类型，使得该晶体管为无结型晶体管，从而减小晶体管的功耗。

Description

垂直晶体管及其制备方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种垂直晶体管及其制备方法。
背景技术
作为第三代半导体材料的典型代表宽禁带半导体，氮化镓(GaN)具有许多硅(Si)材料所不具备的优异性能，GaN是高频、高压、高温和大功率应用的优良半导体材料，在民用和军事领域具有广阔的应用前景。随着GaN技术的进步，特别是大直径硅基GaN外延技术的逐步成熟并商用化GaN功率半导体技术有望成为高性能低成功率技术解决方案，从而GaN的功率器件受到国际著名半导体厂商和研究单位的关注。
发明内容
本发明的目的在于，提供一种垂直晶体管及其制备方法，垂直晶体管为GaN的无结晶体管，减小晶体管的功耗。
为解决上述技术问题，本发明一种垂直晶体管，包括：
第一表面和与所述第一表面相对的第二表面；
具有第一掺杂类型的漂移区域，所述漂移区域位于所述第一表面和所述第二表面之间；
至少一个具有所述第一掺杂类型的源区，所述源区位于所述漂移区域和所述第一表面之间，相邻的所述源区之间设置有第一介质层；
至少一个具有所述第一掺杂类型的漏区，所述漏区位于所述漂移区域和所述第二表面之间，相邻的所述漏区之间设置有栅极，所述栅极包括栅电极以及位于所述栅电极与所述漂移区域之间的栅介质层，所述栅电极与所述第二表面之间设置有第二介质层。
可选的，还包括位于所述第一表面上的源电极以及位于所述第二表面上的漏电极。
可选的，所述第一掺杂类型为N型。
可选的，所述漂移区域为N型掺杂的GaN，厚度为2μm～50μm。
可选的，所述源区为N型重掺杂的GaN，所述漏区为N型重掺杂的GaN。
可选的，所述栅电极为Ti、TiN、Ta、TaN、W、Al、Cu、Ag、Ni、Au、Cr、多晶硅中的一种。
可选的，所述栅介质层为氧化硅，所述栅介质层的厚度为2nm～50nm。
可选的，所述第一介质层为氧化硅、氮氧化硅或氮化硅中的一种，所述第一介质层的厚度为20nm～100nm。
可选的，所述第二介质层为氧化硅、氮氧化硅或氮化硅中的一种，所述第二介质层的厚度为20nm～100nm。
相应的，本发明还提供一种垂直晶体管的制备方法，包括：
提供一图形化的半导体衬底；
在部分所述图形化的半导体衬底上形成第一介质层，在剩余的部分所述图形化的半导体衬底上形成源区，所述源区具有第一掺杂类型；
形成漂移层和漏区膜层，所述漂移层覆盖所述第一介质层和所述源区，所述漏区膜层覆盖所述漂移层，所述漂移层和漏区膜层具有所述第一掺杂类型；
刻蚀所述漏区膜层和所述漂移层形成沟槽，所述沟槽暴露所述漂移层，剩余的所述漂移层形成漂移区域，剩余的所述漏区膜层形成漏区；
形成栅介质层和栅电极，栅介质层覆盖所述沟槽的底壁和侧壁，所述栅电极覆盖所述栅介质层并填充部分所述沟槽；
形成第二介质层，所述第二介质层覆盖所述栅电极，并填充剩余的部分所述沟槽。
可选的，形成所述栅介质层和所示栅电极的步骤包括：
形成介质膜层和电极膜层，介质膜层覆盖所述沟槽的底壁和侧壁以及所述漏区，所述电极膜层覆盖所述介质膜层；
平坦化所述电极膜层，所述电极膜层与所述介质膜层平齐；
刻蚀所述介质膜层形成栅介质层，所述栅介质层暴露出所述漏区；
去除部分所述电极膜层形成所述栅电极。
可选的，还包括：
形成漏电极，所述漏电极覆盖所述第二介质层、所述栅介质层以及所述漏区；
去除所述图形化的半导体衬底；
形成源电极，所述源电极覆盖所述第一介质层以及所述源区。
可选的，所述图形化的半导体衬底的表面具有半球形或多边形的图形。
本发明提供的垂直晶体管，包括源区、漂移区域、漏区、栅极，其中，源区、漏区以及漂移区域均具有第一掺杂类型，使得该晶体管为无结型晶体管，从而减小晶体管的功耗。并且，在栅极上施加电压，控制漂移区域中的载流子通过栅极之间的耗尽区，从而控制晶体管的开关。
附图说明
图1为本发明一实施例中垂直晶体管的剖面结构示意图；
图2为本发明一实施例中制备垂直晶体管的方法流程图；
图3为本发明一实施例中图形化的半导体衬底的剖面结构示意图；
图4为本发明一实施例中第一介质层和源区的剖面结构示意图；
图5为本发明一实施例中形成漂移层和漏区膜层的结构示意图；
图6为本发明一实施例中沟槽的结构示意图；
图7为本发明一实施例中形成介质膜层和电极膜层的结构示意图；
图8为本发明一实施例中平坦化电极膜层的结构示意图；
图9为本发明一实施例中形成栅介质层的结构示意图；
图10为本发明一实施例中形成栅电极的结构示意图；
图11为本发明一实施例中形成第二介质层的结构示意图；‘
图12为本发明一实施例中形成漏电极的结构示意图；
图13为本发明一实施例中垂直晶体管关断的结构示意图；
图14为本发明一实施例中垂直晶体管导通的结构示意图。
具体实施方式
下面将结合示意图对本发明的垂直晶体管及其制备方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
本发明的核心思想在于，提供一种垂直晶体管，包括：第一表面和与所述第一表面相对的第二表面；具有第一掺杂类型的漂移区域，所述漂移区域位于所述第一表面和所述第二表面之间；至少一个具有所述第一掺杂类型的源区，所述源区位于所述漂移区域和所述第一表面之间，相邻的所述源区之间设置有第一介质层；至少一个具有所述第一掺杂类型的漏区，所述漏区位于所述漂移区域和所述第二表面之间，相邻的所述漏区之间设置有栅极，所述栅极包括栅电极以及位于所述栅电极与所述漂移区域之间的栅介质层，所述栅电极与所述第二表面之间设置有第二介质层。本发明中，源区、漏区以及漂移区域均具有第一掺杂类型，使得该晶体管为无结型晶体管，从而减小晶体管的功耗。
下文结合附图对本发明的垂直晶体管及其制备方法进行描述。
参考图1所示，图1为垂直晶体管200的剖面结构示意图，垂直晶体管200包括：
第一表面201和与所述第一表面202相对的第二表面202。
漂移区域230，所述漂移区域230位于所述第一表面201和所述第二表面202之间，漂移区域230具有第一掺杂类型，所述第一掺杂类型为N型。例如，所述漂移区域230为N型掺杂的GaN，漂移区域230的厚度为2μm～50μm。
至少一个源区220，所述源区220位于所述漂移区域230和所述第一表面201之间，源区220具有所述第一掺杂类型，则所述源区220为N型重掺杂的GaN，源区220的厚度为10nm～50nm。并且，相邻的所述源区220之间设置有第一介质层210，第一介质层210用于将源区220隔离开来，第一介质层210为氧化硅、氮氧化硅或氮化硅中的一种，第一介质层210的厚度为20nm～100nm。
至少一个漏区240，所述漏区240位于所述漂移区域230和所述第二表面202之间，漏区240具有所述第一掺杂类型，则所述漏区240为N型重掺杂的GaN，漏区240的厚度为10nm～50nm。相邻的所述漏区240之间设置有栅极300，所述栅极300包括栅电极260以及位于所述栅电极260与所述漂移区域230之间的栅介质层250，所述栅介质层250为氧化硅，所述栅介质层250的厚度为2nm～50nm，所述栅电极260为Ti、TiN、Ta、TaN、W、Al、Cu、Ag、Ni、Au、Cr、多晶硅中的一种。此外，所述栅电极260与所述第二表面202之间设置有第二介质层270，第二介质层270用于实现栅电极260与漏电极之间的电性绝缘，所述第二介质层270为氧化硅、氮氧化硅或氮化硅中的一种，第二介质层270的厚度为20nm～100nm。
此外，垂直晶体管还包括位于所述第一表面201上的源电极290以及位于所述第二表面202上的漏电极280。源电极290为Ti、Ni、Al、Au中的一种，源电极290的厚度为50nm～200nm，漏电极280为Ti、Ni、Al、Au中的一种，漏电极280的厚度为50nm～200nm。
相应的，本发明还提供一种垂直晶体管的制备方法，图2为垂直晶体管的制备流程图，图3～图12为各步骤中的结构示意图，其制备过程包括如下步骤：
执行步骤S1，参考图3所示，提供一图形化的半导体衬底100，所述图形化的半导体衬底100的表面具有半球形或多边形的图形。在本实施例中，在表面平坦的半导体衬底上形成图案阵列，例如，聚苯乙烯小球阵列，接着以图案阵列为掩膜刻蚀半导体衬底，形成图形化的半导体衬底。在本实施例中，半导体衬底100为硅衬底、锗衬底或锗硅衬底，优选为硅衬底。可以理解的是，由于Ⅳ材料与Ⅲ-Ⅴ化合物之间晶格不匹配，在图形化的半导体衬底100上形成Ⅲ-Ⅴ化合物会引入缺陷，然而，在半导体衬底表面形成图形，可以减少由于晶格失配引起的缺陷。
执行步骤S2，参考图4所示，在部分所述图形化的半导体衬底100上形成第一介质层210，在剩余的部分所述图形化的半导体衬底100上形成源区220，本实施例中，所述源区220具有第一掺杂类型，例如，源区220为N型重掺杂的GaN，源区220的厚度为10nm～50nm。第一介质层210为氧化硅、氮氧化硅或氮化硅中的一种，第一介质层210的厚度为20nm～100nm，第一介质层210用于将源区220隔离开来。
执行步骤S3，参考图5所示，形成漂移层231和漏区膜层241，所述漂移层231覆盖所述第一介质层210和所述源区220，所述漏区膜层241覆盖所述漂移层231。本实施例中，漂移层231具有第一掺杂类型，漂移层231为N型掺杂的GaN，漂移层231的厚度为2μm～50μm，同样的，漏区膜层241具有第一掺杂类型，漏区膜层241为N型重掺杂的GaN。
执行步骤S4，参考图6所示，刻蚀所述漏区膜层241和所述漂移层231形成沟槽310，所述沟槽310暴露所述漂移层241，剩余的所述漂移层231形成漂移区域230，剩余的所述漏区膜层241形成漏区240，本实施例中，形成的漏区240的厚度为10nm～50nm。
执行步骤S5，参考图7～10所示，形成栅介质层250和栅电极260，栅介质层250覆盖所述沟槽310的底壁和侧壁，所述栅电极260覆盖所述栅介质层250并填充部分所述沟槽310。本实施例中，形成栅介质层250和栅电极260的步骤具体包括：
参考图7所示，形成介质膜层251和电极膜层261，介质膜层251覆盖所述沟槽310的底壁和侧壁以及所述漏区240，所述电极膜层261覆盖所述介质膜层251；
参考图8所示，平坦化所述电极膜层261，使得所述电极膜层261与所述介质膜层251平齐；
参考图9所示，刻蚀所述介质膜层251，剩余的介质膜层251形成栅介质层250，并且，所述栅介质层250暴露出所述漏区240，本实施例中，所述栅介质层250为氧化硅，所述栅介质层250的厚度为2nm～50nm；
参考图10所示，刻蚀所述电极膜层261，去除部分所述电极膜层261，剩余的电极膜层261形成栅电极260，从而栅介质层250和栅电极260形成垂直晶体管的栅极300。本实施例中，所述栅电极260为Ti、TiN、Ta、TaN、W、Al、Cu、Ag、Ni、Au、Cr、多晶硅中的一种
执行步骤S6，参考图11所示，形成第二介质层270，所述第二介质层270覆盖所述栅电极260，第二介质层270用于将栅电极250与漏电极隔离。本实施例中，所述第二介质层270为氧化硅、氮氧化硅或氮化硅中的一种，第二介质层270的厚度为20nm～100nm。
参考图12所示，垂直晶体管的制备方法中还包括：形成漏电极280，所述漏电极280覆盖所述第二介质层270、所述栅介质层250以及所述漏区240，漏电极280为Ti、Ni、Al、Au中的一种，漏电极280的厚度为50nm～200nm；去除所述图形化的半导体衬底100；形成源电极290，所述源电极290覆盖所述第一介质层210以及所述源区220，源电极290为Ti、Ni、Al、Au中的一种，源电极290的厚度为50nm～200nm，从而形成图1中所示的垂直晶体管200。其中，第一介质层210和源区220共同形成垂直晶体管的第一表面201，第二介质层270、栅介质层260以及漏区240共同形成垂直晶体管的第二表面202，并且，由于第一表面201在图形化的半导体衬底100上制备而成的，第一表面201为平坦的结构。然而，本领域技术人员可以理解的是，在去除图形化的半导体衬底100之后，先进行化学机械抛光，形成平坦的第一表面，再在第一表面上形成源电极，将源区引出。
本发明中的垂直晶体管中源区220、漂移区域230以及漏区240均具有第一掺杂类型，为N型掺杂的GaN，该晶体管为无结型晶体管，从而可以减小晶体管的功耗。并且，由于栅电极260与漂移区域230之间形成金属-氧化物-半导体接触，由于GaN与金属之间的功函数差，使得栅介质层250之间形成耗尽区，当耗尽区贯穿栅介质层250之间的区域时，载流子将不能通过，然而通过在栅极上加上某一电压时，使得载流子刚好能通过栅介质层250之间的区域，该电压即为垂直晶体管的阈值电压Vt，从而本发明的垂直晶体管可以通过控制栅极上的电压值控制晶体管的开关。
参考图13所示，当栅电极260上不加电压或电压Vg小于垂直晶体管的阈值电压Vt时，在源电极290上加上电压后，源区220中形成载流子，载流子从源区220经过漂移区域230中到漏区240，载流子将在栅介质层250之间的区域(图13中的虚线区域)完全耗尽，使得垂直晶体管关断。参考图14所示，在栅电极260上加上电压Vg时，Vg大于垂直晶体管导通的阈值电压Vt，载流子的耗尽区(图14中虚线区域)减小，使得载流子得以通过栅介质层250之间的区域到达漏区240，从而垂直晶体管导通。
综上所述，本发明的垂直晶体管中，包括漂移区域、源区、漏区以及栅极，漂移区域、源区、漏区均具有第一掺杂类型，使得垂直晶体管为无结型晶体管，减小晶体管的功耗。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利。

Claims (10)

1.一种垂直晶体管，其特征在于，包括：
第一表面和与所述第一表面相对的第二表面；
具有第一掺杂类型的漂移区域，所述漂移区域位于所述第一表面和所述第二表面之间；
多个具有所述第一掺杂类型的源区，所述源区位于所述漂移区域和所述第一表面之间，相邻的所述源区之间设置有第一介质层；
多个具有所述第一掺杂类型的漏区，所述漏区位于所述漂移区域和所述第二表面之间，相邻的所述漏区之间设置有栅极，所述栅极包括栅电极以及位于所述栅电极与所述漂移区域之间的栅介质层，所述栅电极与所述第二表面之间设置有第二介质层，
其中，所述漂移区域、所述源区和所述漏区均为N型掺杂的GaN，所述第一表面为图形化的半导体衬底的表面，所述图形化的半导体衬底的表面具有半球形或多边形的图形；
所述垂直晶体管包括多个纵向并行排布的子垂直晶体管，每个所述子垂直晶体管包括所述漏区、所述漂移区域和所述源区；多个所述子垂直晶体管共用所述漂移区域。
2.如权利要求1所述的垂直晶体管，其特征在于，还包括位于所述第一表面上的源电极以及位于所述第二表面上的漏电极。
3.如权利要求1所述的垂直晶体管，其特征在于，所述漂移区域的厚度为2μm～50μm。
4.如权利要求1所述的垂直晶体管，其特征在于，所述栅电极为Ti、TiN、Ta、TaN、W、Al、Cu、Ag、Ni、Au、Cr、多晶硅中的一种。
5.如权利要求1所述的垂直晶体管，其特征在于，所述栅介质层为氧化硅，所述栅介质层的厚度为2μm～50μm。
6.如权利要求1所述的垂直晶体管，其特征在于，所述第一介质层为氧化硅、氮氧化硅或氮化硅中的一种，所述第一介质层的厚度为20nm～100nm。
7.如权利要求1所述的垂直晶体管，其特征在于，所述第二介质层为氧化硅、氮氧化硅或氮化硅中的一种，所述第二介质层的厚度为20nm～100nm。
8.一种垂直晶体管的制备方法，其特征在于，包括：
提供一图形化的半导体衬底；
在部分所述图形化的半导体衬底上形成第一介质层，在剩余的部分所述图形化的半导体衬底上形成源区，所述源区具有第一掺杂类型；
形成漂移层和漏区膜层，所述漂移层覆盖所述第一介质层和所述源区，所述漏区膜层覆盖所述漂移层，所述漂移层和漏区膜层具有所述第一掺杂类型；
刻蚀所述漏区膜层和所述漂移层形成沟槽，所述沟槽暴露所述漂移层，剩余的所述漂移层形成漂移区域，剩余的所述漏区膜层形成漏区；
形成栅介质层和栅电极，栅介质层覆盖所述沟槽的底壁和侧壁，所述栅电极覆盖所述栅介质层并填充部分所述沟槽；
形成第二介质层，所述第二介质层覆盖所述栅电极，并填充剩余的部分所述沟槽，
其中，所述漂移区域、所述源区和所述漏区均为N型掺杂的GaN，所述图形化的半导体衬底的表面具有半球形或多边形的图形；
所述垂直晶体管包括多个纵向并行排布的子垂直晶体管，每个所述子垂直晶体管包括所述漏区、所述漂移区域和所述源区；多个所述子垂直晶体管共用所述漂移区域。
9.如权利要求8所述的垂直晶体管的制备方法，其特征在于，形成所述栅介质层和所示栅电极的步骤包括：
形成介质膜层和电极膜层，介质膜层覆盖所述沟槽的底壁和侧壁以及所述漏区，所述电极膜层覆盖所述介质膜层；
平坦化所述电极膜层，所述电极膜层与所述介质膜层平齐；
刻蚀所述介质膜层形成栅介质层，所述栅介质层暴露出所述漏区；
去除部分所述电极膜层形成所述栅电极。
10.如权利要求8所述的垂直晶体管的制备方法，其特征在于，还包括：
形成漏电极，所述漏电极覆盖所述第二介质层、所述栅介质层以及所述漏区；
去除所述图形化的半导体衬底；
形成源电极，所述源电极覆盖所述第一介质层以及所述源区。
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