JP5964091B2 - 半導体装置およびその製造方法 - Google Patents
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Description
(実施の形態1)
まず半導体基板SUBの主表面における各素子形成領域の配置について図1を用いて説明する。
図7に示す工程においてイオン注入法により形成される局所n型埋め込み領域RBNは、その形成される条件を変化することにより、高耐圧pMOSFET(p型トランジスタPTR)における寄生バイポーラトランジスタの動作、およびそれに伴うp型領域PSRへの漏れ電流(基板漏れ電流)をより確実に抑制することができる。
図17を参照して、本実施の形態における高耐圧アナログI/O回路の形成領域は、図2に示す実施の形態1における高耐圧アナログI/O回路の形成領域と基本的に同様の構成を有する。しかし本実施の形態においては、局所n型埋め込み領域RBNはn型埋め込み層NIに対する主表面MSと反対側、すなわち図2における下側(図4における右側)に、n型埋め込み層NIと接するように配置される。したがって本実施の形態の局所n型埋め込み領域RBNは、半導体基板SUBのp型領域PSRに取り囲まれるように(埋め込まれるように)配置されている。
図18を参照して、本実施の形態における高耐圧アナログI/O回路の形成領域は、図2に示す実施の形態1における高耐圧アナログI/O回路の形成領域と基本的に同様の構成を有する。しかし本実施の形態においては、局所n型埋め込み領域RBNは、n型埋め込み層NIの内部に配置される。したがって本実施の形態の局所n型埋め込み領域RBNは、ドレイン電極Dのp型不純物領域PR(および高耐圧p型ドリフト層HPDF)の直下において、n型埋め込み層NIと同一の領域に配置される。
以上のように本実施の形態においては、局所n型埋め込み領域RBNがn型埋め込み層NIと同一の位置に形成される。しかし不純物濃度プロファイルで考えれば、局所n型埋め込み領域RBNが形成されることにより、たとえば当該局所n型埋め込み領域RBNが存在しない場合に比べて、ドレイン電極Dを取り出す領域の直下におけるn型不純物領域の厚みが増加したり、n型不純物の濃度が高くなったりする。このため本実施の形態の局所n型埋め込み領域RBNも他の実施の形態と同様の上記の効果を奏する。
Claims (11)
- 主表面を有し、かつ内部にp型領域を有する半導体基板に、高耐圧pチャネル型トランジスタを有する半導体装置であり、
前記高耐圧pチャネル型トランジスタは、
前記半導体基板内であって前記p型領域の前記主表面側に配置されたn型埋め込み層と、
前記p型領域上であって前記主表面に形成された、ドレイン電極を取り出すための第1のp型不純物領域と、
前記p型領域上であって前記主表面に形成された、ソース電極を取り出すための第2のp型不純物領域と、
前記第1のp型不純物領域の直下に配置され、前記n型埋め込み層と接するように配置された局所n型埋め込み領域とを備え、
前記高耐圧pチャネル型トランジスタは前記半導体基板に複数形成されており、
前記高耐圧pチャネル型トランジスタは、前記第2のp型不純物領域を取り囲むように前記主表面に形成されたn型ウェル領域を含み、
前記局所n型埋め込み領域は、前記主表面に沿う方向に関して前記第1のp型不純物領域を介して対向配置されている前記n型ウェル領域同士を接続する、半導体装置。 - 前記半導体基板には高耐圧nチャネル型トランジスタをさらに有し、
前記高耐圧nチャネル型トランジスタは、前記高耐圧pチャネル型トランジスタの前記n型埋め込み層と同一の層としてのn型半導体層を含んでいる、請求項1に記載の半導体装置。 - 前記局所n型埋め込み領域は、平面視において前記第1のp型不純物領域と重なり同じ平面形状を有している、請求項1に記載の半導体装置。
- 前記第1のp型不純物領域および前記局所n型埋め込み領域は、前記主表面に沿う方向に関して前記第1のp型不純物領域を介して対向配置されている前記n型ウェル領域内に部分的に入り込み接触するように前記n型ウェル領域同士を接続する、請求項1に記載の半導体装置。
- 前記局所n型埋め込み領域は、前記n型埋め込み層よりも前記主表面側に存在する、請求項1に記載の半導体装置。
- 主表面を有し、かつ内部にp型領域を有する半導体基板に、高耐圧pチャネル型トランジスタを有する半導体装置の製造方法であり、
前記高耐圧pチャネル型トランジスタを形成する工程は、
主表面を有し、かつ内部にp型領域を有する半導体基板を準備する工程と、
前記半導体基板内の前記p型領域の前記主表面側に、n型埋め込み層を形成する工程と、
前記p型領域上であって前記主表面に、ドレイン電極を取り出すための第1のp型不純物領域を形成する工程と、
前記p型領域上であって前記主表面に、ソース電極を取り出すための第2のp型不純物領域を形成する工程と、
前記第1のp型不純物領域の直下に、前記n型埋め込み層と接するように局所n型埋め込み領域を形成する工程とを備え、
前記第1のp型不純物領域を形成する工程と前記局所n型埋め込み領域を形成する工程とは同一のマスクを用いてなされ、
前記高耐圧pチャネル型トランジスタは前記半導体基板に複数形成され、
前記高耐圧pチャネル型トランジスタは、前記第2のp型不純物領域を取り囲むように前記主表面にn型ウェル領域を含むように形成され、
前記局所n型埋め込み領域は、前記主表面に沿う方向に関して前記第1のp型不純物領域を介して対向配置されている前記n型ウェル領域同士を接続するように形成される、半導体装置の製造方法。 - 前記半導体基板には、前記高耐圧pチャネル型トランジスタの前記n型埋め込み層と同一の層としてのn型半導体層を含む高耐圧nチャネル型トランジスタをさらに有し、
前記高耐圧nチャネル型トランジスタの前記n型半導体層を形成する工程は前記高耐圧pチャネル型トランジスタの前記n型埋め込み層を形成する工程と同時になされる、請求項6に記載の半導体装置の製造方法。 - 前記局所n型埋め込み領域はイオン注入法により形成される、請求項7に記載の半導体装置の製造方法。
- 前記第1のp型不純物領域はイオン注入法により形成される、請求項7に記載の半導体装置の製造方法。
- 前記n型埋め込み層はイオン注入法により形成される、請求項7に記載の半導体装置の製造方法。
- 前記第1のp型不純物領域および前記局所n型埋め込み領域は、前記主表面に沿う方向に関して前記第1のp型不純物領域を介して対向配置されている前記n型ウェル領域内に部分的に入り込み接触するように前記n型ウェル領域同士を接続するように形成される、請求項6に記載の半導体装置の製造方法。
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