CN102386240B - 圆柱形嵌入式电容器 - Google Patents

圆柱形嵌入式电容器 Download PDF

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CN102386240B
CN102386240B CN2010105917269A CN201010591726A CN102386240B CN 102386240 B CN102386240 B CN 102386240B CN 2010105917269 A CN2010105917269 A CN 2010105917269A CN 201010591726 A CN201010591726 A CN 201010591726A CN 102386240 B CN102386240 B CN 102386240B
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opening
substrate
conductive layer
capacitor
insulating barrier
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CN102386240A (zh
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苏安治
谢棋君
王姿予
吴伟诚
胡宪斌
侯上勇
邱文智
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种包括具有正面和正面对面的背面的基板的器件。电容器形成在基板中并且其包括第一电容板；环绕第一电容板的第一绝缘层；和环绕第一绝缘层的第二电容板。第一电容板，第一绝缘层，以及第二电容板的每一个都从基板的正面延伸到背面。

Description

圆柱形嵌入式电容器
技术领域
本发明涉及一种圆柱形嵌入式电容器。
背景技术
具有大电容值的大电容器需要大的晶片面积，因此导致了形成集成电路的困难。传统的电容器包括平面型电容器和沟渠型MOS电容器。平面型电容器的电容板与各自基板的主表面平行。形成平面型电容器的工艺是简单的。然而，平面型电容器也需要大面积。
另一方面，沟渠型MOS电容器包括与各自基板的主表面垂直的垂直部分，并且延伸到各自基板中，因此减少了需要的晶片面积。然而，形成沟渠型MOS电容器的工艺是复杂的。
发明内容
针对现有技术，本发明公开了一种器件，包括：
具有第一区域和第二区域的基板；以及
形成在所述基板的所述第一区域中的电容器，所述电容器包括：
第一电容板；
环绕所述第一电容板的第一绝缘层；以及
环绕所述第一绝缘层的第二电容板，其中所述第一电容板，所述第一绝缘层，以及所述第二电容板的每一个都从所述基板的正面延伸到所述基板的背面。
根据本发明所述的器件，进一步包括从所述基板的正面延伸到背面，并且环绕所述电容器的第一隔离层。
根据本发明所述的器件，其中所述电容器具有圆柱形状。
根据本发明所述的器件，其中所述第一电容板形成圆柱体，并且其中所述第一绝缘层和所述第二电容板的每一个都形成圆环。
根据本发明所述的器件进一步包括：
在所述基板的所述第二区域形成基板通孔(TSV)并且从所述基板的正面延伸到背面，其中所述TSV的第一直径比所述第二电容板的第二直径小；以及
位于所述TSV和所述基板之间的第二隔离层。
根据本发明所述的器件，其中所述基板是半导体基板，并且其中在所述半导体基板的正面或背面没有形成有源器件。
根据本发明所述的器件，进一步包括与所述第一和第二电容板之一电连接的金属凸块。
根据本发明所述的器件，进一步包括：
环绕所述第二电容板的第二绝缘层；以及
环绕所述第二绝缘层的第三电容板，其中所述第二绝缘层和所述第三电容板的每一个都从所述基板的正面延伸到背面。
根据本发明所述的器件，其中所述第一和第三电容板互相电连接。
根据本发明的一种器件，包括：
插入件，其中所述插入件中没有形成有源器件，并且其中所述插入件包括：
具有第一区域和第二区域的硅基板；
形成在所述硅基板的第一区域并且从所述硅基板的顶面延伸到背面的电容器；以及
从所述硅基板的顶面延伸到背面的第一隔离层，其中所述隔离层处于所述硅基板和所述电容器之间并且接触所述硅基板和所述电容器。
根据本发明所述的器件，其中所述电容器包括：
第一电容板；
环绕所述第一电容板的第一绝缘层；以及
环绕所述第一绝缘层的第二电容板，其中所述第一电容板，所述第一绝缘层，以及所述第二电容板的每一个都从所述硅基板的正面延伸到背面。
根据本发明所述的器件还包括：
覆在所述硅基板的正面上的互连结构；以及
覆在所述互连结构上并且通过所述互连结构电连接到所述电容器的金属凸块。
根据本发明所述的器件还包括：
覆在所述硅基板的顶面前端的第一金属凸块；
覆在所述硅基板的背面上的第二金属凸块；以及
在所述硅基板的第二区域内形成基板通孔(TSV)，并且从所述硅基板的顶面延伸到背面，其中所述TSV电连接所述第一金属凸块到所述第二金属凸块。
根据本发明的一种形成器件的方法，包括：
提供具有第一区域和第二区域的基板；
在所述基板的第一区域中形成第一开口，其中所述第一开口从正面延伸到所述基板中；
在所述基板的第二区域中形成第二开口，其中所述第二开口从正面延伸到所述基板中；
在所述基板上形成第一导电层以部分地填充所述第一开口的一部分以及完全填充所述第二开口；
在所述第一导电层上形成第一绝缘层；
在所述第一绝缘层上形成第二导电层；
实施平面化工艺以移除所述第一导电层的多余部分，所述第一和第二开口外的所述第一绝缘层和所述第二导电层；以及
研磨所述基板的背面以曝露所述第一导电层，所述第一绝缘层以及所述第二导电层，其中所述第一导电层，所述第一绝缘层以及所述第二导电层在所述第一开口中形成电容器，并且所述第一导电层在所述第二开口中形成基板通孔(TSV)。
根据本发明所述的方法，其中所述第一开口具有比所述第二开口的第二横向尺寸更大的第一横向尺寸。
根据本发明所述的方法，其中所述第一开口具有比所述第二开口的第二深度更深的第一深度。
根据本发明所述的方法，还包括，在所述研磨步骤之前：
在所述第二导电层上形成第二绝缘层；并且
在所述第二绝缘层上形成第三导电层。
根据本发明所述的方法，还包括，在形成所述第一导电层的步骤之前，在所述第一和第二开口中形成隔离层。
根据本发明所述的方法，还包括在所述基板的正面上形成金属凸块，其中所述金属凸块电连接至少所述电容器和所述TSV之一。
根据本发明所述的方法，还包括在所述基板的背面上形成金属凸块，其中所述金属凸块电连接至少所述电容器和所述TSV之一。
根据本发明的器件和方法，减少了需要的晶片面积。并且使得形成沟渠型MOS电容器的工艺简单化。
附图说明
为了更完全地理解实施例以及其优点，现结合附图参考以下描述，其中：
图1到9A是根据实施例生产基板中的嵌入式电容器的中间阶段的横截面视图；
图9B示出了如图9A所示嵌入式电容器的顶视图。
图10A到11示出了根据可选的实施例的电容器的横截面视图。
具体实施方式
以下详细讨论本发明实施例的制作和使用。然而，应该理解实施例提供了许多能以各种特定内容具体化的适用性发明理念。讨论的特定实施例仅仅是说明性的，并且不限定本发明的范围。
根据实施例提供了一种新颖的电容器以及形成其的方法。阐述了生产实施例的中间阶段。然后讨论了各种实施例。在所有各种视图和说明性实施例中，相同的参考标号用于指定相同的元件。
参照图1，提供了基板20，其为管芯22的一部分。在一个实施例中，基板20是半导体基板，其可为例如硅基板。基板20也可包含其他通常使用的材料，如碳，锗，镓，砷，氮，铟，磷和/或其类似物。基板20可由单晶或复合半导体材料形成。在一个实施例中，基板20是插入件的插入件基板，并且在基板20的表面上基本上没有形成有源器件如晶体管。然而，管芯22中可以或不可以形成无源器件如电容器，电感器，电阻器以及其类似物。在可选的实施例中，基板20是器件管芯的一部分，因此可在基板20的表面上形成集成电路如晶体管(图1中未示出，请参照图9)。基板20也可为由有机材料，陶瓷材料或其类似物形成的介电基板。
基板20包括在不同区域100和200中的部分。区域100为基板通孔(TSV)区域，其中形成了TSV。区域200是电容器区域，其中形成了电容器。在示例性实施例中，同时将TSV与电容器分别形成在区域100和200中。然而，TSV和电容器由各自的工艺步骤形成。
开口124和224在基板20中形成，并且从基板20的正面20a延伸到基板20中。开口124和224的形成可包括形成和构成光刻胶(未示出)，然后使用光刻胶来刻蚀基板20。然后移去光刻胶。在一个实施例中，开口124和224分别具有横向尺寸W1和W2，其可为长度/宽度或直径。横向尺寸W2可大于约110％，150％，或200％的横向尺寸W1。当开口124和224同时在相同的刻蚀步骤中形成，由于横向尺寸W1和W2的不同，深度D1和D2也将不同，深度D2大于深度D1。
参照图2，将隔离层26(也可称为内衬)形成以覆盖开口124和224的底部和侧壁。在其中基板20为介电基板的实施例中，可省略隔离层26。隔离层26可由硅氧化物，硅氮氧化物，硅氮化物或其类似物形成。
参照图3，形成了导电层30。导电层30的材料可包括金属材料如铜或铜合金，然而也可使用其它金属材料。导电层30的材料可包括非金属材料如多晶硅。导电层30的形成可包括使用如物理气相沉积(PVD)形成种子层，然后实施电镀以增加导电层30的厚度。工艺是可控的，并且宽度W1和W2以及深度D1和D2也是可选的，因此开口124被导电层30完全填满，而开口224被部分填充。导电层30作为形层形成在开口224的侧壁和底部。
然后形成绝缘层32，并且部分填充开口224，如图4所示。在一个实施例中，使用沉积技术形成绝缘层32用于形成形介电层，如选择性区域化学气相沉积(SACVD)，高纵横比工艺(HARP)或其类似的。绝缘层32可包括硅氮化物，硅氧化物，硅氮氧化物或其类似物。
参照图5，开口224的剩余部分用导电材料34填充。导电材料层34可包括金属材料如铜，钨，铝，其合金，以及其多层。导电材料层34的材料可包括非金属材料如多晶硅。接着，如图6所示，实施平面化步骤，因此去除了导电材料层34，绝缘层32以及基板20的顶面20a正上方的导电层30的多余部分。使用化学机械抛光(CMP)来实施平面化步骤。
在图7中，形成前端互连结构36。前端互连结构36可包括一个或多个介电层38，以及介电层38中的金属线(再分配线)40和通孔42。在其中晶圆22为器件晶圆的实施例中，介电层38可包括层间电介质(ILD)和多个金属间电介质(IMD)，其可由例如具有小于3.0的K值的低-K介电材料形成。然后在晶圆22上形成凸块44。凸块44可为铜柱凸块，焊料凸块，或任何其它类型的通常使用的凸块。
参照图8，在随后的工艺步骤中，研磨基板20的背面直到曝露出导电层30，绝缘层32以及导电层34。接着，如图9A所示，形成背面互连结构48。背面互连结构48也可包括一个或多个介电层，以及再分配线和介电层中的通孔(未示出)。金属凸块50(其可为焊料凸块或铜柱凸块)在基板20的背面形成。
在图9A所示的结构中，TSV区域100中的导电层30的剩余部分形成TSV60，其可电连接到金属凸块50和多个金属凸块44之一。区域200中的导电层30，绝缘层32以及导电层34的剩余部分形成电容器62，其包括作为两个电容板的导电层30和导电层34，以及作为电容器绝缘的绝缘层32。可以观察到电容板30和34以及电容器绝缘32的每一个都从基板20的正面20a延伸到背面20b。如图9A中所示的示例性实施例，将电容板30电连接到前端金属凸块44A，而将电容板34电连接到前端金属凸块44B。
在其中晶圆22为器件晶圆的情况下，有源器件24可在基板20的表面20a上形成。在一些实施例中，TSV60和电容器62可延伸到基板20的正面20a之外。例如，TSV60和电容器62可延伸到有源器件24之上的ILD(未示出)中。
图9B示出了图9A中所示结构的一部分的顶视图，其中顶视图从图9A中的平面交叉线9B-9B得到。可以观察到电容板30为环状，绝缘层32为环状，以及电容板34为被环形板30和层32包围的圆柱状。而且电容器62为圆柱状。虽然图9B示出电容板30和绝缘层32为圆环，它们也可形成具有不同形状的环，例如，矩形顶视图形状，取决于图1中开口224的顶视图形状。
图10A示出了根据可选的实施例的嵌入式电容器62，其中将电容器62电连接到背面金属凸块50。在图10B中，示出了另一个实施例，其中没有将前端金属凸块和后端金属凸块电连接到电容器62上。在这个实施例中，管芯22可为器件管芯，并且可将电容器62电连接到管芯22中形成的集成电路(未示出)上。
图11示出了可选的实施例，其中圆柱形电容器62包括两个电容器绝缘层和三个电容板。电容器绝缘32和电容板30以及70形成第一电容器62A，而电容器绝缘72和电容板70以及34形成第二电容器62B，第一和第二电容器通过包括金属线40和通孔42的金属连接而平行连接。因此，电容器62的电容等于第一和第二电容器的电容的总和。形成工艺与图1到9A所示的形成工艺相似，除了将导电层70和绝缘层72在图4所示步骤和图5所示步骤之间形成。
由于嵌入式电容器62从基板20的正面20a延伸到背面20b，因此由于基板20的大深度，导致电容器62的电容很高。当插入件中形成的不包括有源器件时，电容器62可利用未使用的插入件面积而且不再占用晶片面积。
根据实施例，器件包括具有正面以及正面对面的背面的基板。将电容器形成在基板中并且包括第一电容板；第一绝缘层环绕第一电容板；第二电容板环绕第一绝缘层。第一电容板，第一绝缘层，以及第二电容板的每一个都从基板的正面延伸到背面。
根据其它实施例，器件包括插入件，其中插入件中未形成有源器件。插入件包括具有正面以及正面对面的背面的硅基板；从顶面延伸到背面的电容器；以及从顶面延伸到背面的隔离层，其中隔离层位于并且接触硅基板和电容器之间。
根据又一其它实施例，器件包括具有正面以及正面对面的背面的硅基板，以及电容器。电容器包括具有圆柱形状的第一电容板；第一绝缘层环绕第一电容板；第二电容板环绕第一绝缘层；第二绝缘层环绕第二电容板；并且第三电容板环绕第二绝缘层。第一，第二，和第三电容板以及第一和第二绝缘层从硅基板的正面延伸到背面。将隔离层置于并接触第三电容板和硅基板之间，其中隔离层从硅基板的正面延伸到背面。
根据又一其它实施例，方法包括提供具有第一表面和第一表面对面的第二表面的基板；刻蚀基板以形成从第一表面延伸到基板中的第一开口；在第一开口的侧壁上形成第一导电层；在第一开口中和第一导电层上形成第一绝缘层；在第一开口中和第一绝缘层上形成第二导电层；然后研磨基板的第二表面直到曝露出第一和第二导电层以及第一绝缘层，其中第一和第二导电层以及第一绝缘层形成电容器。
根据又一其它实施例，方法包括提供具有正面和正面对面的背面的基板；刻蚀基板以同时形成从正面延伸到基板中的第一开口和第二开口；形成第一导电层以部分填充第一开口的一部分，其中用第一导电层将第二开口完全填满；在第一开口中和第一导电层上形成第一绝缘层；在第一开口中和第一绝缘层上形成第二导电层；实施平面化以移除第一和第二导电层的多余部分以及第一和第二开口外的第一绝缘层；然后研磨基板的背面直到曝露出第一和第二导电层以及第一绝缘层。第一和第二导电层以及第一绝缘层在第一开口中形成电容器，并且第一导电层在第二开口中形成穿过基板通孔(TSV)。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (7)

1.一种形成半导体器件的方法，包括：
提供具有第一区域和第二区域的基板；
在所述基板的第一区域中形成第一开口，其中所述第一开口从正面延伸到所述基板中；
在所述基板的第二区域中形成第二开口，其中所述第二开口从正面延伸到所述基板中；
在所述基板上形成第一导电层以部分地填充所述第一开口的一部分以及完全填充所述第二开口；
在所述第一导电层上形成第一绝缘层；
在所述第一绝缘层上形成第二导电层；
执行平面化工艺以移除所述第一开口和所述第二开口外的所述第一导电层的多余部分、所述第一开口和所述第二开口外的所述第一绝缘层和所述第二导电层；以及
研磨所述基板的背面以曝露所述第一导电层，所述第一绝缘层以及所述第二导电层，其中所述第一导电层，所述第一绝缘层以及所述第二导电层在所述第一开口中形成电容器，并且所述第一导电层在所述第二开口中形成基板通孔TSV。
2.根据权利要求1所述的方法，其中所述第一开口具有比所述第二开口的第二横向尺寸更大的第一横向尺寸。
3.根据权利要求1所述的方法，其中所述第一开口具有比所述第二开口的第二深度更深的第一深度。
4.根据权利要求1所述的方法，还包括，在所述研磨步骤之前：在所述第二导电层上形成第二绝缘层；并且
在所述第二绝缘层上形成第三导电层；
其中，所形成的第二绝缘层和第三导电层包括位于所述第一开口内的部分。
5.根据权利要求1所述的方法，还包括，在形成所述第一导电层的步骤之前，在所述第一开口和所述第二开口中形成隔离层。
6.根据权利要求1所述的方法，还包括在所述基板的正面上形成金属凸块，其中所述金属凸块电连接至少所述电容器和所述TSV之一。
7.根据权利要求1所述的方法，还包括在所述基板的背面上形成金属凸块，其中所述金属凸块电连接至少所述电容器和所述TSV之一。
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