CN109524347A - 半导体装置结构及其形成方法 - Google Patents
半导体装置结构及其形成方法 Download PDFInfo
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- CN109524347A CN109524347A CN201711275840.9A CN201711275840A CN109524347A CN 109524347 A CN109524347 A CN 109524347A CN 201711275840 A CN201711275840 A CN 201711275840A CN 109524347 A CN109524347 A CN 109524347A
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Abstract
提供一种半导体装置结构的形成方法,包括:形成一第一孔洞和一第二孔洞于一基板的一第一表面中;形成一第一绝缘层于第一孔洞和第二孔洞中;形成一导电层于第一绝缘层之上及第一孔洞和第二孔洞中,其中导电层具有一第一凹部于第一孔洞中并填充第二孔洞;形成一第二绝缘层于导电层之上及第一凹部中,其中第二绝缘层具有一第二凹部于第一凹部中;形成一导电结构于第二凹部中;从基板的一第二表面部分地移除基板、第一绝缘层、导电层、和第二绝缘层,以暴露出导电结构及第一孔洞和第二孔洞中的导电层,其中第二表面相对于第一表面。亦提供一种半导体装置结构。
Description
技术领域
本公开关于半导体装置结构及其形成方法,且特别是有关于一种于基板中形成有导电遮蔽结构的半导体装置结构及其形成方法。
背景技术
半导体集成电路(IC)工业已历经快速发展的阶段。集成电路材料及设计在技术上的进步使得每一代生产的集成电路变得比先前生产的集成电路更小且其电路也变得更复杂。然而,这些进展也增加了集成电路加工和制造上的复杂度。
在集成电路发展的进程中,功能性密度(亦即,每一个芯片区域中内连线装置的数目)已经普遍增加,而几何尺寸(亦即,制程中所能创造出最小的元件或线路)则是下降。这种微缩化的过程通常可通过增加生产效率及降低相关支出提供许多利益。
然而,由于特征尺寸(亦即,芯片封装结构的尺寸)持续下降,制程持续变得更加难以实现。因此,形成具有越来越小尺寸的可靠的半导体装置为一项挑战。
发明内容
根据一实施例,本公开提供一种半导体装置结构的形成方法,包括:形成一第一孔洞和一第二孔洞于一基板的一第一表面中;形成一第一绝缘层于第一孔洞和第二孔洞中;形成一导电层于第一绝缘层之上及第一孔洞和第二孔洞中,其中导电层具有一第一凹部于第一孔洞中并填充第二孔洞;形成一第二绝缘层于导电层之上及第一凹部中,其中第二绝缘层具有一第二凹部于第一凹部中;形成一导电结构于第二凹部中;从基板的一第二表面部分地移除基板、第一绝缘层、导电层、和第二绝缘层,以暴露出导电结构及第一孔洞和第二孔洞中的导电层,其中第二表面相对于第一表面。
根据另一实施例,本公开提供一种半导体装置结构的形成方法,包括:形成一第一孔洞和一第二孔洞于一基板的一第一表面中;共形地形成一第一绝缘层于第一孔洞和第二孔洞中;形成一导电层于第一绝缘层之上,其中导电层共形地覆盖第一孔洞中的第一绝缘层并具有一第一凹部于第一孔洞中,且导电层填充第二孔洞;形成一第二绝缘层于导电层之上,其中第二绝缘层具有一第二凹部于第一凹部中;形成一导电结构于第二凹部中以填充第二凹部;以及从基板的一第二表面部分地移除基板、第一孔洞和第二孔洞中的第一绝缘层、第一孔洞和第二孔洞中的导电层、和第二绝缘层,以暴露出导电结构和第一孔洞和第二孔洞中的导电层,其中第二表面相对于第一表面,且第一孔洞中的导电层形成一导电遮蔽结构。
又根据另一实施例,本公开提供一种半导体装置结构,包括:一基板;一第一导电结构,穿过基板;一第一绝缘层,穿过基板并围绕第一导电结构;一导电遮蔽结构,穿过基板并围绕第一绝缘层;一第二绝缘层,穿过基板并围绕导电遮蔽结构;一第二导电结构,穿过基板,其中第二导电结构和导电遮蔽结构是由相同的导电材料所构成;以及一第三绝缘层,穿过基板并围绕第二导电结构,其中第三绝缘层和第二绝缘层是由相同的绝缘材料所构成。
为让本公开的上述和其他目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合所附附图,作详细说明如下:
附图说明
本公开最好配合附图及详细说明阅读以便了解。要强调的是,依照工业上的标准实施,各个特征并未按照比例绘制。事实上,为了清楚的讨论,可能任意的放大或缩小各个特征的尺寸。
图1A~1O为根据一些实施例显示半导体装置结构形成制程于各阶段的剖面图。
图1M-1为根据一些实施例显示图1M的半导体装置结构的一部分的俯视图。
图1N-1为根据一些实施例显示图1N的半导体装置结构的一区域的俯视图。
图2为根据一些实施例显示一半导体装置结构的剖面图。
图3A为根据一些实施例显示一半导体装置结构形成制程于各阶段的剖面图。
图3B为根据一些实施例显示图3A的半导体装置结构的基板的底视图。
【符号说明】
110~基板
111~高频区域
112、114、124、132b、148、154~表面
116~第一孔洞
116a、118a~内壁
116b、118b~底表面
116T~第一穿孔
118~第二孔洞
118T~第二穿孔
119、126、149、212、254、277~侧壁
120、140~绝缘层
122、132a、134a、144、152、162、252~顶表面
130、150a、160~导电层
131、142~凹部
132~导电遮蔽结构
134、150~导电结构
146、182a~开口
170、271~介电结构
172、174、176、178~介电层
182~掩模层
192、196、276~导电通道结构
194、274a、274b~导线
198、275~导电衬垫
200、300、400~半导体装置结构
210、270~内连线结构
220、310、320~芯片
230、282、286~导电凸块
240~底部填充层
250~成型层
260~载体基板
272、273、274~配线层
284~接地凸块
290~导电遮蔽层
A~区域
G~间隙
I-I’~剖面线
T1、T2、T3~厚度
W1、W2、W3、W4~宽度
S1、S2、S3、S4、S5、S6~距离
具体实施方式
以下揭示提供许多不同的实施方法或是例子来实行本公开的不同特征。以下描述具体的元件及其排列的例子以简化本公开。当然这些仅是例子且不该以此限定本公开的范围。例如,在描述中提及第一个元件形成于第二个元件之上时,其可能包括第一个元件与第二个元件直接接触的实施例,也可能包括两者之间有其他元件形成而没有直接接触的实施例。此外,在不同实施例中可能使用重复的标号及/或符号,这些重复仅为了简单清楚地叙述本公开,不代表所讨论的不同实施例及/或结构之间有特定的关系。
此外,其中可能用到与空间相关的用词,像是“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词,这些关系词为了便于描述附图中一个(些)元件或特征与另一个(些)元件或特征之间的关系。这些空间关系词包括使用中或操作中的装置的不同方位,以及附图中所描述的方位。装置可能被转向不同方位(旋转90度或其他方位),则其中使用的空间相关形容词也可相同地照着解释。应了解的是,可在所述方法之前、期间、及之后提供额外的操作,且一些所述的操作在所述方法的其他实施例中可被置换或移除。
图1A~1O为根据一些实施例显示半导体装置结构形成制程于各阶段的剖面图。半导体装置结构可为具有穿基板导通结构(through substrate vias)或芯片封装结构的半导体基板。
如图1A所示,根据一些实施例,提供一基板110。根据一些实施例,基板110具有相对的表面112和114。基板110是由元素半导体材料所构成,包括单晶、多晶、或非晶结构的硅或锗。
在一些其他实施例中,基板110是由化合物半导体(例如:碳化硅、砷化镓、磷化镓、磷化铟、或砷化铟)、合金半导体(例如:SiGe或GaAsP)、或前述的组合所构成。基板110也可包括多层半导体、绝缘体上半导体(SOI)(像是绝缘体上硅或绝缘体上锗)、或前述的组合。
如图1B所示,根据一些实施例,将部分的基板110从表面112移除以形成第一孔洞116和第二孔洞118于表面112中。在一些实施例中,每一个第一孔洞116的宽度W1大于每一个第二孔洞118的宽度W2。
在一些实施例中,宽度W1为每一个第一孔洞116的最大宽度,且宽度W2为每一个第二孔洞118的最大宽度。在一些实施例中,每一个第一孔洞116的平均宽度大于每一个第二孔洞118的平均宽度。在一些实施例中,移除制程包括蚀刻制程,像是干蚀刻制程。
如图1B所示,根据一些实施例,形成绝缘层120于基板110之上及第一孔洞116和第二孔洞118中。根据一些实施例,绝缘层120共形地覆盖表面112、第一孔洞116的内壁116a和底表面116b、及第二孔洞118的内壁118a和底表面118b。根据一些实施例,绝缘层120也称为衬层。
根据一些实施例,绝缘层120的厚度T1范围介于约0.1μm至约0.2μm。根据一些实施例,绝缘层120包括氧化物(像是硅氧化物)。根据一些实施例,绝缘层120是利用热氧化制程或化学气相沉积制程所形成。
如图1C所示,根据一些实施例,形成导电层130于绝缘层120之上及第一孔洞116和第二孔洞118中。根据一些实施例,导电层130共形地覆盖第一孔洞116中的绝缘层120及表面112之上的绝缘层120。
因此,根据一些实施例,导电层130分别于第一孔洞中具有凹部131。根据一些实施例,导电层130填充第二孔洞118。因此,根据一些实施例,导电层130于第二孔洞118中不具有凹部。
根据一些实施例,导电层130是由金属材料或合金材料所构成。金属材料包括铜、金、铝、钨、或其他合适的金属材料。根据一些实施例,导电层130的形成包括:形成一种子层(未显示)于绝缘层120之上;及镀覆一导电材料层(未显示)于种子层之上。根据一些实施例,导电材料层的镀覆包括一电镀制程。
如图1D所示,根据一些实施例,移除表面112之上的导电层130。根据一些实施例,残留在每一个第一孔洞116中的导电层130形成一导电遮蔽结构132。根据一些实施例,残留在每一个第二孔洞118中的导电层130形成一导电结构134。
根据一些实施例,在移除表面112之上的导电层130之后,导电遮蔽结构132和导电结构134与彼此电性绝缘。根据一些实施例,导电遮蔽结构132和导电结构134通过位于之间的绝缘层120与基板110电性绝缘。
根据一些实施例,移除制程包括于导电层130之上实施一平坦化制程直到暴露出表面112之上的绝缘层120。根据一些实施例,平坦化制程包括一化学机械研磨(CMP)制程。在一些实施例中,在移除制程之后,导电遮蔽结构132、绝缘层120、和导电结构134的顶表面132a、122、和134a共平面。
如图1E所示,根据一些实施例,形成绝缘层140于导电遮蔽结构132、导电结构134、和表面112之上。根据一些实施例,绝缘层140共形地覆盖导电遮蔽结构132、导电结构134、和表面112。因此,根据一些实施例,绝缘层140分别在凹部131中具有凹部142。
根据一些实施例,导电遮蔽结构132(或导电层130)具有一厚度T2。根据一些实施例,绝缘层140具有一厚度T3。根据一些实施例,厚度T3大于厚度T2。根据一些实施例,厚度T2大于绝缘层120的厚度T1。
在一些实施例中,绝缘层140的平均厚度大于导电遮蔽结构132(或导电层130)的平均厚度。在一些实施例中,导电遮蔽结构132(或导电层130)的平均厚度大于绝缘层120的平均厚度。
绝缘层140是由高介电(high-k)材料,像是氧化铪、氧化锆、氧化铝、二氧化铪-铝合金、氧化硅铪、氧氮化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、其他合适的高介电材料、或前述的组合。
绝缘层140是由氧化物材料所构成,像是氧化硅。绝缘层140是由聚合物材料所构成,像是聚酰亚胺、聚苯并恶唑(polybenzoxazole;PBO)、苯并环丁烯(benzocyclobutene;BCB)、或其类似材料。根据一些实施例,利用一沉积制程像是化学气相沉积制程形成绝缘层140。
如图1F所示,根据一些实施例,形成导电层150a于绝缘层140之上。根据一些实施例,凹部142被导电层150a填充。根据一些实施例,导电层150a是由铜、金、铝、钨、或其他合适的导电材料所构成。
根据一些实施例,导电层150a的形成包括形成一种子层(未显示)于绝缘层140之上;及镀覆一导电材料层(未显示)于种子层之上。在一些其他实施例中,利用一物理气相沉积制程形成导电层150a。
如图1G所示,根据一些实施例,移除凹部142外的导电层150a。根据一些实施例,残留在每一个凹部142中的导电层150a形成一导电结构150。
根据一些实施例,利用一平坦化制程像是化学机械研磨制程移除凹部142外的导电层150a。因此,根据一些实施例,导电结构150的顶表面152和绝缘层140的顶表面144共平面。
如图1H所示,根据一些实施例,移除部分的绝缘层140以于绝缘层140中形成开口146。根据一些实施例,开口146暴露出导电结构134的顶表面134a。根据一些实施例,利用一微影制程和一蚀刻制程移除部分的绝缘层140。
如图1H所示,根据一些实施例,形成导电层160于开口146中。根据一些实施例,导电层160与其下方的导电结构134电性连接。根据一些实施例,导电层160与其下方的导电结构134直接接触。
根据一些实施例,导电层160的形成包括形成一种子层(未显示)于导电结构134和绝缘层140之上;镀覆一导电材料层(未显示)于种子层之上;及于导电材料层之上实施一平坦化制程直到暴露出绝缘层140的顶表面144。
根据一些实施例,平坦化制程包括一化学机械研磨(CMP)制程。因此,根据一些实施例,导电层160、绝缘层140、及导电结构150的顶表面162、144、及152共平面。
如图1I所示,根据一些实施例,形成介电层172于绝缘层140和导电层160之上。根据一些实施例,介电层172是由聚合物材料(例如:聚酰亚胺、PBO、或其类似材料)所构成。在一些实施例中,介电层172是由氧化物所构成,像是二氧化硅或高密度等离子体氧化物。在一些实施例中,介电层172是由硼磷硅玻璃(borophosphosilicate glass;BPSG)、旋涂式玻璃(spin on glass;SOG)、未掺杂硅酸盐玻璃(undoped silicate glass;USG)、氟化硅酸盐玻璃(fluorinated silicate glass;FSG)、等离子体增强TEOS(plasma-enhanced TEOS;PETEOS)、其类似材料、或前述的组合所构成。
根据一些实施例,介电层172和绝缘层140是由不同的材料所构成。在一些其他的实施例中,介电层172和绝缘层140是由相同的材料所构成。根据一些实施例,利用一涂布制程形成介电层172。
如图1I所示,根据一些实施例,形成掩模层182于介电层172之上。根据一些实施例,掩模层182具有开口182a,其暴露出部分的介电层172。根据一些实施例,掩模层182是由光阻材料所构成。
如图1J所示,根据一些实施例,透过开口182a移除部分的介电层172以形成开口172a于介电层172中。如图1J所示,根据一些实施例,形成导电通道结构(conductive viastructures)192于开口172a中。
根据一些实施例,一些导电通道结构192与其下方的导电结构150直接接触。根据一些实施例,一些导电通道结构192与其下方的导电结构134直接接触。导电通道结构192是由铜、铝、或其他合适的导电材料所构成。
根据一些实施例,导电通道结构192的形成包括形成一导电材料层(未显示)于介电层172之上以填充开口172a;及于导电材料层之上实施一平坦化制程直到暴露出介电层172。亦即,根据一些实施例,导电通道结构192是利用一单镶嵌制程所形成。
如图1J所示,根据一些实施例,形成介电层174于介电层172之上。根据一些实施例,介电层174是由聚合物材料(例如:聚酰亚胺、PBO、或其类似物)所构成。在一些实施例中,介电层174是由氧化物所构成,像是二氧化硅或高密度等离子体氧化物。在一些实施例中,介电层174是由硼磷硅玻璃(BPSG)、旋涂式玻璃(SOG)、未掺杂硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、等离子体增强TEOS(PETEOS)、其类似材料、或前述的组合所构成。
如图1J所示,根据一些实施例,形成导线194于介电层174中。根据一些实施例,导线194与导电通道结构192电性连接。根据一些实施例,导线194与其下方的导电通道结构192直接接触。根据一些实施例,导线194是由铜、铝、或其他合适的导电材料所构成。根据一些实施例,导线194是利用一单镶嵌制程所形成。
如图1J所示,根据一些实施例,形成介电层176于介电层174和导线194之上。根据一些实施例,介电层176是由聚合物材料(例如:聚酰亚胺、PBO、或其类似物)所构成。在一些实施例中,介电层176是由氧化物所构成,像是二氧化硅或高密度等离子体氧化物。在一些实施例中,介电层176是由硼磷硅玻璃(BPSG)、旋涂式玻璃(SOG)、未掺杂硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、等离子体增强TEOS(PETEOS)、其类似材料、或前述的组合所构成。
如图1J所示,根据一些实施例,形成导电通道结构196于介电层176中。根据一些实施例,导电通道结构196与导线194电性连接。根据一些实施例,导电通道结构196与其下方的导线194直接接触。根据一些实施例,导电通道结构196是由铜、铝、或其他合适的导电材料所构成。根据一些实施例,导电通道结构196是利用一单镶嵌制程所形成。
如图1J所示,根据一些实施例,形成介电层178于介电层176之上。根据一些实施例,介电层178是由聚合物材料(例如:聚酰亚胺、PBO、或其类似物)所构成。在一些实施例中,介电层178是由氧化物所构成,像是二氧化硅或高密度等离子体氧化物。在一些实施例中,介电层178是由硼磷硅玻璃(BPSG)、旋涂式玻璃(SOG)、未掺杂硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、等离子体增强TEOS(PETEOS)、其类似材料、或前述的组合所构成。
如图1J所示,根据一些实施例,形成导电衬垫198于介电层178中。根据一些实施例,导电衬垫198与导电通道结构196电性连接。根据一些实施例,导电衬垫198与其下方的导电通道结构196直接接触。根据一些实施例,导电衬垫198是由铜、铝、或其他合适的导电材料所构成。根据一些实施例,导电衬垫198是利用一单镶嵌制程所形成。
根据一些实施例,介电层172、174、176、和178一起形成介电结构170。导电通道结构192和196、导线194、导电衬垫198、和介电结构170一起形成内连线结构210。
在一些其他实施例中,导电通道结构192和196、导线194、和导电衬垫198是利用一双镶嵌制程所形成。又在一些其他实施例中,介电层172是由光阻材料所构成,且根据一些实施例,介电层172和导电通道结构192的形成包括形成一光阻材料层(未显示)于绝缘层140和导电层160之上;实施一微影制程以形成开口172a;形成一导电材料层(未显示)于介电层172之上以填充开口172a;及于导电材料层之上实施一平坦化制程直到暴露出介电层172。
根据一些实施例,可利用与前述用来形成介电层172和导电通道结构192相似的制程来形成介电层174、176、和178、导线194、导电通道结构196、及导电衬垫198。
如图1K所示,根据一些实施例,透过芯片220和导垫衬垫198之间的导电凸块230将芯片220接合至内连线结构210。根据一些实施例,芯片220透过导电凸块230和内连线结构210与导电结构150和134电性连接。
芯片220为一高频芯片,像是射频(RF)芯片、图像处理单元(graphic processorunit;GPU)芯片、或其他合适的高频芯片。根据一些实施例,芯片220产生具有频率范围介于约1GHz至约60HGz的信号。
如图1K所示,根据一些实施例,形成底部填充层240于芯片220和内连线结构210之间的间隙G中。根据一些实施例,底部填充层240是由一绝缘材料像是聚合物材料所构成。
如图1K所示,根据一些实施例,形成一成型层(molding layer)250于内连线结构210之上。根据一些实施例,成型层250覆盖芯片220并围绕芯片220、底部填充层240、和导电凸块230。
根据一些实施例,成型层250是由一绝缘材料像是聚合物材料所构成。在一些实施例中,成型层250和底部填充层240是由不同的材料所构成。在一些实施例中,成型层250和底部填充层240是由相同的材料所构成。
如图1L所示,根据一些实施例,将成型层250接合至一载体基板260并上下翻转。根据一些实施例,载体基板260被配置以在后续制程步骤期间提供暂时性的机械及结构上的支持。根据一些实施例,载体基板260包括玻璃、氧化硅、氧化铝、金属、前述的组合、及/或其类似材料。
如图1M所示,根据一些实施例,从基板110的表面114部分地移除基板110、第一孔洞116和第二孔洞18中的绝缘层120、导电遮蔽结构132、导电结构134和150、第一孔洞116中的绝缘层140以暴露出导电结构134和150。
根据一些实施例,在移除制程之后,第一孔洞116成为第一穿孔116T,且第二孔洞118形成第二穿孔118T。根据一些实施例,导电结构150分别穿过第一穿孔116T。根据一些实施例,导电结构134分别穿过第二穿孔118T。
根据一些实施例,移除制程包括一平坦化制程,像是一化学机械研磨制程。因此,根据一些实施例,导电结构150、绝缘层140、导电遮蔽结构132、绝缘层120、和基板110的表面154、148、132b、124、和114共平面。根据一些实施例,导电遮蔽结构132与导电结构134和150及芯片220电性绝缘。
图1M-1为根据一些实施例显示图1M的半导体装置结构的一部分的俯视图。图1M为根据一些实施例显示沿着图1M-1的剖面线I-I’的剖面图。
如图1M和图1M-1所示,根据一些实施例,绝缘层140位于第一穿孔116T中且连续地围绕导电结构150。根据一些实施例,导电遮蔽结构132位于第一穿孔116T中且连续地围绕绝缘层140。
根据一些实施例,绝缘层120位于第一穿孔116T中且连续地围绕导电遮蔽结构132。根据一些实施例,绝缘层120位于第二穿孔118T中且连续地围绕导电结构134。
如图1M和图1M-1所示,根据一些实施例,于其中一个第一穿孔116T中的导电遮蔽结构132为管状(tube-shaped)。根据一些实施例,于其中一个第一穿孔116T中,绝缘层140、遮蔽结构132、和绝缘层120为彼此同心的管状结构。根据一些实施例,管状结构与导电结构150同心。
在一些实施例中,每一个导电结构150的宽度W3大致等于每一个导电结构134的宽度W4。在一些实施例中,用词“大致相等”意指“10%以内”。举例而言,根据一些实施例,用词“大致相等”意指“宽度W3和W4之间的差异为宽度W3或W4的10%以内”。
在一些实施例中,两个相邻的导电结构150之间的距离S1、两个相邻的导电结构150和134之间的距离S2、和两个相邻的导电结构134之间的距离S3彼此大致相等。
在一些实施例中,两个相邻的第一穿孔116T之间的距离S4小于两个相邻的穿孔116T和118T之间的距离S5,且距离S5小于两个相邻的第二穿孔118T之间的距离S6。
如图1N所示,根据一些实施例,形成内连线结构270于基板110的表面114之上。内连线结构270包括介电结构271、配线层272、273、和274、导电衬垫275、及导电通道结构276。
根据一些实施例,配线层272、273、和274、导电衬垫275、及导电通道结构276形成于介电结构271中。根据一些实施例,配线层272、273、和274透过位于之间的导电通道结构276与导电衬垫275彼此电性连接。
根据一些实施例,配线层272、273、和274、导电衬垫275、及导电通道结构276与导电结构134和150及导电遮蔽结构132电性连接。
根据一些实施例,配线层274包括导线274a和274b。根据一些实施例,导线274a与导电结构150电性连接。根据一些实施例,导线274b与导电遮蔽结构132电性连接。根据一些实施例,导线274a与导线274b电性绝缘。
图1N-1为根据一些实施例显示图1N的半导体装置结构的区域A的俯视图。如图1N和图1N-1所示,根据一些实施例,导线274b连续地围绕整个导线274a以降低配线层274的导线274a和相邻导线之间的信号干扰。根据一些实施例,配线层272、273、和274、导电衬垫275、及导电通道结构276是利用一单一镶嵌制程所形成。
如图1N和图1N-1所示,根据一些实施例,形成导电凸块282和286及接地凸块284于内连线结构270之上。根据一些实施例,导电凸块282和286及接地凸块284分别定位在导电衬垫275之上。根据一些实施例,导电凸块282分别透过导电衬垫275、配线层272、273、和274、及导电通道结构276与导电结构150电性连接。
根据一些实施例,接地凸块284分别透过导电衬垫275、配线层272、273、和274、及导电通道结构276与导电遮蔽结构132电性连接。导电凸块286分别透过导电衬垫275、配线层272、273、和274、及导电通道结构276与导电结构134电性连接。
如图1N和图1N-1所示,根据一些实施例,接地凸块284围绕导电凸块282、且与导线274b电性连接。根据一些实施例,导电凸块282与导线274a电性连接。根据一些实施例,接地凸块284与导电凸块282电性绝缘。
如图1O所示,根据一些实施例,将基板110上下翻转并移除载体基板260。如图1O所示,根据一些实施例,实施一切割制程以将内连线结构210和270、基板110、绝缘层120和140、和成型层250切割为独立的半导体装置结构200。
为了简单起见,根据一些实施例,图1O仅显示出其中一个半导体装置结构200。根据一些实施例,半导体装置结构200也称为芯片封装结构。
如图1O所示,根据一些实施例,在切割制程之后,形成导电遮蔽层290于成型层250、内连线结构210和270、基板110、绝缘层120和140之上。
根据一些实施例,导电遮蔽层290覆盖成型层250的顶表面252和成型层250的侧壁254、212、149、126、119、和277、内连线结构210、绝缘层140、绝缘层120、基板110、和内连线结构270。
根据一些实施例,导电遮蔽层290被配置以降低半导体装置结构200与相邻半导体装置结构200的其他半导体装置结构之间的信号干扰。导电遮蔽层290与芯片220、导电遮蔽结构132、导电结构134和150电性绝缘。
根据一些实施例,侧壁254、212、149、126、119、和277共平面。根据一些实施例,导电遮蔽层290是由金属材料或合金材料所构成。金属材料包括铜、金、铝、钨、或其他合适的金属材料。根据一些实施例,导电遮蔽层290是利用物理气相沉积制程或镀覆制程所形成。
根据一些实施例,导电结构150被配置以传递高频信号(例如,大于1GHz的频率)。导电结构134被配置以传递频率比导电结构150所传递信号的频率低的信号。根据一些实施例,导电遮蔽结构132被配置以降低导电结构150之间及/或导电结构150和134之间的信号干扰。
因为导电遮蔽结构132降低了信号干扰,可维持两个相邻的导电结构150之间的距离S1、两个相邻的导电结构150和134之间的距离S2、和两个相邻的导电结构134之间的距离S3彼此之间大致相等。也就是说,不需要增加距离S1和S2来降低信号干扰。因此,导电遮蔽结构132的形成可降低基板110和半导体装置结构200的尺寸。在一些其他的实施例中,根据设计需要,距离S1、S2、或S3中的至少两个与彼此不同。
图2为根据一些实施例显示一半导体装置结构300的剖面图。如图2所示,根据一些实施例,半导体装置结构300与图1O的半导体装置结构200相似,除了半导体装置结构300具有芯片310和320,且不具有图1O的半导体装置结构200的芯片200。
根据一些实施例,芯片310与导电结构150电性连接。根据一些实施例,芯片320与导电结构134电性连接。芯片310为高频芯片,像是射频(RF)芯片、图像处理单元(GPU)芯片、或其他合适的高频芯片。
根据一些实施例,芯片320为一低频芯片或其他合适的芯片。根据一些实施例,芯片320产生的信号的频率低于芯片310所产生的信号的频率。根据一些实施例,半导体装置结构300也称为芯片封装结构。
图3A为根据一些实施例显示半导体装置结构400的剖面图。图3B为根据一些实施例显示图3A的半导体装置结构400的基板110的底视图。图3A为根据一些实施例显示沿着图3B的切割线I-I’的半导体装置结构400的剖面图。
如图3A和图3B所示,根据一些实施例,半导体装置结构400与图2的半导体装置结构300相似,除了半导体装置结构400于第一穿孔116T之间具有第二穿孔118T。也就是说,根据一些实施例,第二穿孔118T中的导电结构134分别位于第一穿孔116T中的导电遮蔽结构132之间。
根据一些实施例,基板110具有一高频区域111。可将高频元件(例如,高频芯片)形成于高频区域111中。根据一些实施例,于高频区域111中,交替地配置第一穿孔116T和第二穿孔118T。
根据一些实施例,于高频区域111中,交替地配置导电结构134和导电遮蔽结构132。根据一些实施例,导电遮蔽结构132围绕其中一个导电结构134。根据一些实施例,导电结构134围绕其中一个导电遮蔽结构132。
因为高频区域111中的导电结构134之间的距离S7大于高频区域111之外的导电结构134之间的距离S3,距离S7可降低高频区域111中的导电结构134之间的信号干扰。根据一些实施例,半导体装置结构400也称为芯片封装结构。
根据另一些实施例所述的半导体装置结构的形成方法,其中该部分地移除该基板、该第一绝缘层、该导电层、和该第二绝缘层包括一平坦化制程。
根据另一些实施例所述的半导体装置结构的形成方法,其中该第二绝缘层的一第一厚度大于该导电层的一第二厚度,且该第二厚度大于该第一绝缘层的一第三厚度。
根据另一些实施例所述的半导体装置结构的形成方法,其中该第一孔洞的一第一宽度大于该第二孔洞的一第二宽度。
根据另一些实施例所述的半导体装置结构的形成方法,其中该形成该第二绝缘层包括:共形地沉积该第二绝缘层于该导电层和该第一表面之上;在形成该导电结构之后,形成一开口于该第二绝缘层中,其中该开口暴露出该第二孔洞中的该导电层。
根据另一些实施例所述的半导体装置结构的形成方法,其中该移除该第一表面之上的该导电层包括:于该导电层之上实施一平坦化制程直到暴露出该第一表面之上的该第一绝缘层。
根据一些实施例,提供一种半导体装置结构及其形成方法。半导体装置结构的形成方法于基板中形成导电遮蔽结构以围绕穿基板导通结构(through substrate via),藉此降低穿基板导通结构与其他相邻的穿基板导通结构之间的信号干扰。因此,不需要增加穿基板导通结构之间的距离来降低信号干扰。其结果,导电遮蔽结构的形成可降低基板的尺寸和具有所述基板的芯片封装结构的尺寸。
根据另一些实施例所述的半导体装置结构,还包括:在从该基板之该第二表面部分地移除该基板、该第一孔洞和该第二孔洞中的该第一绝缘层、该第一孔洞和该第二孔洞中的该导电层、和该第二绝缘层之后,形成一第二内连线结构于该第二表面之上,其中该第二内连线结构包括一介电结构、及该介电结构中的一第一导线和一第二导线,该第一导线和该第二导线分别与该导电结构和该导电遮蔽结构电性连接。
根据另一些实施例所述的半导体装置结构,还包括:在形成该导电凸块和该些接地凸块之后,形成一导电遮蔽层于该成型层和该晶片的顶表面及该成型层、该第一内连线结构、该基板、和该第二内连线结构的侧壁之上,其中该导电遮蔽层与该晶片和该导电遮蔽结构电性绝缘。
根据另一些实施例所述的半导体装置结构,其中该第一导电结构的底表面、该第一绝缘层的底表面、该导电遮蔽层的底表面、该第二绝缘层的底表面、该基板的底表面、该第三绝缘层的底表面、和该第二导电结构的底表面共平面。
根据另一些实施例所述的半导体装置结构,其中该第一绝缘层的一第一厚度大于该导电遮蔽结构的一第二厚度,且该第二厚度大于该第二绝缘层的一第三厚度且大于该第三绝缘层的一第四厚度。
根据另一些实施例所述的半导体装置结构,其中该第二绝缘层的一第一厚度大致等于该第三绝缘层的一第二厚度,且该第二绝缘层与该第三绝缘层直接连接。
前述内文概述了许多实施例的特征,以使本技术领域中具有通常知识者可以从各个方面更佳地了解本公开。本技术领域中具有通常知识者应可理解,且可轻易地以本公开为基础来设计或修饰其他制程及结构,并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下,可对本公开进行各种改变、置换或修改。
虽然本公开已以数个较佳实施例公开如上,然其并非用以限定本公开,任何所属技术领域中具有通常知识者,在不脱离本公开的精神和范围内,当可作任意的更动与润饰,因此本公开的保护范围当视后附的申请专利范围所界定者为准。
Claims (10)
1.一种半导体装置结构的形成方法,包括:
形成一第一孔洞和一第二孔洞于一基板的一第一表面中;
形成一第一绝缘层于该第一孔洞和该第二孔洞中;
形成一导电层于该第一绝缘层之上及该第一孔洞和该第二孔洞中,其中该导电层具有一第一凹部于该第一孔洞中并填充该第二孔洞;
形成一第二绝缘层于该导电层之上及该第一凹部中,其中该第二绝缘层具有一第二凹部于该第一凹部中;
形成一导电结构于该第二凹部中;
从该基板的一第二表面部分地移除该基板、该第一绝缘层、该导电层、和该第二绝缘层,以暴露出该导电结构及该第一孔洞和该第二孔洞中的该导电层,其中该第二表面相对于该第一表面。
2.如权利要求1所述的半导体装置结构的形成方法,其中该形成该导电层包括:
形成该导电层于该第一绝缘层之上,其中该导电层共形地覆盖第一孔洞中的该第一绝缘层以及该第一表面之上的该第一绝缘层;以及
移除该第一表面之上的该导电层。
3.如权利要求1所述的半导体装置结构的形成方法,其中从该第二表面部分地移除该基板、该第一绝缘层、该导电层、和该第二绝缘层之后,该第一孔洞中的该导电层为管状(tube-shaped)且连续地围绕该导电结构。
4.如权利要求1所述的半导体装置结构的形成方法,还包括:
在形成该导电结构于该第二凹部中及在从该第二表面部分地移除该基板、该第一绝缘层、该导电层、和该第二绝缘层之前,形成一内连线结构于该第一表面、该导电结构、和该导电层之上;
接合一芯片至该内连线结构;以及
形成一成型层(molding layer)于该内连线结构之上以围绕该芯片。
5.一种半导体装置结构的形成方法,包括:
形成一第一孔洞和一第二孔洞于一基板的一第一表面中;
共形地形成一第一绝缘层于该第一孔洞和该第二孔洞中;
形成一导电层于该第一绝缘层之上,其中该导电层共形地覆盖该第一孔洞中的该第一绝缘层并具有一第一凹部于该第一孔洞中,且该导电层填充该第二孔洞;
形成一第二绝缘层于该导电层之上,其中该第二绝缘层具有一第二凹部于该第一凹部中;
形成一导电结构于该第二凹部中以填充该第二凹部;以及
从该基板的一第二表面部分地移除该基板、该第一孔洞和该第二孔洞中的该第一绝缘层、该第一孔洞和该第二孔洞中的该导电层、和该第二绝缘层,以暴露出该导电结构和该第一孔洞和该第二孔洞中的该导电层,其中该第二表面相对于该第一表面,且该第一孔洞中的该导电层形成一导电遮蔽结构。
6.如权利要求5所述的半导体装置结构的形成方法,还包括:
在形成该导电结构于该第二凹部中及在从该基板的该第二表面部分地移除该基板、该第一孔洞和该第二孔洞中的该第一绝缘层、该第一孔洞和该第二孔洞中的该导电层、和该第二绝缘层之前,形成一第一内连线结构于该第一表面、该导电结构、和该导电层之上;
将一芯片接合至该第一内连线结构,其中该芯片透过该第一内连线结构与该导电结构和该第二孔洞中的该导电层电性连接,且该第一孔洞中的该导电层与该导电结构、该第二孔洞中的该导电层、及该芯片电性绝缘;以及
形成一成型层于该第一内连线结构之上以围绕该芯片。
7.如权利要求6所述的半导体装置结构的形成方法,其中该第一导线与该第二导线电性绝缘,且该第二导线连续地围绕整个该第一导线。
8.如权利要求6所述的半导体装置结构的形成方法,还包括:
形成一导电凸块和复数个接地凸块于该第二内连线结构之上,其中该导电凸块与该导电结构电性连接,且该接地凸块与该导电遮蔽结构电性连接并围绕该导电凸块。
9.一种半导体装置结构,包括:
一基板;
一第一导电结构,穿过该基板;
一第一绝缘层,穿过该基板并围绕该第一导电结构;
一导电遮蔽结构,穿过该基板并围绕该第一绝缘层;
一第二绝缘层,穿过该基板并围绕该导电遮蔽结构;
一第二导电结构,穿过该基板,其中该第二导电结构和该导电遮蔽结构是由相同的导电材料所构成;以及
一第三绝缘层,穿过该基板并围绕该第二导电结构,其中该第三绝缘层和该第二绝缘层是由相同的绝缘材料所构成。
10.如权利要求9所述的半导体装置结构,其中该第一导电结构的顶表面和该第一绝缘层的顶表面共平面。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102386240B (zh) * | 2010-09-01 | 2013-12-11 | 台湾积体电路制造股份有限公司 | 圆柱形嵌入式电容器 |
US20150028450A1 (en) * | 2013-07-25 | 2015-01-29 | Jae-hwa Park | Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same |
CN103824783B (zh) * | 2012-10-01 | 2017-04-26 | Nxp股份有限公司 | 包封晶片级芯片规模(wlcsp)基座封装 |
CN108028245A (zh) * | 2015-09-23 | 2018-05-11 | 南洋理工大学 | 半导体器件及形成其的方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006019455A (ja) | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7348671B2 (en) | 2005-01-26 | 2008-03-25 | Micron Technology, Inc. | Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same |
JP2007311676A (ja) | 2006-05-22 | 2007-11-29 | Sony Corp | 半導体装置とその製造方法 |
US7803714B2 (en) | 2008-03-31 | 2010-09-28 | Freescale Semiconductor, Inc. | Semiconductor through silicon vias of variable size and method of formation |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8916979B2 (en) | 2012-12-28 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-vias and methods of forming the same |
FR3007197B1 (fr) * | 2013-06-18 | 2016-12-09 | St Microelectronics Crolles 2 Sas | Procede de realisation d'une liaison electrique traversante et d'un condensateur traversant dans un substrat, et dispositif correspondant |
US9368440B1 (en) | 2013-07-31 | 2016-06-14 | Altera Corporation | Embedded coaxial wire and method of manufacture |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102386240B (zh) * | 2010-09-01 | 2013-12-11 | 台湾积体电路制造股份有限公司 | 圆柱形嵌入式电容器 |
CN103824783B (zh) * | 2012-10-01 | 2017-04-26 | Nxp股份有限公司 | 包封晶片级芯片规模(wlcsp)基座封装 |
US20150028450A1 (en) * | 2013-07-25 | 2015-01-29 | Jae-hwa Park | Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same |
CN108028245A (zh) * | 2015-09-23 | 2018-05-11 | 南洋理工大学 | 半导体器件及形成其的方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112242365A (zh) * | 2019-07-17 | 2021-01-19 | 三星电子株式会社 | 包括贯穿基底过孔的半导体器件 |
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TWI677920B (zh) | 2019-11-21 |
DE102017127237A1 (de) | 2019-03-21 |
KR102096457B1 (ko) | 2020-04-03 |
US10515851B2 (en) | 2019-12-24 |
US11139206B2 (en) | 2021-10-05 |
TW201916171A (zh) | 2019-04-16 |
US20200075412A1 (en) | 2020-03-05 |
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