TWI677920B - 半導體裝置結構及其形成方法 - Google Patents

半導體裝置結構及其形成方法 Download PDF

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Publication number
TWI677920B
TWI677920B TW106135668A TW106135668A TWI677920B TW I677920 B TWI677920 B TW I677920B TW 106135668 A TW106135668 A TW 106135668A TW 106135668 A TW106135668 A TW 106135668A TW I677920 B TWI677920 B TW I677920B
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Taiwan
Prior art keywords
conductive
hole
layer
insulating layer
forming
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TW106135668A
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English (en)
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TW201916171A (zh
Inventor
余振華
Chen Hua Yu
王垂堂
Chuei Tang Wang
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
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Publication of TW201916171A publication Critical patent/TW201916171A/zh
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Abstract

本揭露提供一種半導體裝置結構之形成方法，包括：形成一第一孔洞和一第二孔洞於一基板之一第一表面中；形成一第一絕緣層於第一孔洞和第二孔洞中；形成一導電層於第一絕緣層之上及第一孔洞和第二孔洞中，其中導電層具有一第一凹部於第一孔洞中並填充第二孔洞；形成一第二絕緣層於導電層之上及第一凹部中，其中第二絕緣層具有一第二凹部於第一凹部中；形成一導電結構於第二凹部中；從基板之一第二表面部分地移除基板、第一絕緣層、導電層、和第二絕緣層，以暴露出導電結構及第一孔洞和第二孔洞中的導電層，其中第二表面相對於第一表面。本揭露亦提供一種半導體裝置結構。

Description

半導體裝置結構及其形成方法
本揭露係關於半導體裝置結構及其形成方法，且特別是有關於一種於基板中形成有導電遮蔽結構的半導體裝置結構及其形成方法。
半導體積體電路(IC)工業已歷經快速發展的階段。積體電路材料及設計在技術上的進步使得每一代生產的積體電路變得比先前生產的積體電路更小且其電路也變得更複雜。然而，這些進展也增加了積體電路加工和製造上的複雜度。
在積體電路發展的進程中，功能性密度(亦即，每一個晶片區域中內連線裝置的數目)已經普遍增加，而幾何尺寸(亦即，製程中所能創造出最小的元件或線路)則是下降。這種微縮化的過程通常可藉由增加生產效率及降低相關支出提供許多利益。
然而，由於特徵尺寸(亦即，晶片封裝結構的尺寸)持續下降，製程持續變得更加難以實現。因此，形成具有越來越小尺寸之可靠的半導體裝置為一項挑戰。
根據一實施例，本揭露提供一種半導體裝置結構 的形成方法，包括：形成一第一孔洞和一第二孔洞於一基板之一第一表面中；形成一第一絕緣層於第一孔洞和第二孔洞中；形成一導電層於第一絕緣層之上及第一孔洞和第二孔洞中，其中導電層具有一第一凹部於第一孔洞中並填充第二孔洞；形成一第二絕緣層於導電層之上及第一凹部中，其中第二絕緣層具有一第二凹部於第一凹部中；形成一導電結構於第二凹部中；從基板之一第二表面部分地移除基板、第一絕緣層、導電層、和第二絕緣層，以暴露出導電結構及第一孔洞和第二孔洞中的導電層，其中第二表面相對於第一表面。
根據另一實施例，本揭露提供一種半導體裝置結構的形成方法，包括：形成一第一孔洞和一第二孔洞於一基板之一第一表面中；共形地形成一第一絕緣層於第一孔洞和第二孔洞中；形成一導電層於第一絕緣層之上，其中導電層共形地覆蓋第一孔洞中的第一絕緣層並具有一第一凹部於第一孔洞中，且導電層填充第二孔洞；形成一第二絕緣層於導電層之上，其中第二絕緣層具有一第二凹部於第一凹部中；形成一導電結構於第二凹部中以填充第二凹部；以及從基板之一第二表面部分地移除基板、第一孔洞和第二孔洞中的第一絕緣層、第一孔洞和第二孔洞中的導電層、和第二絕緣層，以暴露出導電結構和第一孔洞和第二孔洞中的導電層，其中第二表面相對於第一表面，且第一孔洞中的導電層形成一導電遮蔽結構。
又根據另一實施例，本揭露提供一種半導體裝置結構，包括：一基板；一第一導電結構，穿過基板；一第一絕緣層，穿過基板並圍繞第一導電結構；一導電遮蔽結構，穿過 基板並圍繞第一絕緣層；一第二絕緣層，穿過基板並圍繞導電遮蔽結構；一第二導電結構，穿過基板，其中第二導電結構和導電遮蔽結構是由相同的導電材料所構成；以及一第三絕緣層，穿過基板並圍繞第二導電結構，其中第三絕緣層和第二絕緣層是由相同的絕緣材料所構成。
110‧‧‧基板
111‧‧‧高頻區域
112、114、124、132b、148、154‧‧‧表面
116‧‧‧第一孔洞
116a、118a‧‧‧內壁
116b、118b‧‧‧底表面
116T‧‧‧第一穿孔
118‧‧‧第二孔洞
118T‧‧‧第二穿孔
119、126、149、212、254、277‧‧‧側壁
120、140‧‧‧絕緣層
122、132a、134a、144、152、162、252‧‧‧頂表面
130、150a、160‧‧‧導電層
131、142‧‧‧凹部
132‧‧‧導電遮蔽結構
134、150‧‧‧導電結構
146、182a‧‧‧開口
170、271‧‧‧介電結構
172、174、176、178‧‧‧介電層
182‧‧‧罩幕層
192、196、276‧‧‧導電通道結構
194、274a、274b‧‧‧導線
198、275‧‧‧導電襯墊
200、300、400‧‧‧半導體裝置結構
210、270‧‧‧內連線結構
220、310、320‧‧‧晶片
230、282、286‧‧‧導電凸塊
240‧‧‧底部填充層
250‧‧‧成型層
260‧‧‧載體基板
272、273、274‧‧‧配線層
284‧‧‧接地凸塊
290‧‧‧導電遮蔽層
A‧‧‧區域
G‧‧‧間隙
I-I’‧‧‧剖面線
T1、T2、T3‧‧‧厚度
W1、W2、W3、W4‧‧‧寬度
S1、S2、S3、S4、S5、S6‧‧‧距離
本揭露最好配合圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準實施，各個特徵並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個特徵的尺寸。
第1A~1O圖為根據一些實施例顯示半導體裝置結構形成製程於各階段的剖面圖。
第1M-1圖為根據一些實施例顯示第1M圖之半導體裝置結構的一部分的俯視圖。
第1N-1圖為根據一些實施例顯示第1N圖之半導體裝置結構的一區域的俯視圖。
第2圖為根據一些實施例顯示一半導體裝置結構的剖面圖。
第3A圖為根據一些實施例顯示一半導體裝置結構形成製程於各階段的剖面圖。
第3B圖為根據一些實施例顯示第3A圖之半導體裝置結構的基板的底視圖。
以下揭示提供許多不同的實施方法或是例子來實 行本揭露之不同特徵。以下描述具體的元件及其排列的例子以簡化本揭露。當然這些僅是例子且不該以此限定本揭露的範圍。例如，在描述中提及第一個元件形成於第二個元件之上時，其可能包括第一個元件與第二個元件直接接觸的實施例，也可能包括兩者之間有其他元件形成而沒有直接接觸的實施例。此外，在不同實施例中可能使用重複的標號及/或符號，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖式中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係。這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。應瞭解的是，可在所述方法之前、期間、及之後提供額外的操作，且一些所述的操作在所述方法的其他實施例中可被置換或移除。
第1A~1O圖為根據一些實施例顯示半導體裝置結構形成製程於各階段的剖面圖。半導體裝置結構可為具有穿基板導通結構(through substrate vias)或晶片封裝結構的半導體基板。
如第1A圖所示，根據一些實施例，提供一基板110。根據一些實施例，基板110具有相對的表面112和114。基板110是由元素半導體材料所構成，包括單晶、多晶、或非晶結構的 矽或鍺。
在一些其他實施例中，基板110是由化合物半導體(例如：碳化矽、砷化鎵、磷化鎵、磷化銦、或砷化銦)、合金半導體(例如：SiGe或GaAsP)、或前述之組合所構成。基板110也可包括多層半導體、絕緣體上半導體(SOI)(像是絕緣體上矽或絕緣體上鍺)、或前述之組合。
如第1B圖所示，根據一些實施例，將部分的基板110從表面112移除以形成第一孔洞116和第二孔洞118於表面112中。在一些實施例中，每一個第一孔洞116的寬度W1大於每一個第二孔洞118的寬度W2。
在一些實施例中，寬度W1為每一個第一孔洞116的最大寬度，且寬度W2為每一個第二孔洞118的最大寬度。在一些實施例中，每一個第一孔洞116的平均寬度大於每一個第二孔洞118的平均寬度。在一些實施例中，移除製程包括蝕刻製程，像是乾蝕刻製程。
如第1B圖所示，根據一些實施例，形成絕緣層120於基板110之上及第一孔洞116和第二孔洞118中。根據一些實施例，絕緣層120共形地覆蓋表面112、第一孔洞116的內壁116a和底表面116b、及第二孔洞118的內壁118a和底表面118b。根據一些實施例，絕緣層120也稱為襯層。
根據一些實施例，絕緣層120的厚度T1範圍介於約0.1μm至約0.2μm。根據一些實施例，絕緣層120包括氧化物(像是矽氧化物)。根據一些實施例，絕緣層120是利用熱氧化製程或化學氣相沉積製程所形成。
如第1C圖所示，根據一些實施例，形成導電層130於絕緣層120之上及第一孔洞116和第二孔洞118中。根據一些實施例，導電層130共形地覆蓋第一孔洞116中的絕緣層120及表面112之上的絕緣層120。
因此，根據一些實施例，導電層130分別於第一孔洞中具有凹部131。根據一些實施例，導電層130填充第二孔洞118。因此，根據一些實施例，導電層130於第二孔洞118中不具有凹部。
根據一些實施例，導電層130是由金屬材料或合金材料所構成。金屬材料包括銅、金、鋁、鎢、或其他合適的金屬材料。根據一些實施例，導電層130的形成包括：形成一種子層(未顯示)於絕緣層120之上；及鍍覆一導電材料層(未顯示)於種子層之上。根據一些實施例，導電材料層的鍍覆包括一電鍍製程。
如第1D圖所示，根據一些實施例，移除表面112之上的導電層130。根據一些實施例，殘留在每一個第一孔洞116中的導電層130形成一導電遮蔽結構132。根據一些實施例，殘留在每一個第二孔洞118中的導電層130形成一導電結構134。
根據一些實施例，在移除表面112之上的導電層130之後，導電遮蔽結構132和導電結構134與彼此電性絕緣。根據一些實施例，導電遮蔽結構132和導電結構134藉由位於之間的絕緣層120與基板110電性絕緣。
根據一些實施例，移除製程包括於導電層130之上實施一平坦化製程直到暴露出表面112之上的絕緣層120。根據 一些實施例，平坦化製程包括一化學機械研磨(CMP)製程。在一些實施例中，在移除製程之後，導電遮蔽結構132、絕緣層120、和導電結構134的頂表面132a、122、和134a共平面。
如第1E圖所示，根據一些實施例，形成絕緣層140於導電遮蔽結構132、導電結構134、和表面112之上。根據一些實施例，絕緣層140共形地覆蓋導電遮蔽結構132、導電結構134、和表面112。因此，根據一些實施例，絕緣層140分別在凹部131中具有凹部142。
根據一些實施例，導電遮蔽結構132(或導電層130)具有一厚度T2。根據一些實施例，絕緣層140具有一厚度T3。根據一些實施例，厚度T3大於厚度T2。根據一些實施例，厚度T2大於絕緣層120的厚度T1。
在一些實施例中，絕緣層140的平均厚度大於導電遮蔽結構132(或導電層130)的平均厚度。在一些實施例中，導電遮蔽結構132(或導電層130)的平均厚度大於絕緣層120的平均厚度。
絕緣層140是由高介電(high-k)材料，像是氧化鉿、氧化鋯、氧化鋁、二氧化鉿-鋁合金、氧化矽鉿、氧氮化矽鉿、氧化鉭鉿、氧化鈦鉿、氧化鋯鉿、其他合適的高介電材料、或前述之組合。
絕緣層140是由氧化物材料所構成，像是氧化矽。絕緣層140是由聚合物材料所構成，像是聚醯亞胺、聚苯并噁唑(polybenzoxazole；PBO)、苯並環丁烯(benzocyclobutene；BCB)、或其類似材料。根據一些實施例，利用一沉積製程像 是化學氣相沉積製程形成絕緣層140。
如第1F圖所示，根據一些實施例，形成導電層150a於絕緣層140之上。根據一些實施例，凹部142被導電層150a填充。根據一些實施例，導電層150a是由銅、金、鋁、鎢、或其他合適的導電材料所構成。
根據一些實施例，導電層150a的形成包括形成一種子層(未顯示)於絕緣層140之上；及鍍覆一導電材料層(未顯示)於種子層之上。在一些其他實施例中，利用一物理氣相沉積製程形成導電層150a。
如第1G圖所示，根據一些實施例，移除凹部142外的導電層150a。根據一些實施例，殘留在每一個凹部142中的導電層150a形成一導電結構150。
根據一些實施例，利用一平坦化製程像是化學機械研磨製程移除凹部142外的導電層150a。因此，根據一些實施例，導電結構150的頂表面152和絕緣層140的頂表面144共平面。
如第1H圖所示，根據一些實施例，移除部分的絕緣層140以於絕緣層140中形成開口146。根據一些實施例，開口146暴露出導電結構134之頂表面134a。根據一些實施例，利用一微影製程和一蝕刻製程移除部分的絕緣層140。
如第1H圖所示，根據一些實施例，形成導電層160於開口146中。根據一些實施例，導電層160與其下方的導電結構134電性連接。根據一些實施例，導電層160與其下方的導電結構134直接接觸。
根據一些實施例，導電層160的形成包括形成一種子層(未顯示)於導電結構134和絕緣層140之上；鍍覆一導電材料層(未顯示)於種子層之上；及於導電材料層之上實施一平坦化製程直到暴露出絕緣層140的頂表面144。
根據一些實施例，平坦化製程包括一化學機械研磨(CMP)製程。因此，根據一些實施例，導電層160、絕緣層140、及導電結構150之頂表面162、144、及152共平面。
如第1I圖所示，根據一些實施例，形成介電層172於絕緣層140和導電層160之上。根據一些實施例，介電層172是由聚合物材料(例如：聚醯亞胺、PBO、或其類似材料)所構成。在一些實施例中，介電層172是由氧化物所構成，像是二氧化矽或高密度電漿氧化物。在一些實施例中，介電層172是由硼磷矽玻璃(borophosphosilicate glass；BPSG)、旋塗式玻璃(spin on glass；SOG)、未摻雜矽酸鹽玻璃(undoped silicate glass；USG)、氟化矽酸鹽玻璃(fluorinated silicate glass；FSG)、電漿增強TEOS(plasma-enhanced TEOS；PETEOS)、其類似材料、或前述之組合所構成。
根據一些實施例，介電層172和絕緣層140是由不同的材料所構成。在一些其他的實施例中，介電層172和絕緣層140是由相同的材料所構成。根據一些實施例，利用一塗佈製程形成介電層172。
如第1I圖所示，根據一些實施例，形成罩幕層182於介電層172之上。根據一些實施例，罩幕層182具有開口182a，其暴露出部分的介電層172。根據一些實施例，罩幕層182是由 光阻材料所構成。
如第1J圖所示，根據一些實施例，透過開口182a移除部分的介電層172以形成開口172a於介電層172中。如第1J圖所示，根據一些實施例，形成導電通道結構(conductive via structures)192於開口172a中。
根據一些實施例，一些導電通道結構192與其下方的導電結構150直接接觸。根據一些實施例，一些導電通道結構192與其下方的導電結構134直接接觸。導電通道結構192是由銅、鋁、或其他合適的導電材料所構成。
根據一些實施例，導電通道結構192的形成包括形成一導電材料層(未顯示)於介電層172之上以填充開口172a；及於導電材料層之上實施一平坦化製程直到暴露出介電層172。亦即，根據一些實施例，導電通道結構192是利用一單鑲嵌製程所形成。
如第1J圖所示，根據一些實施例，形成介電層174於介電層172之上。根據一些實施例，介電層174是由聚合物材料(例如：聚醯亞胺、PBO、或其類似物)所構成。在一些實施例中，介電層174是由氧化物所構成，像是二氧化矽或高密度電漿氧化物。在一些實施例中，介電層174是由硼磷矽玻璃(BPSG)、旋塗式玻璃(SOG)、未摻雜矽酸鹽玻璃(USG)、氟化矽酸鹽玻璃(FSG)、電漿增強TEOS(PETEOS)、其類似材料、或前述之組合所構成。
如第1J圖所示，根據一些實施例，形成導線194於介電層174中。根據一些實施例，導線194與導電通道結構192 電性連接。根據一些實施例，導線194與其下方的導電通道結構192直接接觸。根據一些實施例，導線194是由銅、鋁、或其他合適的導電材料所構成。根據一些實施例，導線194是利用一單鑲嵌製程所形成。
如第1J圖所示，根據一些實施例，形成介電層176於介電層174和導線194之上。根據一些實施例，介電層176是由聚合物材料(例如：聚醯亞胺、PBO、或其類似物)所構成。在一些實施例中，介電層176是由氧化物所構成，像是二氧化矽或高密度電漿氧化物。在一些實施例中，介電層176是由硼磷矽玻璃(BPSG)、旋塗式玻璃(SOG)、未摻雜矽酸鹽玻璃(USG)、氟化矽酸鹽玻璃(FSG)、電漿增強TEOS(PETEOS)、其類似材料、或前述之組合所構成。
如第1J圖所示，根據一些實施例，形成導電通道結構196於介電層176中。根據一些實施例，導電通道結構196與導線194電性連接。根據一些實施例，導電通道結構196與其下方的導線194直接接觸。根據一些實施例，導電通道結構196是由銅、鋁、或其他合適的導電材料所構成。根據一些實施例，導電通道結構196是利用一單鑲嵌製程所形成。
如第1J圖所示，根據一些實施例，形成介電層178於介電層176之上。根據一些實施例，介電層178是由聚合物材料(例如：聚醯亞胺、PBO、或其類似物)所構成。在一些實施例中，介電層178是由氧化物所構成，像是二氧化矽或高密度電漿氧化物。在一些實施例中，介電層178是由硼磷矽玻璃(BPSG)、旋塗式玻璃(SOG)、未摻雜矽酸鹽玻璃(USG)、 氟化矽酸鹽玻璃(FSG)、電漿增強TEOS(PETEOS)、其類似材料、或前述之組合所構成。
如第1J圖所示，根據一些實施例，形成導電襯墊198於介電層178中。根據一些實施例，導電襯墊198與導電通道結構196電性連接。根據一些實施例，導電襯墊198與其下方的導電通道結構196直接接觸。根據一些實施例，導電襯墊198是由銅、鋁、或其他合適的導電材料所構成。根據一些實施例，導電襯墊198是利用一單鑲嵌製程所形成。
根據一些實施例，介電層172、174、176、和178一起形成介電結構170。導電通道結構192和196、導線194、導電襯墊198、和介電結構170一起形成內連線結構210。
在一些其他實施例中，導電通道結構192和196、導線194、和導電襯墊198是利用一雙鑲嵌製程所形成。又在一些其他實施例中，介電層172是由光阻材料所構成，且根據一些實施例，介電層172和導電通道結構192的形成包括形成一光阻材料層(未顯示)於絕緣層140和導電層160之上；實施一微影製程以形成開口172a；形成一導電材料層(未顯示)於介電層172之上以填充開口172a；及於導電材料層之上實施一平坦化製程直到暴露出介電層172。
根據一些實施例，可利用與前述用來形成介電層172和導電通道結構192相似的製程來形成介電層174、176、和178、導線194、導電通道結構196、及導電襯墊198。
如第1K圖所示，根據一些實施例，透過晶片220和導墊襯墊198之間的導電凸塊230將晶片220接合至內連線結構 210。根據一些實施例，晶片220透過導電凸塊230和內連線結構210與導電結構150和134電性連接。
晶片220為一高頻晶片，像是射頻(RF)晶片、圖像處理單元(graphic processor unit；GPU)晶片、或其他合適的高頻晶片。根據一些實施例，晶片220產生具有頻率範圍介於約1GHz至約60HGz的訊號。
如第1K圖所示，根據一些實施例，形成底部填充層240於晶片220和內連線結構210之間的間隙G中。根據一些實施例，底部填充層240是由一絕緣材料像是聚合物材料所構成。
如第1K圖所示，根據一些實施例，形成一成型層(molding layer)250於內連線結構210之上。根據一些實施例，成型層250覆蓋晶片220並圍繞晶片220、底部填充層240、和導電凸塊230。
根據一些實施例，成型層250是由一絕緣材料像是聚合物材料所構成。在一些實施例中，成型層250和底部填充層240是由不同的材料所構成。在一些實施例中，成型層250和底部填充層240是由相同的材料所構成。
如第1L圖所示，根據一些實施例，將成型層250接合至一載體基板260並上下翻轉。根據一些實施例，載體基板260被配置以在後續製程步驟期間提供暫時性的機械及結構上的支持。根據一些實施例，載體基板260包括玻璃、氧化矽、氧化鋁、金屬、前述之組合、及/或其類似材料。
如第1M圖所示，根據一些實施例，從基板110的表 面114部分地移除基板110、第一孔洞116和第二孔洞18中的絕緣層120、導電遮蔽結構132、導電結構134和150、第一孔洞116中的絕緣層140以暴露出導電結構134和150。
根據一些實施例，在移除製程之後，第一孔洞116成為第一穿孔116T，且第二孔洞118形成第二穿孔118T。根據一些實施例，導電結構150分別穿過第一穿孔116T。根據一些實施例，導電結構134分別穿過第二穿孔118T。
根據一些實施例，移除製程包括一平坦化製程，像是一化學機械研磨製程。因此，根據一些實施例，導電結構150、絕緣層140、導電遮蔽結構132、絕緣層120、和基板110的表面154、148、132b、124、和114共平面。根據一些實施例，導電遮蔽結構132與導電結構134和150及晶片220電性絕緣。
第1M-1圖為根據一些實施例顯示第1M圖之半導體裝置結構的一部分的俯視圖。第1M圖為根據一些實施例顯示沿著第1M-1圖的剖面線I-I’的剖面圖。
如第1M圖和第1M-1圖所示，根據一些實施例，絕緣層140位於第一穿孔116T中且連續地圍繞導電結構150。根據一些實施例，導電遮蔽結構132位於第一穿孔116T中且連續地圍繞絕緣層140。
根據一些實施例，絕緣層120位於第一穿孔116T中且連續地圍繞導電遮蔽結構132。根據一些實施例，絕緣層120位於第二穿孔118T中且連續地圍繞導電結構134。
如第1M圖和第1M-1圖所示，根據一些實施例，於其中一個第一穿孔116T中的導電遮蔽結構132為管狀 (tube-shaped)。根據一些實施例，於其中一個第一穿孔116T中，絕緣層140、遮蔽結構132、和絕緣層120為彼此同心的管狀結構。根據一些實施例，管狀結構與導電結構150同心。
在一些實施例中，每一個導電結構150的寬度W3大致等於每一個導電結構134的寬度W4。在一些實施例中，用詞“大致相等”意指“10%以內”。舉例而言，根據一些實施例，用詞“大致相等”意指“寬度W3和W4之間的差異為寬度W3或W4的10%以內”。
在一些實施例中，兩個相鄰的導電結構150之間的距離S1、兩個相鄰的導電結構150和134之間的距離S2、和兩個相鄰的導電結構134之間的距離S3彼此大致相等。
在一些實施例中，兩個相鄰的第一穿孔116T之間的距離S4小於兩個相鄰的穿孔116T和118T之間的距離S5，且距離S5小於兩個相鄰的第二穿孔118T之間的距離S6。
如第1N圖所示，根據一些實施例，形成內連線結構270於基板110的表面114之上。內連線結構270包括介電結構271、配線層272、273、和274、導電襯墊275、及導電通道結構276。
根據一些實施例，配線層272、273、和274、導電襯墊275、及導電通道結構276係形成於介電結構271中。根據一些實施例，配線層272、273、和274透過位於之間的導電通道結構276與導電襯墊275彼此電性連接。
根據一些實施例，配線層272、273、和274、導電襯墊275、及導電通道結構276與導電結構134和150及導電遮蔽結構132電性連接。
根據一些實施例，配線層274包括導線274a和274b。根據一些實施例，導線274a與導電結構150電性連接。根據一些實施例，導線274b與導電遮蔽結構132電性連接。根據一些實施例，導線274a與導線274b電性絕緣。
第1N-1圖為根據一些實施例顯示第1N圖之半導體裝置結構的區域A的俯視圖。如1N圖和第1N-1圖所示，根據一些實施例，導線274b連續地圍繞整個導線274a以降低配線層274的導線274a和相鄰導線之間的訊號干擾。根據一些實施例，配線層272、273、和274、導電襯墊275、及導電通道結構276是利用一單一鑲嵌製程所形成。
如1N圖和第1N-1圖所示，根據一些實施例，形成導電凸塊282和286及接地凸塊284於內連線結構270之上。根據一些實施例，導電凸塊282和286及接地凸塊284分別定位在導電襯墊275之上。根據一些實施例，導電凸塊282分別透過導電襯墊275、配線層272、273、和274、及導電通道結構276與導電結構150電性連接。
根據一些實施例，接地凸塊284分別透過導電襯墊275、配線層272、273、和274、及導電通道結構276與導電遮蔽結構132電性連接。導電凸塊286分別透過導電襯墊275、配線層272、273、和274、及導電通道結構276與導電結構134電性連接。
如1N圖和第1N-1圖所示，根據一些實施例，接地凸塊284圍繞導電凸塊282、且與導線274b電性連接。根據一些 實施例，導電凸塊282與導線274a電性連接。根據一些實施例，接地凸塊284與導電凸塊282電性絕緣。
如第1O圖所示，根據一些實施例，將基板110上下翻轉並移除載體基板260。如第1O圖所示，根據一些實施例，實施一切割製程以將內連線結構210和270、基板110、絕緣層120和140、和成型層250切割為獨立的半導體裝置結構200。
為了簡單起見，根據一些實施例，第1O圖僅顯示出其中一個半導體裝置結構200。根據一些實施例，半導體裝置結構200也稱為晶片封裝結構。
如第1O圖所示，根據一些實施例，在切割製程之後，形成導電遮蔽層290於成型層250、內連線結構210和270、基板110、絕緣層120和140之上。
根據一些實施例，導電遮蔽層290覆蓋成型層250的頂表面252和成型層250的側壁254、212、149、126、119、和277、內連線結構210、絕緣層140、絕緣層120、基板110、和內連線結構270。
根據一些實施例，導電遮蔽層290被配置以降低半導體裝置結構200與相鄰半導體裝置結構200的其他半導體裝置結構之間的訊號干擾。導電遮蔽層290與晶片220、導電遮蔽結構132、導電結構134和150電性絕緣。
根據一些實施例，側壁254、212、149、126、119、和277共平面。根據一些實施例，導電遮蔽層290是由金屬材料或合金材料所構成。金屬材料包括銅、金、鋁、鎢、或其他合適的金屬材料。根據一些實施例，導電遮蔽層290是利用物理氣相沉積製程或鍍覆製程所形成。
根據一些實施例，導電結構150被配置以傳遞高頻訊號(例如，大於1GHz的頻率)。導電結構134被配置以傳遞頻率比導電結構150所傳遞訊號的頻率低的訊號。根據一些實施例，導電遮蔽結構132被配置以降低導電結構150之間及/或導電結構150和134之間的訊號干擾。
因為導電遮蔽結構132降低了訊號干擾，可維持兩個相鄰的導電結構150之間的距離S1、兩個相鄰的導電結構150和134之間的距離S2、和兩個相鄰的導電結構134之間的距離S3彼此之間大致相等。也就是說，不需要增加距離S1和S2來降低訊號干擾。因此，導電遮蔽結構132的形成可降低基板110和半導體裝置結構200的尺寸。在一些其他的實施例中，根據設計需要，距離S1、S2、或S3中的至少兩個與彼此不同。
第2圖為根據一些實施例顯示一半導體裝置結構300的剖面圖。如第2圖所示，根據一些實施例，半導體裝置結構300與第1O圖的半導體裝置結構200相似，除了半導體裝置結構300具有晶片310和320，且不具有第1O圖的半導體裝置結構200的晶片200。
根據一些實施例，晶片310與導電結構150電性連接。根據一些實施例，晶片320與導電結構134電性連接。晶片310為高頻晶片，像是射頻(RF)晶片、圖像處理單元(GPU)晶片、或其他合適的高頻晶片。
根據一些實施例，晶片320為一低頻晶片或其他合適的晶片。根據一些實施例，晶片320產生之訊號的頻率低於 晶片310所產生之訊號的頻率。根據一些實施例，半導體裝置結構300也稱為晶片封裝結構。
第3A圖為根據一些實施例顯示半導體裝置結構400的剖面圖。第3B圖為根據一些實施例顯示第3A圖之半導體裝置結構400的基板110的底視圖。第3A圖為根據一些實施例顯示沿著第3B圖之切割線I-I’的半導體裝置結構400的剖面圖。
如第3A圖和第3B圖所示，根據一些實施例，半導體裝置結構400與第2圖的半導體裝置結構300相似，除了半導體裝置結構400於第一穿孔116T之間具有第二穿孔118T。也就是說，根據一些實施例，第二穿孔118T中的導電結構134分別位於第一穿孔116T中的導電遮蔽結構132之間。
根據一些實施例，基板110具有一高頻區域111。可將高頻元件(例如，高頻晶片)形成於高頻區域111中。根據一些實施例，於高頻區域111中，交替地配置第一穿孔116T和第二穿孔118T。
根據一些實施例，於高頻區域111中，交替地配置導電結構134和導電遮蔽結構132。根據一些實施例，導電遮蔽結構132圍繞其中一個導電結構134。根據一些實施例，導電結構134圍繞其中一個導電遮蔽結構132。
因為高頻區域111中的導電結構134之間的距離S7大於高頻區域111之外的導電結構134之間的距離S3，距離S7可降低高頻區域111中的導電結構134之間的訊號干擾。根據一些實施例，半導體裝置結構400也稱為晶片封裝結構。
根據一些實施例，提供一種半導體裝置結構及其 形成方法。半導體裝置結構的形成方法於基板中形成導電遮蔽結構以圍繞穿基板導通結構(through substrate via)，藉此降低穿基板導通結構與其他相鄰的穿基板導通結構之間的訊號干擾。因此，不需要增加穿基板導通結構之間的距離來降低訊號干擾。其結果，導電遮蔽結構的形成可降低基板的尺寸和具有所述基板的晶片封裝結構的尺寸。
前述內文概述了許多實施例的特徵，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本揭露已以數個較佳實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (11)

  1. 一種半導體裝置結構之形成方法，包括：形成一第一孔洞和一第二孔洞於一基板之一第一表面中；形成一第一絕緣層於該第一孔洞和該第二孔洞中；形成一導電層於該第一絕緣層之上及該第一孔洞和該第二孔洞中，其中該導電層具有一第一凹部於該第一孔洞中並填充該第二孔洞；形成一第二絕緣層於該導電層之上及該第一凹部中，其中該第二絕緣層具有一第二凹部於該第一凹部中；形成一導電結構於該第二凹部中，其中該第二絕緣層的形成包括：沉積該第二絕緣層於該導電層和該第一表面之上；以及在形成該導電結構之後，形成一開口於該第二絕緣層中，其中該開口暴露出該第二孔洞中的該導電層；以及從該基板之一第二表面部分地移除該基板、該第一絕緣層、該導電層、和該第二絕緣層，以暴露出該導電結構及該第一孔洞和該第二孔洞中的該導電層，其中該第二表面相對於該第一表面。
  2. 如申請專利範圍第1項所述之半導體裝置結構之形成方法，其中該形成該導電層包括：形成該導電層於該第一絕緣層之上，其中該導電層共形地覆蓋第一孔洞中的該第一絕緣層以及該第一表面之上的該第一絕緣層；以及移除該第一表面之上的該導電層；其中該移除該第一表面之上的該導電層包括：於該導電層之上實施一平坦化製程直到暴露出該第一表面之上的該第一絕緣層。
  3. 如申請專利範圍第1項所述之半導體裝置結構之形成方法，其中從該第二表面部分地移除該基板、該第一絕緣層、該導電層、和該第二絕緣層之後，該第一孔洞中的該導電層為管狀(tube-shaped)且連續地圍繞該導電結構。
  4. 如申請專利範圍第1項所述之半導體裝置結構之形成方法，更包括：在形成該導電結構於該第二凹部中及在從該第二表面部分地移除該基板、該第一絕緣層、該導電層、和該第二絕緣層之前，形成一內連線結構於該第一表面、該導電結構、和該導電層之上；接合一晶片至該內連線結構；以及形成一成型層(molding layer)於該內連線結構之上以圍繞該晶片。
  5. 一種半導體裝置結構之形成方法，包括：形成一第一孔洞和一第二孔洞於一基板之一第一表面中；形成一第一絕緣層於該第一孔洞和該第二孔洞中；形成一導電層於該第一絕緣層之上，其中該導電層覆蓋該第一孔洞中的該第一絕緣層並具有一第一凹部於該第一孔洞中，且該導電層填充該第二孔洞；形成一第二絕緣層於該導電層之上，其中該第二絕緣層具有一第二凹部於該第一凹部中；形成一導電結構於該第二凹部中以填充該第二凹部；以及從該基板之一第二表面部分地移除該基板、該第一孔洞和該第二孔洞中的該第一絕緣層、該第一孔洞和該第二孔洞中的該導電層、和該第二絕緣層，以暴露出該導電結構和該第一孔洞和該第二孔洞中的該導電層，其中該第二表面相對於該第一表面，該第一孔洞中的該導電層形成一導電遮蔽結構，且此方法更包括：在形成該導電結構於該第二凹部中之後及在從該基板之該第二表面部分地移除該基板、該第一孔洞和該第二孔洞中的該第一絕緣層、該第一孔洞和該第二孔洞中的該導電層、和該第二絕緣層之前，形成一第一內連線結構於該第一表面、該導電結構、和該導電層之上；將一晶片接合至該第一內連線結構，其中該晶片透過該第一內連線結構與該導電結構和該第二孔洞中的該導電層電性連接，且該第一孔洞中的該導電層與該導電結構、該第二孔洞中的該導電層、及該晶片電性絕緣；以及形成一成型層於該第一內連線結構之上以圍繞該晶片。
  6. 如申請專利範圍第5項所述之半導體裝置結構之形成方法，更包括：在從該基板之該第二表面部分地移除該基板、該第一孔洞和該第二孔洞中的該第一絕緣層、該第一孔洞和該第二孔洞中的該導電層、和該第二絕緣層之後，形成一第二內連線結構於該第二表面之上；其中該第二內連線結構包括一介電結構、及該介電結構中的一第一導線和一第二導線，該第一導線和該第二導線分別與該導電結構和該導電遮蔽結構電性連接。
  7. 如申請專利範圍第6項所述之半導體裝置結構之形成方法，其中該第一導線與該第二導線電性絕緣，且該第二導線連續地圍繞整個該第一導線。
  8. 如申請專利範圍第6項所述之半導體裝置結構之形成方法，更包括：形成一導電凸塊和複數個接地凸塊於該第二內連線結構之上，其中該導電凸塊與該導電結構電性連接，且該接地凸塊與該導電遮蔽結構電性連接並圍繞該導電凸塊；以及在形成該導電凸塊和該些接地凸塊之後，形成一導電遮蔽層於該成型層和該晶片的頂表面及該成型層、該第一內連線結構、該基板、和該第二內連線結構的側壁之上；其中該導電遮蔽層與該晶片和該導電遮蔽結構電性絕緣。
  9. 一種半導體裝置結構，包括：一基板；一第一導電結構，穿過該基板；一第一絕緣層，穿過該基板並圍繞該第一導電結構；一導電遮蔽結構，穿過該基板並圍繞該第一絕緣層，其中該第一絕緣層覆蓋該導電遮蔽結構的一端的頂表面；一第二絕緣層，穿過該基板並圍繞該導電遮蔽結構；一內連線結構，位於該基板之下，包括：一第一導線，與該第一導電結構電性連接；以及一第二導線，與該導電遮蔽結構的另一端電性連接並圍繞該第一導線，其中該第二導線延伸至該第二絕緣層的正下方；一第二導電結構，穿過該基板，其中該第二導電結構和該導電遮蔽結構是由相同的導電材料所構成；以及一第三絕緣層，穿過該基板並圍繞該第二導電結構，其中該第三絕緣層和該第二絕緣層是由相同的絕緣材料所構成。
  10. 如申請專利範圍第9項所述之半導體裝置結構，其中該第一導電結構的頂表面和該第一絕緣層的頂表面共平面，其中該第一導電結構的底表面、該第一絕緣層的底表面、該導電遮蔽層的底表面、該第二絕緣層的底表面、該基板的底表面、該第三絕緣層的底表面、和該第二導電結構的底表面共平面。
  11. 如申請專利範圍第9項所述之半導體裝置結構，其中該第二導線連續地圍繞該第一導線。
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