TWI559447B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI559447B
TWI559447B TW104123374A TW104123374A TWI559447B TW I559447 B TWI559447 B TW I559447B TW 104123374 A TW104123374 A TW 104123374A TW 104123374 A TW104123374 A TW 104123374A TW I559447 B TWI559447 B TW I559447B
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Taiwan
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conductive structure
dielectric layer
layer
conductive
forming
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TW104123374A
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TW201616607A (zh
Inventor
彭泰彥
吳佳典
鄭价言
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台灣積體電路製造股份有限公司
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Description

半導體裝置與其形成方法
本發明關於半導體裝置，更特別關於其鑲嵌結構與其形成方法。
半導體積體電路(IC)產業已快速成長一段時日。IC材料與設計的技術進步，使每一代的IC比前一代的IC更小且其電路更複雜。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線元件數目)，與較小的尺寸(比如製程形成的最小構件或連線)。製程尺寸縮小往往有利於增加製程效率並降低相關成本。
為符合裝置密度的需求，產業採用的方法之一為用於內連線結構的鑲嵌與雙鑲嵌結構。在鏘嵌製程中，圖案化下方的絕緣層以形成溝槽。之後沉積並平坦化導體，使導體與絕緣層齊平以形成圖案化的導體結構。雙鑲嵌製程採用類似製程，單次沉積導體使其形成並填入兩個結構(如溝槽與通孔)中。
然而在結構更小且密度需求增加的情況下，結構(如內連線結構)之間的腳距亦縮小。如此一來，製程難度持續增加。在半導體裝置中，形成腳距越來越短的內連線結構是個挑戰。
本發明一實施例提供之半導體裝置，包括：半導體基板；第一導電結構，位於半導體基板上；第一介電層，位於半導體基板上並圍繞第一導電結構；第二導電結構，位於第一導電結構上，其中第二導電結構延伸至第一導電結構中；以及第二介電層，位於第一介電層上並圍繞第二導電結構。
本發明一實施例提供之半導體裝置，包括：半導體基板；第一導電結構，位於半導體基板上，其中第一導電結構具有凹陷；第一介電層，位於半導體基板上並圍繞第一導電結構；第二導電結構，位於第一導電結構上，其中部份第二導電結構位於第一導電結構之凹陷中；以及第二介電層，位於第一介電層上並圍繞第二導電結構。
本發明一實施例提供之半導體裝置的形成方法，包括：形成第一介電層於半導體基板上；形成第一導電結構於第一介電層中；形成第二介電層於第一介電層上；形成孔洞於第二介電層中以露出第一導電結構；移除部份第一導電結構以形成凹陷；以及形成第二導電結構於孔洞及凹陷中。
H‧‧‧深度
W‧‧‧寬度
100‧‧‧半導體基板
102、106、118、130、134‧‧‧蝕刻停止層
104、108、120、132、136‧‧‧介電層
110、138‧‧‧開口
112、140‧‧‧阻障層
114、142‧‧‧導電層
116A、116B、128A、128B、144A、144B‧‧‧導電結構
117b、129b、129b’‧‧‧下表面
117t、129t‧‧‧上表面
122‧‧‧孔洞
124A、124B‧‧‧凹陷
126‧‧‧阻障區
129s‧‧‧側壁
第1A至1M圖係某些實施例中，半導體裝置於製程中不同階段的剖視圖。
第2圖係某些實施例中，半導體裝置的剖視圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本 發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本發明之某些實施例將敘述如下。第1A至1M圖係某些實施例中，半導體裝置於製程中不同階段的剖視圖。在第1A至1M圖中的製程階段之前、之中、及/或之後，可進行額外步驟。其他實施例可置換或省略上述的某些製程階段。半導體裝置可具有額外結構，而其他實施例可置換或省略下述的某些結構。
如第1A圖所示，提供半導體基板100。在某些實施例中，半導體基板100為基體半導體基板如半導體晶圓。舉例來說，半導體基板100包含矽或其他半導體元素材料(如鍺)。在某些其他實施例中，半導體基板100包含半導體化合物。半導體化合物可包含碳化矽、砷化鎵、砷化銦、磷化銦、其他合適的半導體化合物、或上述之組合。在某些實施例中，半導體基板100包含絕緣層上半導體(SOI)基板。SOI基板之製作方法可 為氧佈植隔離(SIMOX)製程、晶圓接合製程、另一適用方法、或上述之組合。
在某些實施例中，形成隔離結構(未圖示)於半導體基板100中，以定義並隔離形成於半導體基板100中的多種裝置單元(未圖示)。舉例來說，隔離結構包含淺溝槽隔離(STI)結構或局部氧化矽(LOCOS)結構。
舉例來說，形成於半導體基板100中的多種裝置單元可包含電晶體(如金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極接點電晶體(BJT)、高電壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體(PFET/NFET)、二極體、另一合適單元、或上述之組合。用以形成多種裝置單元的多種製程可為沉積、蝕刻、佈植、光微影、回火、平坦化、另一適用製程、或上述之組合。
如第1A圖所示之某些實施例中，沉積蝕刻停止層102於半導體基板100上。在某些實施例中，蝕刻停止層102形成於內連線結構(未圖示)上。內連線結構包含一或多個介電層與一或多個導電結構。舉例來說，內連線結構包含接點插塞，其電性連接至形成於半導體基板100中的裝置單元。蝕刻停止層102可用以避免內連線結構或其下之裝置單元在後續蝕刻製程中損傷。
在某些實施例中，蝕刻停止層102之組成為碳化矽(SiC)、碳氮化矽(SiCN)、碳氧化矽(SiCO)、氮化矽(SiN)、氮氧化矽(SiON)、另一合適材料、或上述之組合。在某些實施例中，蝕刻停止層102之沉積方法可為化學氣相沉積(CVD)製程、 旋轉塗佈製程、另一適用製程、或上述之組合。本發明實施例具有許多變化。在某些實施例中，並未形成蝕刻停止層102。
如第1A圖所示之某些實施例中，介電層104係沉積於蝕刻停止層102上。介電層104作為金屬間介電(IMD)層。在某些實施例中，介電層104之組成為低介電常數介電材料。低介電常數介電材料的介電常數小於二氧化矽的介電常數。舉例來說，低介電常數介電材料之介電常數介於約1.2至約3.5之間。
當半導體裝置的密度增加且電路單元的尺寸變得更小時，電阻電容(RC)延遲時間更主宰了電路效能。介電層104採用低介電常數介電材料，有助於降低RC延遲。
在某些實施例中，介電層104包含旋塗無機介電物、旋塗有機介電物、孔洞狀的介電材料、有機高分子、有機氧化矽玻璃、SiOF系列材料、氫倍半矽氧烷(HSQ)系列材料、甲基倍半矽氧烷(MSQ)系列材料、孔洞狀的有機系列材料、另一合適材料、或上述之組合。在某些實施例中，介電層104包含的材料具有矽、碳、氧、與氫。舉例來說，介電層104包含SiO2、SiOC、SiON、SiCOH、SiOCN、或上述之組合。在某些實施例中，介電層104之組成為掺雜碳的氧化矽。掺雜碳的氧化矽亦可稱作有機矽酸鹽玻璃(OSG)或C-氧化物。在某些實施例中，掺雜碳的氧化矽包含甲基倍半矽氧烷(MSQ)、氫倍半矽氧烷(HSQ)、聚倍半矽氧烷、另一合適材料、或上述之組合。在某些實施例中，介電層104包含掺雜氟的矽酸鹽玻璃(FSG)如掺雜氟的-(O-Si(CH3)2O)O-。在某些實施例中，介電層104之沉積方法為CVD製程、旋轉塗佈製程、噴灑塗佈製程、另一適 用製程、或上述之組合。
如第1A圖所示之某些實施例中，蝕刻停止層106沉積於介電層104上。接著圖案化蝕刻停止層106以保護其下方之部份介電層104免於後續蝕刻製程的蝕刻。在某些實施例中，蝕刻停止層106之組成與蝕刻停止層102之組成不同。
在某些實施例中，蝕刻停止層106之組成為氮化物材料。在某些其他實施例中，蝕刻停止層106之組成為氧化物材料、氮化物材料、碳化物材料、另一合適材料、或上述之組合。舉例來說，蝕刻停止層106之組成為碳化矽(SiC)、氮碳化矽(SiCN)、碳氧化矽(SiCO)、氮化矽(SiN)、氮氧化矽(SiON)、另一合適材料、或上述之組合。在某些實施例中，蝕刻停止層106之沉積方法為CVD製程、旋轉塗佈製程、另一適用製程、或上述之組合。本發明實施例具有許多變化。在某些其他實施例中，並未形成蝕刻停止層106。
如第1A圖所示之某些實施例中，介電層108沉積於蝕刻停止層106上。在某些實施例中，介電層108的材料與形成方法，與前述之介電層104的材料與形成方法類似。
如第1B圖所示之某些實施例中，移除部份介電層108、蝕刻停止層106、介電層104、與蝕刻停止層102以形成一或多個開口110。在某些實施例中，每一開口110露出蝕刻停止層102下的內連線結構或裝置單元。在某些實施例中，開口110與溝槽可用以形成導電線路。在某些實施例中，開口110的形成方法為光微影與蝕刻製程。多種蝕刻品可依序使用，以形成開口110。
如第1C圖所示之某些實施例中，阻障層112係沉積於介電層108與開口110的底部與側壁上。之後沉積導電層114於阻障層112上，如第1C圖所示之某些實施例。阻障層112可用以避免導電層114之金屬材料擴散至介電層108與104。阻障層112亦可作為導電層114與介電層104或108之間的黏著層。
在某些實施例中，阻障層112之組成為氮化鈦、氮化鉭、鈦、氮化鎢、另一合適材料、或上述之組合。在某些實施例中，阻障層112的沉積方法為物理氣相沉積(PVD)製程、CVD製程、原子層沉積(ALD)製程、無電電鍍製程、另一適用製程、或上述之組合。
在某些實施例中，導電層114之組成為銅、鋁、鎢、鈦、鎳、金、鉑、另一合適導電材料、或上述之組合。在某些實施例中，導電層114之沉積方法可為電化學電鍍製程、無電電鍍製程、PVD製程、CVD製程、旋轉塗佈製程、另一適用製程、或上述之組合。
在某些實施例中，在沉積導電層114之前，先沉積晶種層(未圖示)於阻障層112上。在某些實施例中，晶種層係順應性地形成於阻障層112上。晶種層係用以輔助形成導電層114。
在某些實施例中，晶種層之組成為銅或銅合金。在某些實施例中，晶種層包括銅、銀、金、鈦、鋁、鎢、另一合適材料、或上述之組合。在某些實施例中，晶種層之沉積方法可為PVD製程、CVD製程、另一適用製程、或上述之組合。本發明實施例具有許多變化。在某些其他實施例中，並未形成 晶種層。
如第1D圖所示之某些實施例中，移除開口110之外的部份導電層114與阻障層112。如此一來，形成導電結構116A與116B。如第1D圖所示，蝕刻停止層102與106及介電層104與108，圍繞導電結構116A與116B。在某些實施例中，導電結構116A與116B為導電線路，其可電性連接至半導體基板100之上或之中對應的裝置單元。舉例來說，內連線結構之接點插塞(未圖示)可用以形成導電結構與裝置單元之間的電性連接。
在某些實施例中，在導電層114上進行平坦化製程，直到露出介電層108。平坦化製程可包含化學機械研磨(CMP)製程、研磨製程、蝕刻製程、另一適用製程、或上述之組合。
如第1E圖所示之某些實施例中，蝕刻停止層118與介電層120沉積於介電層108及導電結構116A與116B上。在某些實施例中，蝕刻停止層118的材料與形成方法，與蝕刻停止層102的材料與形成方法類似。在某些實施例中，介電層120的材料與形成方法，與介電層104的材料與形成方法類似。
如第1F圖所示之某些實施例中，移除部份介電層120與蝕刻停止層118以形成一或多個孔洞122。在某些實施例中，孔洞122露出導電結構116A與116B。在某些實施例中，孔洞122可作為後續形成之導電通孔所用之通孔孔洞。在某些實施例中，孔洞122的形成方法可為光微影製程與蝕刻製程。多種蝕刻品可依序使用，以形成孔洞122。
當半導體裝置的結構尺寸持續縮小，微影疊對控 制變得越來越難。在某些情況下，孔洞122與導電結構116A或116B之間可能產生對不準或偏移。如第1F圖所示的某些情況下，導電結構116A與孔洞122之間產生對不準。孔洞122不只露出導電結構116A的頂部，亦露出導電結構116A之側壁上的阻障層112。蝕刻停止層106可保護其下之介電層108免於形成孔洞122製程的蝕刻。
如第1G圖所示之某些實施例中，移除部份導電結構116A與116B以形成凹陷124A與124B。在某些實施例中，移除部份導電結構116A與116B之方法為化學處理。化學處理關於施加一或多種液態及/或氣態的移除劑。在某些實施例中，濕蝕刻製程及/或乾蝕刻製程係用以使導電結構116A與116B凹陷。蝕刻停止層106可保護其下方之介電層108免於形成凹陷124A與124B製程的損傷。
如第1F圖所示，每一凹陷124A與124B具有深度H。深度H為凹陷124A或124B之底部與導電結構116A或116B之上表面之間的距離。在某些實施例中，凹陷124A的深度H與凹陷124B的深度H實質上相同。在某些其他實施例中，凹陷124A與124B的深度不同。
在某些實施例中，深度H介於約5nm至約20nm之間。如第1H圖所示，每一導電結構116A與116B具有寬度W。寬度W介於約7nm至約20nm之間。在某些實施例中，深度H與寬度W的比例(H/W)介於約0.33至約1之間。在某些其他實施例中，深度H與寬度W的比例(H/W)介於約0.25至約2.85之間。
如第1H圖所示之某些實施例中，阻障區126形成於 介電層120上。在某些實施例中，阻障區126圍繞孔洞122。在某些實施例中，阻障區126亦形成於介電層108中。阻障區126係用以避免後續形成於孔洞122中的導電結構其金屬材料擴散至介電層120與108。在這些情況下，沒有阻障層形成於孔洞122之側壁上。
在某些實施例中，阻障區126為介電層120與108之掺雜區。阻障區126包含掺質如氮、氫、另一合適掺質、或上述之組合。在某些實施例中，阻障區126之形成方法為電漿處理、浸泡處理、另一合適處理、或上述之組合。舉例來說，用以形成阻障區126之反應氣體包含氫氣、氮氣、氬氣、另一合適反應氣體、或上述之組合。舉例來說，可採用之製程壓力介於約1mTorr至約100Torr之間，而製程溫度可介於約25℃至約400℃之間。在某些實施例中，阻障區126比介電層120的其他部份緻密。
本發明實施例可具有多種變化，而不限於上述實施例。在某些其他實施例中，並未形成阻障區126。在某些實施例中，阻障層(未圖示)係形成於孔洞122的側壁上，且阻障層之材料與形成方法，可與阻障層112之材料與形成方法類似。
如第1I圖所示之某些實施例中，導電結構128A與128B係形成於孔洞122及凹陷124A與124B中。如第1I圖所示，蝕刻停止層118與介電層120與108圍繞導電結構128A與128B。在某些實施例中，導電結構128A與128B凸出於介電層120上。
在某些實施例中，導電結構128A與128作為導電通 孔，其分別電性連接至導電結構116A與116B。在某些實施例中，導電結構128A與128B分別直接接觸導電結構116A與116B。沒有較高電阻之阻障層形成於導電結構116A與128A之間(或導電結構116B與128B之間)，因此可改善半導體裝置的效能。
如前所述，阻障區126可用以阻止導電結構128A與128B之金屬材料進一步擴散至介電層120中。阻障區126亦可用以改善導電結構128A與128B及介電層120之間的黏著性。
在某些實施例中，導電結構128A與128B之組成為鈷。在某些其他實施例中，導電結構128A與128B之組成為鈷、鈦、鎳、金、銀、鉑、鎢、鈀、銅、另一合適材料、或上述之組合。在某些實施例中，導電結構128A與128B之組成不同於導電結構116A與116B之組成。舉例來說，導電結構128A與128B之組成包含鈷，而導電結構116A與116B之組成包含銅。
本發明實施例具有許多變化。在某些其他實施例中，導電結構128A與128B及導電結構116A與116B之組成相同。舉例來說，導電結構128A與128B及導電結構116A與116B之組成為銅。
在某些實施例中，導電結構128A與128B分別直接形成於導電結構116A與116B上。在某些實施例中，導電結構128A與128B的形成方法為CVD製程、PVD製程、無電沉積製程、電化學沉積製程、另一適用製程、或上述之組合。
如第1I圖所示之某些實施例中，導電結構128A與128B分別延伸至導電結構116A與116B中。換言之，導電結構 128A與128B分別部份地埋置於導電結構116A與116B中。導電結構116A圍繞部份的導電結構128A。導電結構116B亦圍繞部份的導電結構128B。如此一來，可增加導電結構128A與116A之間的接觸面積，以及導電結構128B與116B之間的接觸面積，進而明顯地降低導電結構128A與116A之間的電阻(或導電結構128B與116B之間的電阻)。上述裝置的效能與可靠性亦改善。
即使導電結構之間(比如導電結構128A與116A之間)產生對不準或偏移，其接觸面積仍足夠大，即導電結構128A與116A之間的電阻仍維持於可接受的範圍內。
如第1J圖所示之某些實施例中，蝕刻停止層130沉積於介電層120及導電結構128A與128B上。在某些實施例中，蝕刻停止層130的材料與形成方法，與蝕刻停止層102的材料與形成方法類似。之後沉積介電層132於蝕刻停止層130上，如第1J圖所示之某些實施例。在某些實施例中，介電層132之材料與形成方法，與介電層104之材料與形成方法類似。在某些實施例中，在介電層132上進行平坦化製程，使介電層132具有實質上平坦的上表面。此平坦化製程可包含CMP製程、研磨製程、蝕刻製程、另一適用製程、或上述之組合。
如第1J圖所示之某些實施例中，蝕刻停止層134與介電層136依序沉積於介電層132上。在某些實施例中，蝕刻停止層134之材料與形成方法，與蝕刻停止層106之材料與形成方法類似。在某些實施例中，介電層136之材料與形成方法，與介電層104之材料與形成方法類似。本發明實施例具有許多變化。在某些其他實施例中，並未形成蝕刻停止層134。在某些 其他實施例中，並未形成介電層136。
如第1K圖所示之某些實施例中，移除部份的介電層136、蝕刻停止層134、介電層132、與蝕刻停止層130，以形成一或多個開口138。在某些實施例中，開口138露出導電結構128A與128B的上表面。在某些實施例中，開口138亦露出導電結構128A與128B之側壁129s。在某些實施例中，開口138作為溝槽以於後續形成導電線路。在某些實施例中，開口138之形成方法為光微影與蝕刻製程。多種蝕刻品可依序使用，以形成開口138。
如第1L圖所示之某些實施例中，阻障層140沉積於介電層136、開口138之側壁、及導電結構128A與128B上。在某些實施例中，阻障層140之材料與形成方法，與阻障層112之材料與形成方法類似。之後沉積導電層142於阻障層140上以填入開口138，如第1L圖所示之某些實施例。在某些實施例中，導電層142之組成與形成方法，與導電層114之組成與形成方法類似。在某些實施例中，導電層142之組成與導電結構128A及128B之組成不同。
如第1M圖所示之某些實施例中，移除開口138以外之部份導電層142與阻障層140。如此一來，將形成導電結構144A與144B。如第1M圖所示，蝕刻停止層130與134及介電層132與136圍繞導電結構144A與144B。在某些實施例中，導電結構144A與144B為導電線路，其分別電性連接至導電結構128A與128B。
在某些實施例中，在導電層142上進行平坦化製程 直到露出介電層136。上述平坦化製程可包括CMP製程、研磨製程、蝕刻製程、另一適用製程、或上述之組合。
如第1M圖所示之某些實施例中，導電結構144A圍繞部份的導電結構128A。同樣地，導電結構144B圍繞部份的導電結構128B。換言之，導電結構128A與128B分別延伸至導電結構144A與144B中，如第1M圖所示之某些實施例。如此一來，導電結構128A與144A之間(以及導電結構128B與144B之間)的接觸面積增加。導電結構128A與144A之間(或導電結構128B與144B之間)的電阻明顯下降。裝置效能與可靠性均改良。
即使導電結構(比如導電結構128A與144A)之間發生對不準或偏移，兩者之間的接觸面積仍夠大。導電結構128A與144A之間的電阻可維持於可接受的範圍內。
在某些實施例中，導電結構128A(或128B)的下表面129b位於導電結構116A(或116B)之上表面117t與下表面117b之間。同樣地，導電結構128A(或128B)的上表面129t位於導電結構144A(或144B)之上表面與下表面之間。
在某些實施例中，導電結構128A或128B之下表面129b為弧狀表面，如第1M圖所示。然而應理解的是本發明實施例並不限於此。第2圖係某些實施例中，半導體裝置的剖視圖。在這些實施例中，導電結構128A或128B的下表面129b'為實質上平坦的表面。藉由調整凹陷124A與124B的輪廓，可改變導電結構128A與128B的輪廓。舉例來說，可調整蝕刻條件以形成所需輪廓之凹陷124A與124B。
本發明實施例提供具有鑲嵌結構之半導體裝置的 結構與其形成方法。在形成上方的導電線路(如導電通孔)於下方的導電結構(如導電線路)前，先使下方的導電結構凹陷。堆疊的導電結構之間的接觸面積因此增加。即使堆疊的導電結構可能產生對不準或偏移，導電結構之間的接觸面積仍足以維持導電結構之間的電阻維持於可接受的範圍內。裝置效能與可靠性將明顯改善。
在某些實施例中，提供半導體裝置。半導體裝置包括半導體基板，與第一導電結構位於半導體基板上。半導體裝置亦包括第一介電層，其位於半導體基板上並圍繞第一導電結構。半導體裝置亦包括第二導電結構，其位於該第一導電結構上，且第二導電結構延伸至第一導電結構中。此外，半導體裝置包括第二介電層，其位於第一介電層上並圍繞第二導電結構。
在某些實施例中，提供半導體裝置。半導體裝置包括半導體基板與第一導電結構位於半導體基板上，且第一導電結構具有凹陷。半導體裝置亦包括第一介電層，其位於半導體基板上並圍繞第一導電結構。半導體裝置亦包括第二導電結構，其位於第一導電結構上，且部份第二導電結構位於第一導電結構之凹陷中。此外，半導體裝置包括第二介電層，其位於第一介電層上並圍繞第二導電結構。
在某些實施例中，提供半導體裝置的形成方法。此方法包括形成第一介電層於半導體基板上，以及形成第一導電結構於第一介電層中。此方法亦包括形成第二介電層於第一介電層上；以及形成孔洞於第二介電層中以露出第一導電結 構。此方法亦包括移除部份第一導電結構以形成凹陷。此外，此方法包括形成第二導電結構於孔洞及凹陷中。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明之精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
100‧‧‧半導體基板
102、106、118、130、134‧‧‧蝕刻停止層
104、108、120、132、136‧‧‧介電層
112、140‧‧‧阻障層
116A、116B、128A、128B、144A、144B‧‧‧導電結構
117b、129b‧‧‧下表面
117t、129t‧‧‧上表面
126‧‧‧阻障區
129s‧‧‧側壁

Claims (11)

  1. 一種半導體裝置，包括：一半導體基板；一第一導電結構，位於該半導體基板上；一第一介電層，位於該半導體基板上並圍繞該第一導電結構；一第二導電結構，位於該第一導電結構上，其中該第二導電結構延伸至該第一導電結構中；一第二介電層，位於該第一介電層上並圍繞該第二導電結構；一蝕刻停止層，位於該第一介電層與該第二介電層之間，其中該蝕刻停止層圍繞該第一導電結構；以及一層間介電層，位於該蝕刻停止層與該第二介電層之間，其中該層間介電層圍繞該第一導電結構與該第二導電結構。
  2. 如申請專利範圍第1項所述之半導體裝置，其中：該第二導電結構具有下表面；該第一導電結構具有上表面與下表面；以及該第二導電結構之下表面位於該第一導電結構之上表面與下表面之間。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括：一第三導電結構，位於該第二導電結構上；以及一第三介電層，位於該第二介電層上並圍繞該第三導電結構，其中該第二導電結構延伸至該第三導電結構中。
  4. 如申請專利範圍第3項所述之半導體裝置，更包括一阻障層位於該第二導電結構與該第三導電結構之間。
  5. 一種半導體裝置，包括：一半導體基板；一第一導電結構，位於該半導體基板上，其中該第一導電結構具有一凹陷；一第一介電層，位於該半導體基板上並圍繞該第一導電結構；一第二導電結構，位於該第一導電結構上，其中部份該第二導電結構位於該第一導電結構之該凹陷中；一第二介電層，位於該第一介電層上並圍繞該第二導電結構；一蝕刻停止層，位於該第一介電層與該第二介電層之間，其中該蝕刻停止層圍繞該第一導電結構；以及一層間介電層，位於該蝕刻停止層與該第二介電層之間，其中該層間介電層圍繞該第一導電結構與該第二導電結構。
  6. 如申請專利範圍第5項所述之半導體裝置，更包括：一第三導電結構，位於該第二導電結構上，其中該第二導電結構延伸至該第三導電結構中；以及一第三介電層，位於該第二介電層上並圍繞該第三導電結構。
  7. 如申請專利範圍第5項所述之半導體裝置，更包括一阻障層位於該第三導電結構與該第三介電層之間，其中該阻障層 亦位於該第三導電結構與該第二導電結構之間。
  8. 一種半導體裝置的形成方法，包括：形成一第一介電層於一半導體基板上；形成一蝕刻停止層於該第一介電層上；形成一層間介電層於該蝕刻停止層上；在形成該層間介電層後，形成一第一導電結構於該第一介電層中；形成一第二介電層於該層間介電層上；形成一孔洞於該第二介電層中以露出該第一導電結構；移除部份該第一導電結構以形成一凹陷；以及形成一第二導電結構於該孔洞及該凹陷中。
  9. 如申請專利範圍第8項所述之半導體裝置的形成方法，更包括形成一阻障層於該第二介電層中，其中該阻障層圍繞該孔洞。
  10. 如申請專利範圍第8項所述之半導體裝置的形成方法，更包括：形成一第三介電層於該第二介電層上；形成一開口於該第三介電層中以露出該第二導電結構，其中該開口露出該第二導電結構的上表面與側壁；以及形成一第三導電結構於該開口中。
  11. 如申請專利範圍第10項所述之半導體裝置的形成方法，更包括在形成該第三導電結構前，先形成一阻障層於該開口之側壁以及該第二導電結構上。
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KR20160044990A (ko) 2016-04-26
US10475703B2 (en) 2019-11-12
US20170316975A1 (en) 2017-11-02
US20160276221A1 (en) 2016-09-22
US9397045B2 (en) 2016-07-19
US9721836B2 (en) 2017-08-01
DE102014115955A1 (de) 2016-04-21
US20200027788A1 (en) 2020-01-23
KR20160141687A (ko) 2016-12-09
US10847418B2 (en) 2020-11-24
CN105870102B (zh) 2018-09-25
KR101742925B1 (ko) 2017-06-01
US20160111371A1 (en) 2016-04-21
CN105870102A (zh) 2016-08-17
DE102014115955B4 (de) 2020-06-04

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