CN105870102A - 镶嵌结构的结构和形成方法 - Google Patents

镶嵌结构的结构和形成方法 Download PDF

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CN105870102A
CN105870102A CN201510027762.5A CN201510027762A CN105870102A CN 105870102 A CN105870102 A CN 105870102A CN 201510027762 A CN201510027762 A CN 201510027762A CN 105870102 A CN105870102 A CN 105870102A
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conductive component
dielectric layer
layer
conductive
certain embodiments
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CN201510027762.5A
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CN105870102B (zh
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彭泰彥
吴佳典
郑价言
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了半导体器件的结构和形成方法。该半导体器件包括半导体衬底和位于半导体衬底上方的第一导电部件。该半导体器件也包括位于半导体衬底上方并且围绕第一导电部件的第一介电层。该半导体器件还包括位于第一导电部件上方的第二导电部件，并且第二导电部件延伸到第一导电部件内。此外，该半导体器件包括位于第一介电层上方并且围绕第二导电部件的第二介电层。本发明还涉及镶嵌结构的结构和形成方法。

Description

镶嵌结构的结构和形成方法
技术领域
本发明涉及集成电路器件，更具体地，涉及镶嵌结构的结构和形成方法。
背景技术
半导体集成电路(IC)产业已经经历了快速增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代IC都比前一代IC具有更小和更复杂的电路。在IC演化过程中，功能密度(即，每芯片面积的互连器件的数量)已普遍增大，而部件尺寸(即，使用制造工艺可以产生的最小组件)却已减小。这种按比例缩小的工艺通常通过提高生产效率和降低相关成本提供益处。
工业中用来满足对器件密度的需求的一种方法是对互连结构采用镶嵌和双镶嵌结构。在镶嵌工艺中，下面的绝缘层被图案化为具有开口沟槽。然后，沉积并抛光导体至绝缘层的水平处以形成图案化的导体部件。双镶嵌工艺使用类似的方法，其中，形成两个部件(沟槽和通孔)并且通过导体的单个沉积填充该两个部件。
然而，随着部件尺寸进一步缩小并且密度需求增大，诸如互连结构的部件之间的间距减小。结果，制造工艺不断地变得更难以实施。在半导体器件中形成具有越来越短的间距的互连结构是个挑战。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种半导体器件，包括：半导体衬底；第一导电部件，位于所述半导体衬底上方；第一介电层，位于所述半导体衬底上方并且围绕所述第一导电部件；第二导电部件，位于所述第一导电部件上方，其中，所述第二导电部件延伸至所述第一导电部件内；以及第二介电层，位于所述第一介电层上方并且围绕所述第二导电部件。
在上述半导体器件中，其中，所述第一导电部件和所述第二导电部件由不同的材料制成。
在上述半导体器件中，其中，所述第二导电部件包括钴。
在上述半导体器件中，其中，所述第二导电部件具有底面，所述第一导电部件具有顶面和底面，以及所述第二导电部件的所述底面位于所述第一导电部件的所述顶面和所述底面之间。
在上述半导体器件中，其中，所述第一导电部件与所述第二导电部件直接接触。
在上述半导体器件中，其中，所述半导体器件还包括：第三导电部件，位于所述第二导电部件上方；以及第三介电层，位于所述第二介电层上方并且围绕所述第三导电部件。
在上述半导体器件中，其中，所述半导体器件还包括：第三导电部件，位于所述第二导电部件上方；以及第三介电层，位于所述第二介电层上方并且围绕所述第三导电部件，其中，所述第二导电部件延伸至所述第三导电部件内。
在上述半导体器件中，其中，所述半导体器件还包括：第三导电部件，位于所述第二导电部件上方；以及第三介电层，位于所述第二介电层上方并且围绕所述第三导电部件，其中，所述第二导电部件延伸至所述第三导电部件内，其中，所述半导体器件还包括：阻挡层，位于所述第二导电部件和所述第三导电部件之间。
在上述半导体器件中，其中，所述第一导电部件是导线，并且所述第二导电部件是导电通孔。
在上述半导体器件中，其中，所述第二导电部件突出于所述第二介电层之上。
根据本发明的另一方面，提供了一种半导体器件，包括：半导体衬底；第一导电部件，位于所述半导体衬底上方，其中，所述第一导电部件具有凹槽；第一介电层，位于所述半导体衬底上方并且围绕所述第一导电部件；第二导电部件，位于所述第一导电部件上方，其中，所述第二导电部件的部分位于所述第一导电部件的所述凹槽中；以及第二介电层，位于所述第一介电层上方并且围绕所述第二导电部件。
在上述半导体器件中，其中，所述第一导电部件包括铜，并且所述第二导电部件包括钴。
在上述半导体器件中，其中，所述第二导电部件与所述第一导电部件直接接触。
在上述半导体器件中，其中，所述半导体器件还包括：第三导电部件，位于所述第二导电部件上方，其中，所述第二导电部件延伸至所述第三导电部件内；以及第三介电层，位于所述第二介电层上方并且围绕所述第三导电部件。
在上述半导体器件中，其中，所述半导体器件还包括：阻挡层，位于所述第三导电部件和所述第三介电层之间，其中，所述阻挡层也位于述第三导电部件和所述第二导电部件之间。
根据本发明的又一方面，提供了一种形成半导体器件的方法，包括：在半导体衬底上方形成第一介电层；在所述第一介电层中形成第一导电部件；在所述第一介电层上方形成第二介电层；在所述第二介电层中形成孔以暴露所述第一导电部件；部分地去除所述第一导电部件以形成凹槽；以及在所述孔和所述凹槽中形成第二导电部件。
在上述方法中，其中，所述方法还包括：在所述第二介电层中形成阻挡区，其中，所述阻挡区围绕所述孔。
在上述方法中，其中，所述方法还包括：在所述第二介电层上方形成第三介电层；在所述第三介电层中形成开口以暴露所述第二导电部件，其中，所述开口暴露所述第二导电部件的顶面和侧壁；以及在所述开口中形成第三导电部件。
在上述方法中，其中，所述方法还包括：在所述第二介电层上方形成第三介电层；在所述第三介电层中形成开口以暴露所述第二导电部件，其中，所述开口暴露所述第二导电部件的顶面和侧壁；以及在所述开口中形成第三导电部件，其中，所述方法还包括：在形成所述第三导电部件之前，在所述开口的侧壁以及所述第二导电部件上方形成阻挡层。
在上述方法中，其中，在所述第一导电部件上直接形成所述第二导电部件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1M是根据一些实施例的用于形成半导体器件的工艺的各个阶段的截面图。
图2是根据一些实施例的半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文中使用的空间相对描述符可以同样地作出相应的解释。
描述了本发明的一些实施例。图1A至图1M是根据一些实施例的用于形成半导体器件的工艺的各个阶段的截面图。可以在图1A至图1M中描述的阶段之前、期间和/或之后提供额外的操作。对于不同的实施例，可以代替或消除描述的一些阶段。在半导体器件中可以添加额外的部件。对于不同的实施例，可以代替或消除下面描述的一些部件。
如图1A所示，提供了半导体衬底100。在一些实施例中，半导体衬底100是诸如半导体晶圆的块状半导体衬底。例如，半导体衬底100包括硅或诸如锗的其他元素半导体材料。在一些其他实施例中，半导体衬底100包括化合物半导体。化合物半导体可以包括碳化硅、砷化镓、砷化铟、磷化铟、其他合适的化合物半导体或它们的组合。在一些实施例中，半导体衬底100包括绝缘体上半导体(SOI)衬底。可以使用注氧隔离(SIMOX)工艺、晶圆接合工艺、其他适用的方法或它们的组合制造SOI衬底。
在一些实施例中，在半导体衬底100中形成隔离部件(未示出)以限定并且隔离在半导体衬底100中形成的各种器件元件(未示出)。例如，隔离部件包括浅沟槽隔离(STI)部件或硅的局部氧化(LOCOS)部件。
可以在半导体衬底100中形成的各种器件元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)、二极管、其他合适的元件或它们的组合。实施各种工艺以形成各种器件元件，各种工艺诸如沉积、蚀刻、注入、光刻、退火、平坦化、其他适用的工艺或它们的组合。
如图1A所示，根据一些实施例，在半导体衬底100上方沉积蚀刻停止层102。在一些实施例中，在包括一个或多个介电层和一个或多个导电部件的互连结构(未示出)上方形成蚀刻停止层102。例如，互连结构包括电连接至形成在半导体衬底100中的器件元件的接触插塞。蚀刻停止层102可以用于防止其下面的互连结构或器件元件在后续蚀刻工艺期间受到损坏。
在一些实施例中，蚀刻停止层102由碳化硅(SiC)、碳氮化硅(SiCN)、碳氧化硅(SiCO)、氮化硅(SiN)、氮氧化硅(SiON)、其他合适的材料或它们的组合制成。在一些实施例中，使用化学汽相沉积(CVD)工艺、旋涂工艺、其他适用的工艺或它们的组合沉积蚀刻停止层102。本发明的实施例具有许多变化。在一些其他实施例中，不形成蚀刻停止层102。
如图1A所示，根据一些实施例，在蚀刻停止层102上方沉积介电层104。介电层104用作金属间介电(IMD)层。在一些实施例中，介电层104由低k介电材料制成。该低k介电材料的介电常数小于二氧化硅的介电常数。例如，低k介电材料具有在从约1.2至约3.5的范围内的介电常数。
随着半导体器件的密度增大并且电路元件的尺寸变得更小，电阻电容(RC)延迟时间日益主导电路性能。将低k介电材料用作介电层104有助于减小RC延迟。
在一些实施例中，介电层104包括旋涂无机电介质、旋涂有机电介质、多孔介电材料、有机聚合物、有机石英玻璃、SiOF系列材料、氢倍半硅氧烷(HSQ)系列材料、甲基倍半硅氧烷(MSQ)系列材料、多孔有机系列材料、其他合适的材料或它们的组合。在一些实施例中，介电层104包括包含Si、C、O或H的材料。例如，介电层104包括SiO2、SiOC、SiON、SiCOH、SiOCN或它们的组合。在一些实施例中，介电层104由碳掺杂的氧化硅制成。碳掺杂的氧化硅也可以称为有机硅酸盐玻璃(OSG)或C-氧化物。在一些实施例中，碳掺杂的氧化硅包括甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、聚倍半硅氧烷、其他合适的材料或它们的组合。在一些实施例中，介电层104包括氟掺杂的硅酸盐玻璃(FSG)，诸如氟掺杂的-(O—Si(CH3)2—O)-。在一些实施例中，使用CVD工艺、旋涂工艺、喷涂工艺、其他适用的工艺或它们的组合沉积介电层104。
如图1A所示，根据一些实施例，在介电层104上方沉积蚀刻停止层106。然后蚀刻停止层106被图案化并且将用于保护下面的介电层104的部分在后续蚀刻工艺期间不被蚀刻。在一些实施例中，蚀刻停止层106由与蚀刻停止层102的材料不同的材料制成。
在一些实施例中，蚀刻停止层106由氮化物材料制成。在一些其他实施例中，蚀刻停止层106由氧化物材料、氮化物材料、碳化物材料、其他合适的材料或它们的组合制成。例如，蚀刻停止层106由碳化硅(SiC)、碳氮化硅(SiCN)、碳氧化硅(SiCO)、氮化硅(SiN)、氮氧化硅(SiON)、其他合适的材料或它们的组合制成。在一些实施例中，使用化学汽相沉积(CVD)工艺、旋涂工艺、其他适用的工艺或它们的组合沉积蚀刻停止层106。本发明的实施例具有许多变化。在一些其他实施例中，不形成蚀刻停止层106。
如图1A所示，根据一些实施例，在蚀刻停止层106上方沉积介电层108。在一些实施例中，介电层108的材料和形成方法类似于上面提及的介电层104的材料和形成方法。
如图1B所示，根据一些实施例，去除介电层108、蚀刻停止层106、介电层104和蚀刻停止层102的部分以形成一个或多个开口110。在一些实施例中，每个开口110均暴露位于蚀刻停止层102下方的互连结构或器件元件。在一些实施例中，开口110是其中将形成导线的沟槽。在一些实施例中，使用光刻和蚀刻工艺形成开口110。可以循序地使用各种蚀刻剂以形成开口110。
如图1C所示，根据一些实施例，在介电层108上方以及开口110的底部和侧壁上方沉积阻挡层112。然后，如图1C所示，根据一些实施例，在阻挡层112上方沉积导电层114。阻挡层112用于保护介电层108和104免受导电层114中的金属材料的扩散的影响。阻挡层112也用作导电层114和介电层104或108之间的粘合层。
在一些实施例中，阻挡层112由氮化钛、氮化钽、钛、氮化钨、其他合适的材料或它们的组合制成。在一些实施例中，使用物理汽相沉积(PVD)工艺、CVD工艺、原子层沉积(ALD)工艺、化学镀工艺、其他适用的工艺或它们的组合沉积阻挡层112。
在一些实施例中，导电层114由铜、铝、钨、钛、镍、金、铂、其他合适的导电材料或它们的组合制成。在一些实施例中，使用电化学镀工艺、化学镀工艺、PVD工艺、CVD工艺、旋涂工艺、其他适用的工艺或它们的组合沉积导电层114。
在一些实施例中，根据一些实施例，在沉积导电层114之前，在阻挡层112上方沉积晶种层(未示出)。在一些实施例中，晶种层共形地形成在阻挡层112上方。晶种层用于辅助导电层114的形成。
在一些实施例中，晶种层由铜或铜合金制成。在一些实施例中，晶种层包括铜、银、金、钛、铝、钨、其他合适的材料或它们的组合。在一些实施例中，使用PVD工艺、CVD工艺、其他适用的工艺或它们的组合沉积晶种层。本发明的实施例具有许多变化。在一些其他实施例中，不形成晶种层。
如图1D所示，根据一些实施例，去除位于开口110的外部的导电层114和阻挡层112的部分。结果，形成了导电部件116A和116B。如图1D所示，蚀刻停止层102和106以及介电层104和108围绕导电部件116A和116B。在一些实施例中，导电部件116A和116B是电连接至形成于半导体衬底100中或上的相应的器件元件的导线。例如，互连结构的接触插塞(未示出)用于形成导电部件和器件元件之间的电连接。
在一些实施例中，对导电层114实施平坦化工艺，直到暴露介电层108。平坦化工艺可以包括化学机械抛光(CMP)工艺、研磨工艺、蚀刻工艺、其他适用的工艺或它们的组合。
如图1E所示，根据一些实施例，在介电层108和导电部件116A和116B上方沉积蚀刻停止层118和介电层120。在一些实施例中，蚀刻停止层118的材料和形成方法类似于蚀刻停止层102的材料和形成方法。在一些实施例中，介电层120的材料和形成方法类似于介电层104的材料和形成方法。
如图1F所示，根据一些实施例，去除介电层120和蚀刻停止层118的部分以形成一个或多个孔122。在一些实施例中，孔122暴露导电部件116A和116B。在一些实施例中，孔122用作其中将形成导电通孔的通孔。在一些实施例中，使用光刻工艺和蚀刻工艺形成孔122。可以循序地使用各种蚀刻剂以形成孔122。
随着半导体器件的部件尺寸不断减小，光刻覆盖控制变得越来越难。在一些情况下，可能发生孔122和导电部件116A或116B之间的未对准或偏移。如图1F所示，在一些情况下，发生导电部件116A和孔122之间的未对准。孔122不仅暴露导电部件116A的顶部，而且暴露导电部件116A的侧壁上的阻挡层112。蚀刻停止层106可以保护其下面的介电层104在孔122的形成期间不被蚀刻。
如图1G所示，根据一些实施例，去除导电部件116A和116B的部分以形成凹槽124A和124B。在一些实施例中，通过化学处理部分地去除导电部件116A和116B。化学处理包括施加一种或多种液体和/或气体去除试剂。在一些实施例中，湿蚀刻工艺和/或干蚀刻工艺用于使导电部件116A和116B凹进。蚀刻停止层106可以保护其下面的介电层104在凹槽124A和124B的形成期间不被损坏。
如图1G所示，每个凹槽124A和124B均具有深度H。深度H是凹槽124A或124B的底部与导电部件116A或116B的顶面117t之间的距离。在一些实施例中，凹槽124A的深度H基本上等于凹槽124B的深度H。在一些其他实施例中，凹槽124A和124B的深度彼此不同。
在一些实施例中，深度H在从约5nm至约20nm的范围内。如图1H所示，每个导电部件116A和116B均具有宽度W。宽度W可以在从约7nm至约20nm的范围内。在一些实施例中，深度H与宽度W的比率(H/W)在从约0.33至约1的范围内。在一些其他实施例中，深度H与宽度W的比率(H/W)在从约0.25至约2.85的范围内。
如图1H所示，根据一些实施例，在介电层120中形成阻挡区126。在一些实施例中，阻挡区126围绕孔122。在一些实施例中，阻挡区126也形成在介电层108中。阻挡区126用于保护介电层120和108免受将形成在孔122中的导电部件的金属材料的扩散的影响。在这些情况下，在孔122的侧壁上方不形成阻挡层。
在一些实施例中，阻挡区126是介电层120和108的掺杂区。阻挡区126包括诸如氮、氢、其他合适的掺杂剂或它们的组合的掺杂剂。在一些实施例中，使用等离子体处理、浸渍处理、其他合适的处理或它们的组合形成阻挡区126。例如，包括H2、N2、Ar、其他合适的反应气体或它们的组合的反应气体可以用于形成阻挡区126。例如，可以使用从约1毫托至约100托的范围内的处理压力以及从约25摄氏度至约400℃的范围内的处理温度。在一些实施例中，阻挡区126比介电层120的其他部分更加致密。
本发明的实施例具有许多变化并且不限于上面提及的实施例。在一些其他实施例中，不形成阻挡区126。在一些实施例中，在孔122的侧壁上方形成阻挡层(未示出)。阻挡层的材料和形成方法可以类似于阻挡层112的材料和形成方法。
如图1I所示，根据一些实施例，在孔122以及凹槽124A和124B中形成导电部件128A和128B。如图1I所示，蚀刻停止层118和介电层120和108围绕导电部件128A和128B。在一些实施例中，导电部件128A和128B突出于介电层120之上。
在一些实施例中，导电部件128A和128B用作分别电连接至导电部件116A和116B的导电通孔。在一些实施例中，导电部件128A和128B分别与导电部件116A和116B直接接触。在导电部件116A和128A之间或者在导电部件116B和128B之间不形成具有较高电阻的阻挡层。因此改进了半导体器件的性能。
如上所述，阻挡区126可以用于防止导电部件128A和128B的金属材料进一步扩散到介电层120内。阻挡区126也可以用于改进导电部件128A和128B与介电层120之间的粘附。
在一些实施例中，导电部件128A和128B由钴制成。在一些其他实施例中，导电部件128A和128B由钴、钛、镍、金、银、铂、钨、钯、铜、其他合适的材料或它们的组合制成。在一些实施例中，导电部件128A和128B由与导电部件116A和116B的材料不同的材料制成。例如，导电部件128A和128B由钴制成(或含钴)，而导电部件116A和116B由铜制成(或含铜)。
本发明的实施例具有许多变化。在一些其他实施例中，导电部件128A和128B以及导电部件116A和116B由相同的材料制成。例如，导电部件128A和128B以及导电部件116A和116B均由铜制成。
在一些实施例中，在导电部件116A和116B上分别直接形成导电部件128A和128B。在一些实施例中，通过CVD工艺、PVD工艺、化学沉积工艺、电化学沉积工艺、其他适用的工艺或它们的组合形成导电部件128A和128B。
如图1I所示，根据一些实施例，导电部件128A和128B分别延伸到导电部件116A和116B内。换句话说，导电部件128A和128B分别部分地嵌入在导电部件116A和116B中。导电部件116A围绕导电部件128A的部分。导电部件116B也围绕导电部件128B的部分。结果，导电部件128A和116A之间的接触面积以及导电部件128B和116B之间的接触面积增大。因此，导电部件128A和116A之间(或128B和116B之间)的电阻显著减小。改进了器件的性能和可靠性。
即使发生导电部件之间(诸如128A和116A之间)的未对准或偏移，导电部件之间的接触面积仍足够大。导电部件128A和116A之间的电阻可以保持在可接受范围内。
如图1J所示，根据一些实施例，在介电层120以及导电部件128A和128B上方沉积蚀刻停止层130。在一些实施例中，蚀刻停止层130的材料和形成方法类似于蚀刻停止层102的材料和形成方法。然后，如图1J所示，根据一些实施例，在蚀刻停止层130上方沉积介电层132。在一些实施例中，介电层132的材料和形成方法类似于介电层104的材料和形成方法。在一些实施例中，对介电层132实施平坦化工艺以提供介电层132的基本上平坦的顶面。平坦化工艺可以包括CMP工艺、研磨工艺、蚀刻工艺、其他适用的工艺或它们的组合。
如图1J所示，根据一些实施例，在介电层132上方循序地沉积蚀刻停止层134和介电层136。在一些实施例中，蚀刻停止层134的材料和形成方法类似于蚀刻停止层106的材料和形成方法。在一些实施例中，介电层136的材料和形成方法类似于介电层104的材料和形成方法。本发明的实施例具有许多变化。在一些其他实施例中，不形成蚀刻停止层134。在一些其他实施例中，不形成介电层136。
如图1K所示，根据一些实施例，去除介电层136、蚀刻停止层134、介电层132和蚀刻停止层130的部分以形成一个或多个开口138。在一些实施例中，开口138暴露导电部件128A和128B的顶面。在一些实施例中，开口138也暴露导电部件128A和128B的侧壁129s。在一些实施例中，开口138是其中将形成导线的沟槽。在一些实施例中，使用光刻和蚀刻工艺形成开口138。可以循序地使用各种蚀刻剂以形成开口138。
如图1L所示，根据一些实施例，在介电层136、开口138的侧壁、以及导电部件128A和128B的上方沉积阻挡层140。在一些实施例中，阻挡层140的材料和形成方法类似于阻挡层112的材料和形成方法。然后，如图1L所示，根据一些实施例，在阻挡层140上方沉积导电层142以填充开口138。在一些实施例中，导电层142的材料和形成方法类似于导电层114的材料和形成方法。在一些实施例中，导电层142由与导电部件128A和128B的材料不同的材料制成。
如图1M所示，根据一些实施例，去除位于开口138的外部的导电层142和阻挡层140的部分。结果，形成了导电部件144A和144B。如图1M所示，蚀刻停止层130和134以及介电层132和136围绕导电部件144A和144B。在一些实施例中，导电部件144A和144B是分别电连接至导电部件128A和128B的导线。
在一些实施例中，对导电层142实施平坦化工艺，直到暴露介电层136。平坦化工艺可以包括化学机械抛光(CMP)工艺、研磨工艺、蚀刻工艺、其他适用的工艺或它们的组合。
如图1M所示，根据一些实施例，导电部件144A围绕导电部件128A的部分。类似地，导电部件144B围绕导电部件128B的部分。换句话说，如图1M所示，根据一些实施例，导电部件128A和128B分别延伸到导电部件144A和144B内。因此，导电部件128A和144A之间的接触面积以及导电部件128B和144B之间的接触面积增大。导电部件128A和144A之间(或128B和144B之间)的电阻显著减小。改进了器件的性能和可靠性。
即使发生导电部件之间(诸如128A和144A之间)的未对准或偏移，导电部件之间的接触面积仍足够大。导电部件128A和144A之间的电阻可以保持在可接受范围内。
在一些实施例中，导电部件128A(或128B)的底面129b位于导电部件116A(或116B)的顶面117t和底面117b之间。类似地，导电部件128A(或128B)的顶面129t位于导电部件144A(或144B)的顶面和底面之间。
如图1M所示，在一些实施例中，导电部件128A或128B的底面129b是弯曲表面。然而，应该理解，本发明的实施例不限于此。图2是根据一些实施例的半导体器件的截面图。在这些实施例中，导电部件128A或128B的底面129b’是基本上平坦的表面。通过调节凹槽124A和124B的轮廓，可以改变导电部件128A和128B的轮廓。例如，调整蚀刻条件以形成具有期望轮廓的凹槽124A和124B。
本发明的实施例提供了具有镶嵌结构的半导体器件的结构和形成方法。在下面的导线上形成上面的导电部件(诸如导电通孔)之前，使下面的导电部件(诸如导线)凹进。增大了堆叠的导电部件之间的接触面积。即使可能发生堆叠的导电部件之间的未对准或偏移，堆叠的导电部件之间的接触面积仍足够以将它们之间的电阻保持在可接受范围内。显著改进了器件的性能和可靠性。
根据一些实施例，提供了一种半导体器件。该半导体器件包括半导体衬底和位于半导体衬底上方的第一导电部件。该半导体器件也包括位于半导体衬底上方并且围绕第一导电部件的第一介电层。该半导体器件还包括位于第一导电部件上方的第二导电部件，并且第二导电部件延伸到第一导电部件内。此外，该半导体器件包括位于第一介电层上方并且围绕第二导电部件的第二介电层。
根据一些实施例，提供了一种半导体器件。该半导体器件包括半导体衬底和位于半导体衬底上方的第一导电部件，并且第一导电部件具有凹槽。该半导体器件也包括位于半导体衬底上方并且围绕第一导电部件的第一介电层。该半导体器件还包括位于第一导电部件上方的第二导电部件，并且第二导电部件的部分位于第一导电部件的凹槽中。此外，该半导体器件包括位于第一介电层上方并且围绕第二导电部件的第二介电层。
根据一些实施例，提供了一种形成半导体器件的方法。该方法包括在半导体衬底上方形成第一介电层以及在第一介电层中形成第一导电部件。该方法也包括在第一介电层上方形成第二介电层以及在第二介电层中形成孔以暴露第一导电部件。该方法还包括部分地去除第一导电部件以形成凹槽。此外，该方法包括在孔和凹槽中形成第二导电部件。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
半导体衬底；
第一导电部件，位于所述半导体衬底上方；
第一介电层，位于所述半导体衬底上方并且围绕所述第一导电部件；
第二导电部件，位于所述第一导电部件上方，其中，所述第二导电部件延伸至所述第一导电部件内；以及
第二介电层，位于所述第一介电层上方并且围绕所述第二导电部件。
2.根据权利要求1所述的半导体器件，其中，所述第一导电部件和所述第二导电部件由不同的材料制成。
3.根据权利要求1所述的半导体器件，其中，所述第二导电部件包括钴。
4.根据权利要求1所述的半导体器件，其中：
所述第二导电部件具有底面，
所述第一导电部件具有顶面和底面，以及
所述第二导电部件的所述底面位于所述第一导电部件的所述顶面和所述底面之间。
5.根据权利要求1所述的半导体器件，其中，所述第一导电部件与所述第二导电部件直接接触。
6.根据权利要求1所述的半导体器件，还包括：
第三导电部件，位于所述第二导电部件上方；以及
第三介电层，位于所述第二介电层上方并且围绕所述第三导电部件。
7.根据权利要求6所述的半导体器件，其中，所述第二导电部件延伸至所述第三导电部件内。
8.根据权利要求7所述的半导体器件，还包括：
阻挡层，位于所述第二导电部件和所述第三导电部件之间。
9.一种半导体器件，包括：
半导体衬底；
第一导电部件，位于所述半导体衬底上方，其中，所述第一导电部件具有凹槽；
第一介电层，位于所述半导体衬底上方并且围绕所述第一导电部件；
第二导电部件，位于所述第一导电部件上方，其中，所述第二导电部件的部分位于所述第一导电部件的所述凹槽中；以及
第二介电层，位于所述第一介电层上方并且围绕所述第二导电部件。
10.一种形成半导体器件的方法，包括：
在半导体衬底上方形成第一介电层；
在所述第一介电层中形成第一导电部件；
在所述第一介电层上方形成第二介电层；
在所述第二介电层中形成孔以暴露所述第一导电部件；
部分地去除所述第一导电部件以形成凹槽；以及
在所述孔和所述凹槽中形成第二导电部件。
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