CN103515308B - 铜内连结构及其制造方法 - Google Patents

铜内连结构及其制造方法 Download PDF

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CN103515308B
CN103515308B CN201310101937.3A CN201310101937A CN103515308B CN 103515308 B CN103515308 B CN 103515308B CN 201310101937 A CN201310101937 A CN 201310101937A CN 103515308 B CN103515308 B CN 103515308B
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copper
insulating barrier
dielectric layer
interconnect structure
layers
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黄琦雯
苏国辉
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Nanya Technology Corp
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Abstract

本发明公开一种铜内连结构及其制造方法，所述方法包括提供具有导电区域的基板，在基板上形成具有介层开口的绝缘层，介层开口暴露出导电区域。依序通过沉积及回流工艺，在第一绝缘层上形成铜层，且填满介层开口。在铜层上形成掩模层以覆盖介层开口，接着对未被掩模层覆盖的铜层进行非等向性氧化。通过湿蚀刻工艺去除掩模层及氧化铜层，以形成位于介层开口的铜插塞及位于铜插塞上的铜接线。本发明因为通过形成铜层后所进行的回流工艺可消除对应于介层开口的铜层内所形成的孔洞，因此可增加铜内连结构的可靠度。再者，通过非电镀工艺形成铜层，铜内连线内的杂质可以减少或消除。因此，可降低铜内连线的电阻，进而增强其电特性。

Description

铜内连结构及其制造方法
技术领域
本发明涉及一种半导体技术，尤其涉及一种铜内连结构及其制造方法。
背景技术
集成电路（integratedcircuit,IC）的制造中，集成电路其中的半导体装置(例如晶体管、电阻、电容或其他公知的半导体部件)的尺寸不断缩小，以增加装置密度。个别半导体装置通常由内连结构作为电性连接。
上述内连结构包括插塞及金属层，其中铝及铝合金常作为金属内连材料。然而，因为铜比惯用的铝及铝合金具有较低的电阻，可以减少时间常数(RC，R是集成电路的电阻，而C是集成电路的电容)的延迟及集成电路的电力损耗，因此，铜广泛地应用于半导体装置的内连结构。
内连结构通常通过双镶嵌工艺所制造。图1A至图1E绘示出由双镶嵌工艺制造铜内连结构的公知方法剖面示意图。请参照图1A，提供一基板100，例如一硅基板。基板100可包含导电层102，其包括金属(例如铜)，通常用于接线连接基板内及基板上不相连的半导体装置(未绘示)。一绝缘层104形成于基板100上，其包括内层介电层(interlayerdielectric，ILD)和/或金属层间介电层(intermetaldielectric，IMD)。再者，具有开口图案106a的第一光阻层106形成于绝缘层104上。
请参照图1B，由第一光阻层106作为蚀刻掩模层进行非等向性蚀刻，产生穿透绝缘层104的介层开口104a，以暴露出导电层102。去除第一光阻层106后，具有沟槽开口图案108a的第二光阻层108形成于绝缘层104上。
请参照图1C，由第二光阻层108作为蚀刻掩模层，同样进行非等向性蚀刻，产生穿透绝缘层104的沟槽开口104b，如此一来沟槽开口104b对应于介层开口104a上方，而形成双镶嵌开口。去除第二光阻层108后，在绝缘层104上及双镶嵌开口(即沟槽开口104b及介层开口104a)的内侧表面顺应性形成铜种子层110。
请参照图1D，进行电镀工艺，以在绝缘层104上形成铜层112，且填满双镶嵌开口。之后，通过化学机械研磨工艺(chemicalmechanicalpolishing，CMP)，去除双镶嵌开口上过量的铜层112，如图1E所示。
然而，由于当半导体装置的尺寸缩小，内连结构的尺寸也缩小，因而增加了双镶嵌开口的深宽比(aspectratio,AR)。如此一来，当进行电镀工艺时，铜层112内可能形成一个或多个孔洞114(如图1D及图1E所示)。再者，因为进行电镀工艺的缘故，铜层112内的杂质(未绘示)可能会增加，此缺点使内连结构的电阻增加而使其可靠度降低。
因此，为了减轻或排除上述的问题，有必要发展出改良的铜内连结构及其改良的制造方法。
发明内容
为了克服现有技术的缺陷，本发明提供一种铜内连结构的制造方法，包括提供具有导电区域的基板，在基板上形成具有介层开口的第一绝缘层，介层开口暴露出导电区域。依序通过沉积及回流工艺，在第一绝缘层上形成铜层且填满介层开口，在铜层上形成掩模层以覆盖介层开口，接着对未被掩模层覆盖的铜层进行非等向性氧化。通过湿蚀刻工艺去除掩模层及氧化铜层，以形成位于介层开口内的铜插塞及位于该铜插塞上的铜接线。
本发明因为通过形成铜层后所进行的回流工艺可消除对应于介层开口的铜层内所形成的孔洞，因此可增加铜内连结构的可靠度。再者，通过非电镀工艺形成铜层，铜内连线内的杂质可以减少或消除。因此，可降低铜内连线的电阻，进而增强其电特性。
附图说明
图1A至图1E是绘示出由双镶嵌工艺制造铜内连结构的公知方法剖面示意图。
图2A至图2F是绘示出根据本发明实施例的用于半导体装置的铜内连结构制造方法剖面示意图。
其中，附图标记说明如下：
公知
实施例
具体实施方式
有关本发明的前述及其他技术内容、特点与功效，在以下配合参考附图的一较佳实施例的详细说明中，将可清楚的呈现。然而，可轻易了解本发明所提供的实施例仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
请参照图2F，其绘示出一种用于半导体装置的一铜内连结构，其包括基板200、第一绝缘层204、第二绝缘层220及内连线218。在本实施例中，基板200可为硅基板或其他半导体材料的基板，基板200可包括不同的元件(未绘示，例如晶体管、电阻、电容或其他公知的半导体部件)。再者，基板200可包括至少一导电区域202，以将基板200内的元件电性连接其他位于其内的元件或通过后续形成的内连线(例如铜内连线)与外部电路(未绘示)电性连接。在一实施例中，导电区域202可为一金属层(例如铜或铝或其他公知的接线材料)。另外，导电区域202可为掺杂区域(例如N型或P型掺杂区域)。
第一绝缘层204内具有至少一介层开口204a且设置于基板200上，介层开口204a暴露出基板200的导电区域202。在一实施例中，第一绝缘层200可作为内层介电层(interlayerdielectric，ILD)或金属层间介电层(intermetaldielectric，IMD)。再者，第一绝缘层204可包括氧化硅、磷硅玻璃(phosphosilicateglass，PSG)、硼磷硅玻璃(borophosphosilicateglass，BPSG)或低介电常数(k)的材料(例如氟硅玻璃(fluorosilicateglass，FSG)或有机硅玻璃(organosilicateglass，OSG))或其组合。
内连线218设置于第一绝缘层204上，且通过形成于第一绝缘层204内的介层开口204a电性连接位于基板200上的导电区域202。在本实施例中，内连线218包括铜插塞218a及铜接线218b。铜接线218b对应于介层开口204a且设置于第一绝缘层204上。铜插塞218a从铜接线218b延伸入介层开口204a，使铜插塞218a及铜接线218b为一体成形。内连线218还包括一非必要的金属阻障层(未绘示)，例如钛、氮化钛、钽、氮化钽或其组合，其顺应性形成于介层开口204a内表面及第一绝缘层204与铜接线218b之间。
第二绝缘层220顺应性覆盖第一绝缘层204及铜接线218b，第二绝缘层220可作为扩散阻障层，以避免铜接线218b内的铜原子扩散。在一实施例中，第二绝缘层220可包括低介电常数的阻障材料(例如氮化硅化合物(SiNx)、碳氮化硅或碳氧化硅化合物(SiCOx))以避免铜迁移。
在另一实施例中，铜内连结构可还包括一第三绝缘层222，以覆盖铜接线218b。例如，第三绝缘层222设置于第二绝缘层220上，以覆盖第一绝缘层204及铜接线218b。第三绝缘层222可由相同或相似于第一绝缘层204的材料所组成。
图2A至图2F是绘示出根据本发明实施例的一种用于半导体装置的铜内连结构制造方法剖面示意图。请参照图2A，提供一基板200，其可为硅基板或其他半导体基板。再者，基板200可包括至少一导电区域202，以将基板200内的元件电性连接其他位于其内的元件或通过后续形成的内连线(例如铜内连线)与外部电路(未绘示)电性连接。在一实施例中，导电区域202可为一金属层(例如铜或铝或其他公知的接线材料)。另外，导电区域202可为掺杂区域(例如N型或P型掺杂区域)。
通过沉积工艺，例如等离子体辅助化学气相沉积(plasmaenhancedchemicalvapordeposition，PECVD)、高密度等离子体化学气相沉积(high-densityplasmachemicalvapordeposition，HDPCVD)或其他公知的合适的化学气相沉积，于基板200上形成一第一绝缘层204，其作为内层介电层(interlayerdielectric，ILD)或内金属介电层(intermetaldielectric，IMD)。在一实施例中，第一绝缘层204可为单层或多层的结构。再者，第一绝缘层204可包括氧化硅、磷硅玻璃(phosphosilicateglass，PSG)、硼磷硅玻璃(borophosphosilicateglass，BPSG)或低介电常数(k)的材料(例如氟硅玻璃(fluorosilicateglass，FSG)或有机硅玻璃(organosilicateglass，OSG))或其组合。接着，掩模层206(例如光阻层)通过公知的微影工艺图案化且形成于第一绝缘层204上，图案化掩模层206具有至少一开口图案206a，其对应于基板200上的导电区域202上方。
请参照图2B通过掩模层206(绘示于图2A)作为蚀刻掩模层进行一蚀刻工艺，以在第一绝缘层204内形成一介层开口204a而暴露出基板200的导电区域202。形成介层开口204a后，去除掩模层206。接着，通过合适的沉积工艺(例如物理气相沉积(physicalvapordeposition，PVD))，在第一绝缘层204上形成一铜层208且填满介层开口204a。形成铜层208之前，可视情况将金属阻障层(未绘示，例如钛、氮化钛、钽、氮化钽或其组合)顺应性形成于介层开口204a内表面。当半导体装置的尺寸缩小，介层开口204a的深宽比值高，可能使铜层208内形成孔洞209。
因此，请参照图2C，形成铜层208后，于其上进行回流工艺210，使铜层208可以完全填满介层开口204a而不会于铜层208内形成任何孔洞。在一实施例中，回流工艺210的工艺温度为250℃至450℃的范围。
请参照图2D，一掩模层212(例如光阻层)通过公知的微影工艺图案化且形成于铜层208上，而覆盖介层开口204a及铜层208上的接线形成区。接着，对未被掩模层212覆盖的铜层208进行非等向性的氧化。例如，未被掩模层212覆盖的铜层208在室温下进行去耦合等离子体氧化工艺(decouplingplasmaoxidation，DPO)214，以于第一绝缘层204上形成氧化铜层215。在进行去耦合等离子体氧化工艺(decouplingplasmaoxidation，DPO)215时，施加偏压，以驱使氧离子从铜层208表面进入其特定深度。
请参照图2E，形成氧化铜层215(绘示于图2D)后，各自地或同时地通过湿蚀刻工艺216去除掩模层212(绘示于图2D)及氧化铜层215，以暴露出部分的第一绝缘层204并于第一绝缘层204上形成内连线218。内连线218通过第一绝缘层204内的介层开口204a与基板200上的导电区域202电性连接。在本实施例中，内连线218包括铜插塞218a及铜接线218b。铜接线218b对应于介层开口204a且设置于第一绝缘层204上。铜插塞218a从铜接线218b延伸入介层开口204a。
在一实施例中，掩模层212及氧化铜层215可能同时由湿蚀刻工艺216去除，其使用的蚀刻溶液包括醋酸、氢氟酸及水，其中醋酸用于去除氧化铜层215及保护铜接线218b被蚀刻，而氢氟酸用于去除掩模层212。
在某些实施例中，蚀刻溶液可还包括硝酸，其用于去除于铜接线218b侧壁上残留的铜(未绘示)。
请参照图2F，一第二绝缘层220顺应性覆盖第一绝缘层204及铜接线218b，其可作为扩散阻障层，以避免铜接线218b内的铜原子扩散。在一实施例中，第二绝缘层220可包括低介电常数的阻障材料(例如氮化硅、碳氮化硅或碳氧化硅化合物)，且通过公知的沉积工艺形成(例如化学气相沉积(chemicalvapordeposition，CVD))。如此一来，铜内连结构即完成。
在另一实施例中，可通过公知的沉积工艺(例如化学气相沉积工艺(chemicalvapordeposition，CVD))于第二绝缘层220上形成一第三绝缘层222，使第三绝缘层222覆盖第一绝缘层204及铜接线218b。在此实施例中，第三绝缘层222可由相同或相似于第一绝缘层204的材料所组成。再者，可于第三绝缘层222及第二绝缘层220内形成额外的介层开口(未绘示)。再者，可于第三绝缘层222内形成额外的内连线(未绘示)，且通过上述额外的介层开口电性连接内连线218。额外的介层开口及额外的内连线可由相同或相似于图2A至图2E绘示的方法所形成。
根据上述实施例，因为通过形成铜层后所进行的回流工艺可消除对应于介层开口的铜层内所形成的孔洞，因此可增加铜内连结构的可靠度。再者，通过非电镀工艺形成铜层，铜内连线内的杂质可以减少或消除。因此，可降低铜内连线的电阻，进而增强其电特性。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (12)

1.一种铜内连结构的制造方法，包括：
提供具有一导电区域的一基板；
在该基板上形成具有一介层开口的一第一绝缘层，其中该介层开口暴露出该导电区域；
依序通过沉积及回流工艺在该第一绝缘层上形成一铜层且填满该介层开口；
在该铜层上形成一掩模层，以覆盖该介层开口；
对未被该掩模层覆盖的该铜层进行非等向性氧化，其中在进行非等向性氧化期间施加偏压；
通过一湿蚀刻工艺去除该掩模层及该氧化铜层，以形成位于该介层开口内的一铜插塞及位于该铜插塞上的一铜接线；以及
在该第一绝缘层及该铜接线上顺应性覆盖一第二绝缘层，其中该第一绝缘层与该第二绝缘层由不同的低介电常数的材料所构成。
2.权利要求1所述的铜内连结构的制造方法，还包括：
在该第二绝缘层上形成一第三绝缘层，以覆盖该第一绝缘层及该铜接线。
3.权利要求2所述的铜内连结构的制造方法，其中该第三绝缘层包括氧化硅，且该第二绝缘层包括一阻障层。
4.权利要求1所述的铜内连结构的制造方法，其中该导电区域包括一金属层或一掺杂区。
5.权利要求1所述的铜内连结构的制造方法，其中该沉积工艺包括一物理性气相沉积工艺。
6.权利要求1所述的铜内连结构的制造方法，其中该铜层通过一去耦合等离子体氧化工艺进行非等向性氧化。
7.权利要求1所述的铜内连结构的制造方法，其中该湿蚀刻工艺所使用的一蚀刻溶液包括醋酸及氢氟酸。
8.权利要求7所述的铜内连结构的制造方法，其中该蚀刻溶液，还包括硝酸。
9.一种铜内连结构，包括：
一基板，具有一导电区域；
一第一绝缘层，具有一介层开口且设置于该基板上，其中该介层开口暴露出该导电区域；
一铜接线，设置于该第一绝缘层上；
一铜插塞，从铜接线延伸入该介层开口；
一第二绝缘层，顺应性覆盖该第一绝缘层及该铜接线，其中该第一绝缘层与该第二绝缘层由不同的低介电常数的材料所构成；以及
一第三绝缘层，设置于该第二绝缘层上，以覆盖该第一绝缘层及该铜接线。
10.权利要求9所述的铜内连结构，其中该第三绝缘层，包括氧化硅。
11.权利要求9所述的铜内连结构，其中该第二绝缘层包括一阻障层。
12.权利要求9所述的铜内连结构，其中该导电区域包括一金属层或一掺杂区。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0859407A2 (en) * 1997-02-13 1998-08-19 Texas Instruments Incorporated Method of fabrication of a copper containing structure in a semiconductor device
US5854095A (en) * 1996-08-28 1998-12-29 Samsung Electronics Co., Ltd. Dual source gas methods for forming integrated circuit capacitor electrodes
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100215846B1 (ko) * 1996-05-16 1999-08-16 구본준 반도체장치의 배선형성방법
KR100304962B1 (ko) * 1998-11-24 2001-10-20 김영환 텅스텐비트라인형성방법
US6531407B1 (en) * 2000-08-31 2003-03-11 Micron Technology, Inc. Method, structure and process flow to reduce line-line capacitance with low-K material
KR100527668B1 (ko) * 2003-03-07 2005-11-28 삼성전자주식회사 캐패시터-언더-비트라인 구조를 갖는 반도체 장치 및 그제조방법
US20050212020A1 (en) * 2003-04-24 2005-09-29 Fujitsu Limited Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854095A (en) * 1996-08-28 1998-12-29 Samsung Electronics Co., Ltd. Dual source gas methods for forming integrated circuit capacitor electrodes
EP0859407A2 (en) * 1997-02-13 1998-08-19 Texas Instruments Incorporated Method of fabrication of a copper containing structure in a semiconductor device
US6077780A (en) * 1997-12-03 2000-06-20 Advanced Micro Devices, Inc. Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure

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