JP2007221161A - 半導体デバイスで用いられるキャパシタとその製造方法 - Google Patents
半導体デバイスで用いられるキャパシタとその製造方法 Download PDFInfo
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- JP2007221161A JP2007221161A JP2007104568A JP2007104568A JP2007221161A JP 2007221161 A JP2007221161 A JP 2007221161A JP 2007104568 A JP2007104568 A JP 2007104568A JP 2007104568 A JP2007104568 A JP 2007104568A JP 2007221161 A JP2007221161 A JP 2007221161A
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- capacitor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】半導体ウェハの基板上に形成された食刻相互接続構造(damascene)を有する半導体デバイスで使用される本発明のキャパシタは、食刻相互接続構造の一部を含む第1キャパシタ電極164と、食刻相互接続構造の上に形成され、パッシベーション層として機能する絶縁層166と、絶縁層の少なくとも一部の上に形成された導電層を含む第2キャパシタ電極168とを有する。
【選択図】図1
Description
110 集積回路
115 相互接続構造
120 誘電体層
123 n−タブ
125 p−タブ
133 ソース領域
135 ドレイン領域
140 ゲート電極構造
141 ゲート
143 酸化物層
145 スペーサ
150 食刻プラグ
152 食刻貫通導体
155 上部部分
160 食刻相互接続構造
161 バリア層
162 キャパシタ
164 第1キャパシタ電極
166 絶縁層
168 第2キャパシタ電極
170 Cu/Alバリア層
310 開口
Claims (1)
- 半導体ウェハの基板上に形成された食刻相互接続構造(damascene)を有する半導体デバイスで使用されるキャパシタにおいて、
(A)食刻相互接続構造の一部を含む第1キャパシタ電極(164)と、
(B)前記食刻相互接続構造の上に形成され、パッシベーション層として機能する絶縁層(166)と、
(C)前記絶縁層の少なくとも一部の上に形成された導電層を含む第2キャパシタ電極(168)と
を有することを特徴とする半導体デバイスで用いられるキャパシタ。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/489,092 US6498364B1 (en) | 2000-01-21 | 2000-01-21 | Capacitor for integration with copper damascene processes |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001011599A Division JP2001223339A (ja) | 2000-01-21 | 2001-01-19 | 半導体デバイスで用いられるキャパシタとその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007221161A true JP2007221161A (ja) | 2007-08-30 |
Family
ID=23942372
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001011599A Pending JP2001223339A (ja) | 2000-01-21 | 2001-01-19 | 半導体デバイスで用いられるキャパシタとその製造方法 |
JP2007104568A Pending JP2007221161A (ja) | 2000-01-21 | 2007-04-12 | 半導体デバイスで用いられるキャパシタとその製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001011599A Pending JP2001223339A (ja) | 2000-01-21 | 2001-01-19 | 半導体デバイスで用いられるキャパシタとその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US6498364B1 (ja) |
EP (1) | EP1119027B1 (ja) |
JP (2) | JP2001223339A (ja) |
KR (1) | KR100429726B1 (ja) |
DE (1) | DE60142863D1 (ja) |
TW (1) | TW477002B (ja) |
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US6576525B2 (en) * | 2001-03-19 | 2003-06-10 | International Business Machines Corporation | Damascene capacitor having a recessed plate |
US6596579B1 (en) * | 2001-04-27 | 2003-07-22 | Lsi Logic Corporation | Method of forming analog capacitor dual damascene process |
JP2003051501A (ja) * | 2001-05-30 | 2003-02-21 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6461914B1 (en) * | 2001-08-29 | 2002-10-08 | Motorola, Inc. | Process for making a MIM capacitor |
DE10159466A1 (de) * | 2001-12-04 | 2003-06-12 | Koninkl Philips Electronics Nv | Anordnung mit Kondensator |
JP2003264235A (ja) * | 2002-03-08 | 2003-09-19 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6746914B2 (en) * | 2002-05-07 | 2004-06-08 | Chartered Semiconductor Manufacturing Ltd. | Metal sandwich structure for MIM capacitor onto dual damascene |
US20040063295A1 (en) * | 2002-09-30 | 2004-04-01 | Intel Corporation | One-mask process flow for simultaneously constructing a capacitor and a thin film resistor |
KR100480641B1 (ko) * | 2002-10-17 | 2005-03-31 | 삼성전자주식회사 | 고 커패시턴스를 지니는 금속-절연체-금속 커패시터, 이를구비하는 집적회로 칩 및 이의 제조 방법 |
US7229875B2 (en) | 2002-10-17 | 2007-06-12 | Samsung Electronics Co., Ltd. | Integrated circuit capacitor structure |
KR100466310B1 (ko) * | 2002-11-13 | 2005-01-14 | 삼성전자주식회사 | 금속-절연체-금속 커패시터의 제조 방법 |
US7176082B2 (en) * | 2003-04-08 | 2007-02-13 | Lsi Logic Corporation | Analog capacitor in dual damascene process |
US7165233B2 (en) * | 2004-04-12 | 2007-01-16 | Nanya Technology Corp. | Test ket layout for precisely monitoring 3-foil lens aberration effects |
US7262139B2 (en) * | 2004-06-02 | 2007-08-28 | Avx Israel, Ltd. | Method suitable for batch ion etching of copper |
US7253522B2 (en) * | 2004-06-02 | 2007-08-07 | Avx Israel, Ltd. | Integrated capacitor for RF applications with Ta adhesion layer |
JP2006086155A (ja) * | 2004-09-14 | 2006-03-30 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2008311457A (ja) * | 2007-06-15 | 2008-12-25 | Renesas Technology Corp | 半導体装置の製造方法 |
US9831171B2 (en) * | 2014-11-12 | 2017-11-28 | Infineon Technologies Ag | Capacitors with barrier dielectric layers, and methods of formation thereof |
US9431343B1 (en) * | 2015-03-11 | 2016-08-30 | Samsung Electronics Co., Ltd. | Stacked damascene structures for microelectronic devices |
US9806018B1 (en) | 2016-06-20 | 2017-10-31 | International Business Machines Corporation | Copper interconnect structures |
KR20180068595A (ko) * | 2016-12-14 | 2018-06-22 | 삼성전자주식회사 | 반도체 장치 |
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-
2001
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- 2001-01-08 DE DE60142863T patent/DE60142863D1/de not_active Expired - Lifetime
- 2001-01-15 TW TW090100857A patent/TW477002B/zh not_active IP Right Cessation
- 2001-01-19 JP JP2001011599A patent/JP2001223339A/ja active Pending
- 2001-01-19 KR KR10-2001-0003082A patent/KR100429726B1/ko active IP Right Grant
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2002
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2007
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Patent Citations (5)
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JPH0992794A (ja) * | 1995-09-22 | 1997-04-04 | Toshiba Corp | 半導体記憶装置の製造方法 |
JPH11265984A (ja) * | 1998-03-17 | 1999-09-28 | Sony Corp | 半導体装置の製造方法 |
JP2000164812A (ja) * | 1998-11-27 | 2000-06-16 | Sharp Corp | 半導体装置及びその製造方法 |
WO2000046844A1 (en) * | 1999-02-02 | 2000-08-10 | Conexant Systems, Inc. | Thin-film capacitors and methods for forming the same |
WO2000067324A1 (fr) * | 1999-04-30 | 2000-11-09 | Hitachi, Ltd. | Circuit integre, son procede de fabrication, et procede de production d'un dessin de masque |
Also Published As
Publication number | Publication date |
---|---|
US6498364B1 (en) | 2002-12-24 |
JP2001223339A (ja) | 2001-08-17 |
EP1119027A3 (en) | 2004-11-24 |
TW477002B (en) | 2002-02-21 |
US7135733B2 (en) | 2006-11-14 |
KR20010076367A (ko) | 2001-08-11 |
KR100429726B1 (ko) | 2004-05-03 |
EP1119027B1 (en) | 2010-08-25 |
EP1119027A2 (en) | 2001-07-25 |
US20020177287A1 (en) | 2002-11-28 |
DE60142863D1 (de) | 2010-10-07 |
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