TW201810591A - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TW201810591A
TW201810591A TW105127215A TW105127215A TW201810591A TW 201810591 A TW201810591 A TW 201810591A TW 105127215 A TW105127215 A TW 105127215A TW 105127215 A TW105127215 A TW 105127215A TW 201810591 A TW201810591 A TW 201810591A
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layer
opening
metal lines
dielectric layer
forming
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TWI579998B (zh
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吳於貝
魏聖軒
李莉渝
吳岱洋
陳殿豪
鄭价言
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置的形成方法包括：形成第一介電層於基板上，以及形成多個第一凹陷於第一介電層中。形成多個金屬線路於第一凹陷中，且金屬線路沿著第一方向延伸。形成遮罩層於金屬線路與第一介電層上。遮罩層包括沿著第一方向延伸的第一開口，且第一開口位於兩個相鄰的金屬線路之間的空間上。以遮罩層作為蝕刻遮罩，蝕刻第一介電層以形成第一凹槽對應金屬線路之間的第一開口。形成第二介電層，以形成第一氣隙於第一凹槽中。第一開口於第二方向的寬度小於兩個相鄰的金屬線路於第二方向的間距，且第二方向垂直於第一方向。

Description

半導體裝置與其形成方法
本揭露關於半導體積體電路，更特別關於在金屬線路之間具有氣隙的半導體裝置與其形成方法。
新一代的積體電路(IC)具有較高效能與較多功能，當其導入半導體產業時，將增加IC的單元密度。IC的構件或單元之間的尺寸或間距將縮小，這將導致多種問題。舉例來說，當相鄰的兩個導電結構之間距縮短時，將增加寄生電容而增加耗能與電阻-電容(RC)時間常數(比如延遲訊號)。兩個相鄰的導電結構如金屬線路之間的電容，係填入導電結構之間的絕緣材料其介電常數(k值)的函數，以及導電結構之側壁表面的尺寸與導電結構之間距的函數。如此一來，半導體IC效能與功能的持續改良取決於低k值的絕緣材料發展。由於具有最低介電常數的物質為空氣(k=1.0)，氣隙可進一步降低金屬線路層的等效k值。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成第一介電層於基板上；形成多個第一凹陷於第一介電層中；形成多個金屬線路於第一凹陷中，且金屬線路沿著第一方向延伸；形成遮罩層於金屬線路與第一介電層上，遮罩層 包括沿著第一方向延伸的第一開口，且第一開口位於兩個相鄰的金屬線路之間的空間上；以遮罩層作為蝕刻遮罩，蝕刻第一介電層以形成第一凹槽對應兩個相鄰的金屬線路之間的第一開口；以及形成第二介電層以形成第一氣隙於第一凹槽中，其中第一開口於第二方向的寬度小於兩個相鄰的金屬線路於第二方向的間距，且第二方向垂直於第一方向。
本揭露一實施例提供之半導體裝置的形成方法，包括：形成第一介電層於基板上；形成多個第一凹陷於第一介電層中；形成多個金屬線路於第一凹陷中，且金屬線路沿著第一方向延伸；形成第一絕緣層於金屬線路與第一介電層上；形成第一遮罩圖案於第一絕緣層上，第一遮罩圖案包含沿著第一方向延伸的第一開口，第一開口於第二方向具有寬度，且第二方向垂直於第一方向；縮減第一開口的寬度以形成第二遮罩圖案，第二遮罩圖案具有第二開口，且第二開口的寬度小於第一開口；以第二遮罩圖案作為蝕刻遮罩，圖案化第一絕緣層以形成第三開口於第一絕緣層中，且第三開口對應第二開口；以及經由第三開口蝕刻第一介電層，以形成第一凹槽對應兩個相鄰的金屬線路之間的第三開口；以及形成第二介電層以形成第一氣隙於第一凹槽中，其中第三開口於第二方向的寬度，小於兩個相鄰之金屬線路於第二方向的間距。
本揭露一實施例提供之半導體裝置，包括：第一介電層，位於基板上；多個金屬線路埋置於第一介電層中，且金屬線路沿著第一方向延伸；第二介電層，位於第一介電層與金屬線路上；絕緣層，位於第一介電層與第二介電層之間；以 及氣隙，形成於兩個相鄰的金屬線路之間，其中絕緣層完全覆蓋兩個相鄰的金屬線路的上表面，使金屬線路的上表面不接觸第二介電層，以及絕緣層懸吊於兩個相鄰的金屬線路之間的空間上。
A1‧‧‧密線路區
A2‧‧‧疏線路區
H1‧‧‧深度
L1‧‧‧懸吊量
S1、S2‧‧‧間距
TR‧‧‧梯形區域
W1、W2、W3‧‧‧寬度
1‧‧‧基板
5‧‧‧下層結構
10‧‧‧第一ILD層
15‧‧‧第一凹陷
20‧‧‧下層的ESL
30‧‧‧下層的蓋層
50‧‧‧第二ILD層
52‧‧‧第一凹槽
54‧‧‧第二凹槽
56、58‧‧‧氣隙
90‧‧‧阻障層
100、102、104、106‧‧‧金屬線路
150‧‧‧第三ILD層
200‧‧‧第一ESL
210‧‧‧第一遮罩層
212‧‧‧交聯層
215、215’‧‧‧第一開口
217、217’‧‧‧第二開口
215”、217”‧‧‧開口
220‧‧‧第二遮罩層
230‧‧‧光阻圖案
235‧‧‧第一開口
237‧‧‧第二開口
240‧‧‧第二ESL
260‧‧‧蓋層
300‧‧‧毯覆性的間隔物層
312‧‧‧第一側壁間隔物
314‧‧‧第二側壁間隔物
第1-3、4A-10A、4B-10B、11圖係本揭露一實施例中，依序製作具有氣隙的半導體裝置的製程。
第12圖係具有氣隙的半導體裝置之比較例。
可以理解的是，下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，單元尺寸並不限於揭露的範圍或數值，而可依製程條件及/或裝置所需的性質而定。此外，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。為了簡化與清楚說明，可依不同比例任意繪示多種結構。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。此外，用語「之組成為」指的是「包括」或者「由...組成」。
第1至11圖係本揭露一實施例中，依序製作具有氣隙的半導體裝置的製程。第1-11圖之製程形成金屬線路層之一者於基板上。雖然基板與金屬線路層之間具有半導體裝置(以下稱作下層結構)，其由核心結構如電晶體或其他單元(如接點)所組成，但第1-11圖將省略這些單元的細節以簡化圖式。製程順序可視情況改變。第1至3、5A、6A、...10A、與11圖係剖視圖，而第5B、6B、...與10B圖為上視圖。
如第1圖所示，第一ILD(層間介電)層10係形成於下層結構5上，而下層結構5位於基板1上。ILD層亦可稱作IMD(金屬間介電)層。舉例來說，第一ILD層10之組成可為一或多層的低k介電材料。低k介電材料之k值低於約4.0。某些低k材料的k值可低於約3.5，而其他低k材料的k值可低於約2.5。
第一ILD層10的材料可為包含Si、O、C、及/或H等元素的化合物，比如SiCOH或SiOC。有機材料如高分子亦可作為第一ILD層10。舉例來說，第一ILD層10之組成可為一或多層的含碳材料、有機矽酸鹽玻璃、含成孔劑的材料、及/或上述之組合。在某些實施例中，第一ILD層10亦可含氮。第一ILD層10可為孔洞層。在一實施例中，第一ILD層10的密度小於約3g/cm3。在其他實施例中，第一ILD層10的密度可小於約2.5g/cm3。舉例來說，第一ILD層10的形成方法可為電漿增強化學氣相沉積(PECVD)、低壓CVD(LPCVD)、原子層CVD(ALCVD)、及/或旋轉塗佈技術。以PECVD為例，沉積膜的基板溫度介於約25℃至約400℃之間，而壓力小於100Torr。
在某些實施例中，第一ILD層10包含層間絕緣膜與 線路間絕緣膜，而金屬線路主要形成於金屬間絕緣膜中。層間絕緣膜可包含SiOC膜，而線路間絕緣膜可包含TEOS(四乙氧基矽烷)膜。
在某些實施例中，下層的ESL(蝕刻停止層)20係形成於第一ILD層10上，而下層的蓋層30係形成於下層的ESL 20上。下層的ESL 20包含一或多層的SiN、SiCO、SiON、SiCN、或SiCON。在某些實施例中，下層的蓋層30包含一或多層的氧化矽為主材料，比如氧化矽、四乙氧矽烷、或SiON。
此外，第二ILD層50形成於第一ILD層10上，或下層的蓋層30上(若採用下層的蓋層30)。第二ILD層50的材料可擇自前述之第一ILD層10的材料。
如第2圖所示，以圖案化步驟如微影與蝕刻製程形成第一凹陷15於第二ILD層50中。在某些實施例中，用以連接至一或多個下方結構的一或多個單元的一或多個通孔(接點孔，未圖示)係形成於第一凹陷15的底部。
如第3圖所示，金屬材料係形成於第一凹陷中，以形成金屬線路100、102、104、與106。用以形成金屬線路的步驟包含鑲嵌製程。在鑲嵌製程中，一或多層的金屬材料係形成於第一凹陷15中與第二ILD層50的上表面上。接著進行平坦化步驟如化學機械研磨法及/或回蝕刻法，以移除第二ILD層50其上表面上的部份金屬材料。
如第3圖所示，此實施例的半導體裝置包含密線路區A1與疏線路區A2。在密線路區A1中，金屬線路100、102、與104以間距S1排列。在疏線路區A2中，金屬線路104與106以 間距S2排列，且間距S2大於間距S1。在第3圖中，金屬線路104屬於密線路區A1與疏線路區A2以達本申請案的目的。在其他實施例中，密線路區A1與疏線路區A2並未彼此相鄰，且未共用相同的金屬線路。疏線路區A2中的金屬線路106可為虛置金屬線路，其非部份的功能電路。在第3圖中，金屬線路沿著Y方向延伸。
在一實施例中，此層中的金屬線路其間距S1為最小間距Smin，其由設計規則所定義。換言之，在半導體裝置，沒有同層的兩個相鄰金屬線路之間距小於最小間距Smin。通常半導體裝置中某一金屬線路層其最小間距Smin，可不同於其他半導體裝置或其他金屬線路層的最小間距Smin。
在某些實施例中，間距S1介於約10nm至約38nm之間。此外，一實施例之密線路區A1中的金屬線路，其線寬與間距S1實質上相同。在其他實施例中，密線路區A1中的金屬線路以間距S1排列，且SminS1<αSmin(1<α<3，比如1.2、1.5、2.0、或2.5等等)。氣隙通常形成於密線路區A1中。
相反地，疏線路區A2中相鄰的金屬線路之間距S2設定為大於間距S1。間距S2隨著半導體裝置變化，比如金屬線路的位置與功能。在一實施例中，間距S2大於S1。在此實施例中，當S1=Smin時，S2大於Smin。當SminS1<αSmin時，S2大於或等於αSmin。在其他實施例中，SminS1αSmin，且S1<S2。
用於金屬線路100、102、104、與106的一或多層金屬材料可由CVD、物理氣相沉積(PVD)如濺鍍、及/或電鍍等方法所形成。
用於金屬線路的金屬可為一或多層的Al、Cu、Co、Mn、W、Ti、Ta、TiN、TaN、TiW、WN、TiAl、TiAlN、TaC、TaCN、或TiSiN。舉例來說，金屬線路可包含阻障層90與主體層(金屬線路100、102、104、與106)。舉例來說，阻障層90之組成可為TiN及/或TaN，而主體層之組成可為Cu或銅為主的材料。金屬線路結構的形成方法可為鑲嵌製程。
在形成金屬線路100、102、104、與106後，形成第一ESL 200於金屬線路及第二ILD層50上，如第4A圖所示。第一ESL 200在後續蝕刻第二ILD層50的步驟中，作為蝕刻遮罩層。第一ESL 200包含一或多層的Si為主絕緣材料(包含Si搭配O、N、C、B、及/或H)，或Al為主絕緣材料(包含Al搭配O、N、C、B、及/或H)。第一ESL 200可為SiN、SiCO、SiCN、或SiCON。在一實施例中，可採用SiN作為第一ESL 200。
在某些實施例中，第一ESL 200之厚度介於約1nm至約30nm之間。在其他實施例中，第一ESL 200之厚度介於約5nm至約15nm之間。在一實施例中，第一ESL 200之密度小於約3g/cm3。在其他實施例中，第一ESL 200之密度小於約2.5g/cm3。
舉例來說，第一ESL 200之形成方法可為PECVD、LPCVD、ALDCVD、及/或旋轉塗佈技術。以PECVD為例，沉積第一ESL 200的基板溫度介於約25℃至約400℃之間，而壓力小於100Torr。
在形成第一ESL 200後，形成第一遮罩層200於第一ESL 200上，並形成第二遮罩層220於第一遮罩層210上，如 第4A圖所示。舉例來說，第一遮罩層210之組成可為有機材料，比如用於底抗反射塗層(BARC)的材料。第二遮罩層220之組成對第一遮罩層具有高蝕刻選擇性，比如高Si含量(大於或等於約30wt%)的有機材料(Si含量不同於第一遮罩層210)。在某些實施例中，第一遮罩層210之厚度介於約50nm至約200nm之間。在某些實施例中，第二遮罩層220之厚度介於約20nm至約50nm之間。
此外如第4A圖所示，具有第一開口235與第二開口237的光阻圖案230係形成於第一ESL 200、第一遮罩層210、與第二遮罩層220的堆疊上。在第4B圖的上視圖中，第一開口235與第二開口237的長邊延著Y方向，且位於相鄰的金屬線路之邊緣的上表面上。換言之，第一開口235與金屬線路100與102中至少一者部份重疊。
藉由光阻圖案230作為蝕刻遮罩，圖案化第二遮罩層220。接著圖案化第一遮罩層210。在圖案化第一遮罩層210的步驟中，光阻圖案230作為蝕刻遮罩。若在圖案化第一遮罩層210的步驟時已先移除光阻圖案，則圖案化後的第二遮罩層220作為蝕刻遮罩。在移除光阻圖案與第二遮罩層後，第一遮罩層具有第一開口215與第二開口217，如第5A與5B圖所示。如第5A圖所示的某些實施例中，有機材料的交聯層212係形成於圖案化的第一遮罩層210上。交聯層212可視情況省略，端視第二遮罩層的材料而定。
在圖案化第一遮罩層210後，第一開口215與第二開口217於X方向的寬度W1，大於或等於相鄰的兩個金屬線路 (比如金屬線路100與102，或者金屬線路102與104)其上表面的間距S1。如第5B圖所示之上視圖所示，開口215與217沿著Y方向的長邊，位於相鄰之金屬線路的邊緣其上表面上。換言之，第一開口215與金屬線路100與102中至少一者部份重疊。當相鄰的兩個金屬線路間距寬度為S，而金屬線路的線寬為L，則開口的寬度小於約S+L，且開口中心位於相鄰的兩金屬線路之間的空間上，即第一開口215與第二開口217彼此分離。
接著進行縮減第一開口215與第二開口217之寬度的步驟。如第6A與6B圖所示，形成毯覆性的間隔物層300於第5A與5B圖的結構上。毯覆性的間隔物層300包含氧化物材料如TiO2或ZrO2，或氮化物材料如TiN或TaN。在此實施例中，TiO2可作為毯覆性的間隔物層300。在某些實施例中，毯覆性的間隔物層300的厚度可介於約3nm至約10nm之間。
在毯覆性的間隔物層300上進行非等向蝕刻，以形成第一側壁間隔物312於第一開口215的側壁上，以及第二側壁間隔物314於第二開口217的側壁上。如此一來，遮罩圖案具有因第一側壁間隔物312而縮減的第一開口215’，以及因第二側壁間隔物314而縮減的第二開口217’，如第7A與7B圖所示。
縮減的第一開口215’其寬度W2小於相鄰的兩個金屬線路的間距S1。在某些實施例中，寬度W2介於約5nm至約10nm之間。此外如上視圖所示，縮減的第一開口215’未與下方之金屬線路100與102重疊。縮減的第二開口217’其構形與縮減的第一開口215’實質上類似。
在某些實施例中，形成第二遮罩圖案於第一ESL 200上之步驟，可讓光阻圖案之開口具有縮減的寬度W2。上述步驟採用高解析度的微影工具，比如電子束、EUV、或X光微影系統。
如第8A與8B圖所示，採用第二遮罩作為蝕刻遮罩，蝕刻圖案化第一ESL 200以形成開口215”與217”於第一ESL 200中，其分別對應縮減的第一開口215’與第二開口217’。開口215”與217”的寬度，與縮減之第一開口215’與第二開口217’的寬度實質上相同。上述蝕刻步驟將露出位於開口215”與217”底部的第二ILD層200的部份上表面。
如第9A與9B圖所示，經由開口215”與217”蝕刻第二ILD層50，以形成第一凹槽52與第二凹槽54於相鄰的金屬線路(金屬線路100與102，以及金屬線路102與104)之間。第一凹槽52對應開口215”，而第二凹槽54對應開口217”。
在一實施例中，圖案化的第一ESL 200與搭配側壁間隔物的第一遮罩層210之堆疊作為蝕刻遮罩，如第9A與9B圖所示。蝕刻第二ILD層50的方法包含乾蝕刻及/或濕蝕刻，之後進行濕式清潔製程。在某些實施例中，移除第一遮罩層210與側壁間隔物，只保留圖案化的第一ESL 200作為蝕刻遮罩。在某些實施例中，第一凹槽52於X方向的最大寬度W3介於約15nm至約20nm之間。在某些實施例中，第一凹槽52於Z方向的深度H1介於約70nm至約120nm之間。第一槽槽52之底部可低於金屬線路的底部。第二凹槽54之構形與第一凹槽52實質上相同。
在蝕刻第二ILD層50以形成第一凹槽52與第二凹槽54後，移除第一遮罩層210與側壁間隔物，如第10A與10B圖 所示。
在第10A與10B圖中，以遮罩層覆蓋而不露出與第一凹槽52相鄰之金屬線路100與102的上表面。同樣地，以遮罩層覆蓋而不露出與第二凹槽54相鄰之金屬線路102與104的上表面。部份第一ESL 200懸吊於第一凹槽52與第二凹槽54上。在某些實施例中，懸吊量L1介於介於約0.5nm至約2nm之間。
在形成凹槽並移除第一遮罩層210及側壁間隔物後，形成介電層於凹槽之中與之上，以形成氣隙56與58。介電層包含兩層或更多層的介電材料。
如第11圖所示的某些實施例中，介電層包含第二ESL 240、蓋層260、與第三ILD層150。第二ESL 240順應性地形成於第一凹槽52與第二凹槽54之內側表面上。在某些實施例中，蓋層260亦順應性地形成於第二ESL 240上。第三ILD層150與蓋層260不同，實質上不形成於凹槽中。如此一來，凹槽的上開口將會非常小。此外，第三ILD層150不覆蓋第一與第二凹槽中的部份蓋層260。在某些實施例中，蓋層260完全封閉凹槽的上開口。
如第11圖所示，形成於凹槽中的第二ESL 240之厚度，小於形成在第一ESL 200上的第二ESL 240之厚度。同樣地，形成於凹槽中的蓋層260之厚度，小於形成於地一ESL 200上的蓋層260之厚度。綜上所述，這可增加氣隙56與58之體積。在某些實施例中，氣隙56取代超過三分之二的相鄰兩金屬線路之間的體積。如第11圖的剖視圖所示，氣隙56的面積大於三分之二的金屬線路100與102之間的梯形區域TR。
第二ESL 240包含一或多層的SiN、SíCO、SiCN、或SiCON。在一實施例中，第二ESL 240採用SiN。在某些實施例中，第二ESL 240之厚度介於約5nm至約15nm之間。蓋層260包含一或多層的氧化矽為主材料，比如二氧化矽、四乙氧基矽烷、或SiON。在一實施例中，蓋層260採用四乙氧基矽烷。在某些實施例中，蓋層260之厚度介於約5nm至約15nm之間。
藉由第三ILD層150形成氣隙的方法，可採用低階梯覆蓋條件的非順應性CVD法。為採用非順應性的CVD，可在第三ILD層之絕緣材料填入凹槽前，先沉積第三ILD層於凹槽的開口處使其「夾止」，以形成氣隙於凹槽中。
第三ILD層150可包含一或多層的氧化矽、氮氧化矽(SiON)、SiCN、SiOC、SiOCN、或低k材料。舉例來說，第三ILD層150可掺雜磷以增加其形成空洞的效果。
第12圖係一比較例，其採用之遮罩圖案(對應用於蝕刻第二ILD層的第二遮罩圖案)具有較寬的開口，且開口與三個線路圖案之間的兩個空間重疊。在比較例中，蝕刻第二ILD層50時會露出並蝕刻金屬線路100、102、與104其較上部份的上表面，因此形成圓潤角落的形狀。自金屬線路移除的金屬如銅將殘留於凹槽中，需要額外的清潔步驟移除殘留的金屬。此外，可能需要額外沉積金屬材料如鈷以補償被移除的金屬線路，以避免金屬線路的上表面被侵蝕。另一方面，形成氣隙的區域其輪廓高度，低於不具有氣隙形成其中的區域。
相反地，實施例中的第一ESL 200保護金屬線路上表面，因此金屬線路較上方的角路可維持尖銳的角度而不致圓 潤化。此外，第一ESL 200、第二ESL 240、與蓋層260的疊層位於金屬線路上，在對第三ILD進行平坦化步驟(如化學機械研磨)後仍可保持相同高度。另一方面，第一ESL形成於金屬線路如銅上可避免銅層被侵蝕。再者，由於蓋層(與第三ILD層)填入凹槽中的量較少，因此可能增加氣隙體積。
應理解的是，上述內容不必提及所有的優點，所有實施例或實例不需包含特定優點，且其他實施例或實例可具有不同優點。
在本揭露一實施例中，半導體裝置的形成方法包括：形成第一介電層於基板上。形成多個第一凹陷於第一介電層中。形成多個金屬線路於第一凹陷中。金屬線路沿著第一方向延伸。形成遮罩層於金屬線路與第一介電層上。遮罩層包括沿著第一方向延伸的第一開口，且第一開口位於兩個相鄰的金屬線路之間的空間上。以遮罩層作為蝕刻遮罩，蝕刻第一介電層以形成第一凹槽對應金屬線路之間的第一開口。形成第二介電層，以形成第一氣隙於第一凹槽中。第一開口於第二方向的寬度小於兩個相鄰的金屬線路於第二方向的間距，且第二方向垂直於第一方向。
在本揭露另一實施例中，半導體裝置的形成方法包括：形成第一介電層於基板上。形成多個第一凹陷於第一介電層中。形成多個金屬線路於第一凹陷中。金屬線路沿著一第一方向延伸。形成第一絕緣層於金屬線路與第一介電層上。形成第一遮罩圖案於第一絕緣層上。第一遮罩圖案包含沿著第一方向延伸的第一開口，且第一開口於第二方向具有寬度。第二 方向垂直於第一方向。縮減第一開口的寬度以形成第二遮罩圖案，第二遮罩圖案具有第二開口，且第二開口的寬度小於第一開口。以第二遮罩圖案作為蝕刻遮罩，圖案化該第一絕緣層以形成第三開口於第一絕緣層中，且第三開口對應第二開口。經由第三開口蝕刻第一介電層，以形成第一凹槽對應兩個相鄰的金屬線路之間的第三開口。形成第二介電層以形成第一氣隙於第一凹槽中。第三開口於第二方向的寬度，小於兩個相鄰之金屬線路於第二方向的間距。
在本揭露又一實施例中，半導體裝置包括第一介電層位於基板上、多個金屬線路、第二介電層、絕緣層、以及氣隙。金屬線路埋置於第一介電層中，且沿著第一方向延伸一第二介電層位於第一介電層與金屬線路上。第一絕緣層，位於第一介電層與第二介電層之間。氣隙形成於兩個相鄰的金屬線路之間。絕緣層完全覆蓋兩個相鄰的金屬線路的上表面，使金屬線路的上表面不接觸第二介電層，絕緣層懸吊於兩個相鄰的該些金屬線路之間的空間上。
上述實施例或實例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露之精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
TR‧‧‧梯形區域
10‧‧‧第一ILD層
20‧‧‧下層的ESL
30‧‧‧下層的蓋層
50‧‧‧第二ILD層
56、58‧‧‧氣隙
90‧‧‧阻障層
100、106‧‧‧金屬線路
150‧‧‧第三ILD層
200‧‧‧第一ESL
240‧‧‧第二ESL
260‧‧‧蓋層

Claims (10)

  1. 一種半導體裝置的形成方法，包括：形成一第一介電層於一基板上；形成多個第一凹陷於該第一介電層中；形成多個金屬線路於該些第一凹陷中，且該些金屬線路沿著一第一方向延伸；形成一遮罩層於該些金屬線路與該第一介電層上，該遮罩層包括沿著該第一方向延伸的一第一開口，且該第一開口位於兩個相鄰的該些金屬線路之間的空間上；以該遮罩層作為一蝕刻遮罩，蝕刻該第一介電層以形成一第一凹槽對應兩個相鄰的該些金屬線路之間的該第一開口；以及形成一第二介電層以形成一第一氣隙於該第一凹槽中；其中該第一開口於一第二方向的寬度小於兩個相鄰的該些金屬線路於該第二方向的間距，且該第二方向垂直於該第一方向。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該第一凹槽之步驟後，該遮罩層覆蓋且未露出兩個相鄰的該些金屬線路之上表面，且該遮罩層懸吊於該第一凹槽上。
  3. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該第二介電層包括兩個或更多的介電層，且該些介電層中的一或兩者順應性地形成於該第一凹槽中。
  4. 一種半導體裝置的形成方法，包括： 形成一第一介電層於一基板上；形成多個第一凹陷於該第一介電層中；形成多個金屬線路於該些第一凹陷中，且該些金屬線路沿著一第一方向延伸；形成一第一絕緣層於該些金屬線路與該第一介電層上；形成一第一遮罩圖案於該第一絕緣層上，該第一遮罩圖案包含沿著該第一方向延伸的一第一開口，該第一開口於一第二方向具有一寬度，且該第二方向垂直於該第一方向；縮減該第一開口的寬度以形成一第二遮罩圖案，該第二遮罩圖案具有一第二開口，且該第二開口的寬度小於該第一開口；以該第二遮罩圖案作為一蝕刻遮罩，圖案化該第一絕緣層以形成一第三開口於該第一絕緣層中，且該第三開口對應該第二開口；經由該第三開口蝕刻該第一介電層，以形成一第一凹槽對應兩個相鄰的該些金屬線路之間的該第三開口；以及形成一第二介電層以形成一第一氣隙於該第一凹槽中；其中該第三開口於該第二方向的寬度，小於兩個相鄰之該些金屬線路於該第二方向的間距。
  5. 如申請專利範圍第4項所述之半導體裝置的形成方法，其中該第一開口的寬度大於或等於兩個相鄰的該些金屬線路之間距。
  6. 如申請專利範圍第4項所述之半導體裝置的形成方法，其中形成該第一凹槽之步驟後，該第一絕緣層覆蓋且未露出兩 個相鄰的該些金屬線路之上表面，且該第一絕緣層懸吊於該第一凹槽上。
  7. 如申請專利範圍第4項所述之半導體裝置的形成方法，其中：該第二介電層包括一第一蝕刻停止層、一蓋層、與一層間介電層；該第一蝕刻停止層順應性地形成於該第一凹槽中；該蓋層順應性地形成於該第一蝕刻停止層上；以及該層間介電層未覆蓋該第一凹槽中的部份該蓋層。
  8. 一種半導體裝置，包括：一第一介電層，位於一基板上；多個金屬線路埋置於該第一介電層中，且該些金屬線路沿著一第一方向延伸；一第二介電層，位於該第一介電層與該些金屬線路上；一絕緣層，位於該第一介電層與該第二介電層之間；以及一氣隙，形成於兩個相鄰的該些金屬線路之間；其中該絕緣層完全覆蓋兩個相鄰的該些金屬線路的上表面，使該些金屬線路的上表面不接觸該第二介電層；以及該絕緣層懸吊於兩個相鄰的該些金屬線路之間的空間上。
  9. 如申請專利範圍第8項所述之半導體裝置，其中：該絕緣層包括一開口位於兩個相鄰的該些金屬線路之間的空間上；以及該開口於一第二方向的寬度小於兩個相鄰的該些金屬線路於該第二方向的間距，且該第二方向垂直於該第一方向。
  10. 如申請專利範圍第8項所述之半導體裝置，其中：一凹槽形成於兩個相鄰的該些金屬線路之間的空間中；該第二介電層包括一第一蝕刻停止層、一蓋層、以及一層間介電層；該第一蝕刻停止層順應性地形成於該凹槽中；該蓋層順應性地形成於該第一蝕刻停止層上，以定義該氣隙的側部與底部；以及該層間介電層未覆蓋該凹槽中的部份該蓋層。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI832862B (zh) * 2019-05-28 2024-02-21 聯華電子股份有限公司 內連線結構及其製造方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653348B1 (en) * 2015-12-30 2017-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US20170365504A1 (en) * 2016-06-20 2017-12-21 Globalfoundries Inc. Forming air gap
CN111052345A (zh) * 2017-09-30 2020-04-21 英特尔公司 导电过孔及金属线端制造及由其所得的结构
CN111602236A (zh) * 2018-01-11 2020-08-28 索尼半导体解决方案公司 半导体装置、其制造方法和电子设备
US10658179B2 (en) * 2018-08-17 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure of middle layer removal
CN110858562B (zh) * 2018-08-23 2023-07-11 联华电子股份有限公司 半导体元件制造方法及其制得的半导体元件
KR102661963B1 (ko) * 2018-09-28 2024-04-30 삼성전자주식회사 반도체 소자 및 반도체 소자 제조 방법
JP7431746B2 (ja) * 2018-10-31 2024-02-15 浜松ホトニクス株式会社 ダマシン配線構造、アクチュエータ装置、及びダマシン配線構造の製造方法
KR102244811B1 (ko) 2018-12-17 2021-04-27 주식회사 이엠따블유 Rf 필터의 공진기
US10818541B2 (en) * 2018-12-27 2020-10-27 Nanya Technology Corporation Semiconductor structure
US10707119B1 (en) * 2019-01-14 2020-07-07 Globalfoundries Inc. Interconnect structures with airgaps and dielectric-capped interconnects
US11164773B2 (en) * 2019-09-23 2021-11-02 Nanya Technology Corporation Method for forming semiconductor device structure with air gap
US11127678B2 (en) * 2019-12-10 2021-09-21 Globalfoundries U.S. Inc. Dual dielectric layer for closing seam in air gap structure
CN113223997A (zh) * 2020-01-21 2021-08-06 夏泰鑫半导体(青岛)有限公司 半导体元器件及其制备方法及电子装置
US10991651B1 (en) * 2020-03-03 2021-04-27 Nanya Technology Corporation Interconnection structure having reduced capacitance and method of manufacturing the same
CN113948401A (zh) * 2020-07-16 2022-01-18 长鑫存储技术有限公司 半导体结构及其形成方法
WO2023028843A1 (zh) * 2021-08-31 2023-03-09 长江存储科技有限责任公司 半导体结构及其制备方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319743B1 (ko) * 1998-11-24 2002-05-09 오길록 기생 캐패시턴스 및 자장의 간섭을 감소시킬 수 있는 집적소자및 그 제조 방법
US6159840A (en) * 1999-11-12 2000-12-12 United Semiconductor Corp. Fabrication method for a dual damascene comprising an air-gap
US6423630B1 (en) * 2000-10-31 2002-07-23 Lsi Logic Corporation Process for forming low K dielectric material between metal lines
US6406992B1 (en) * 2001-05-29 2002-06-18 United Microelectronics Corp. Fabrication method for a dual damascene structure
US20030213617A1 (en) * 2002-05-20 2003-11-20 Subramanian Karthikeyan Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device
US6949456B2 (en) * 2002-10-31 2005-09-27 Asm Japan K.K. Method for manufacturing semiconductor device having porous structure with air-gaps
JP2004214594A (ja) * 2002-11-15 2004-07-29 Sharp Corp 半導体装置およびその製造方法
US7138329B2 (en) * 2002-11-15 2006-11-21 United Microelectronics Corporation Air gap for tungsten/aluminum plug applications
CN100372113C (zh) * 2002-11-15 2008-02-27 联华电子股份有限公司 一种具有空气间隔的集成电路结构及其制作方法
KR100505062B1 (ko) * 2003-02-22 2005-07-29 삼성전자주식회사 반도체 소자의 제조방법
JP4102246B2 (ja) * 2003-04-28 2008-06-18 株式会社東芝 半導体装置及びその製造方法
JP4106048B2 (ja) 2004-10-25 2008-06-25 松下電器産業株式会社 半導体装置の製造方法及び半導体装置
US20090001594A1 (en) * 2007-06-29 2009-01-01 Hui Jae Yoo Airgap interconnect system
US7566627B2 (en) * 2007-06-29 2009-07-28 Texas Instruments Incorporated Air gap in integrated circuit inductor fabrication
US20090072409A1 (en) * 2007-09-14 2009-03-19 International Business Machines Corporation Interconnect Structures Incorporating Air-Gap Spacers
US7879683B2 (en) * 2007-10-09 2011-02-01 Applied Materials, Inc. Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
US7964442B2 (en) * 2007-10-09 2011-06-21 Applied Materials, Inc. Methods to obtain low k dielectric barrier with superior etch resistivity
US20090093100A1 (en) * 2007-10-09 2009-04-09 Li-Qun Xia Method for forming an air gap in multilevel interconnect structure
US7772706B2 (en) * 2007-12-27 2010-08-10 Intel Corporation Air-gap ILD with unlanded vias
US7943480B2 (en) 2008-02-12 2011-05-17 International Business Machines Corporation Sub-lithographic dimensioned air gap formation and related structure
US7754601B2 (en) 2008-06-03 2010-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnect air gap formation process
US7915158B2 (en) * 2008-06-23 2011-03-29 International Business Machines Corporation Method for forming an on-chip high frequency electro-static discharge device
DE102008059499A1 (de) * 2008-11-28 2010-07-01 Advanced Micro Devices, Inc., Sunnyvale Mikrostrukturbauelement mit einer Metallisierungsstruktur mit Luftspalten, die zusammen mit Kontaktdurchführungen hergestellt sind
DE102009023377B4 (de) * 2009-05-29 2017-12-28 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung eines Mikrostrukturbauelements mit einer Metallisierungsstruktur mit selbstjustiertem Luftspalt
US8120179B2 (en) 2009-11-10 2012-02-21 International Business Machines Corporation Air gap interconnect structures and methods for forming the same
JP2012009490A (ja) * 2010-06-22 2012-01-12 Toshiba Corp 半導体装置およびその製造方法
US8519482B2 (en) * 2011-09-28 2013-08-27 Globalfoundries Singapore Pte. Ltd. Reliable contacts
JP5898991B2 (ja) * 2012-02-10 2016-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
TW201338092A (zh) 2012-03-08 2013-09-16 Rexchip Electronics Corp 半導體之氣隙的形成方法
KR20130137393A (ko) 2012-06-07 2013-12-17 에스케이하이닉스 주식회사 에어갭 캡핑을 위한 스페이서를 갖는 반도체 장치 및 그 제조 방법
CN103474388B (zh) * 2012-06-08 2015-12-16 中芯国际集成电路制造(上海)有限公司 沟槽间形成空气间隔的方法
US9490163B2 (en) * 2012-08-31 2016-11-08 Taiwan Semiconductor Manufacturing Company Limited Tapered sidewall conductive lines and formation thereof
US9274920B2 (en) 2012-09-28 2016-03-01 Dialog Semiconductor B.V. Code profiling in embedded ULE applications
JP5932604B2 (ja) * 2012-10-24 2016-06-08 株式会社東芝 半導体装置及びその製造方法
TWI508188B (zh) 2012-10-25 2015-11-11 Macronix Int Co Ltd 氣隙結構與其製造方法
KR20140086645A (ko) 2012-12-28 2014-07-08 에스케이하이닉스 주식회사 자기정렬된 에어갭을 구비한 반도체장치 및 그 제조 방법
US9312220B2 (en) * 2013-03-12 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a low-K dielectric with pillar-type air-gaps
US9401329B2 (en) * 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming the same
KR102044275B1 (ko) 2013-07-31 2019-11-14 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US9099465B2 (en) * 2013-10-14 2015-08-04 Stmicroelectronics, Inc. High aspect ratio vias for high performance devices
KR102092863B1 (ko) * 2013-12-30 2020-03-24 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102247918B1 (ko) * 2014-04-07 2021-05-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9659856B2 (en) * 2014-10-24 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Two step metallization formation
US9431294B2 (en) * 2014-10-28 2016-08-30 GlobalFoundries, Inc. Methods of producing integrated circuits with an air gap
US9536842B2 (en) * 2014-12-18 2017-01-03 GlobalFoundries, Inc. Structure with air gap crack stop
US9496169B2 (en) * 2015-02-12 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming an interconnect structure having an air gap and structure thereof
US9653348B1 (en) * 2015-12-30 2017-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI832862B (zh) * 2019-05-28 2024-02-21 聯華電子股份有限公司 內連線結構及其製造方法

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US10879179B2 (en) 2020-12-29
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