TWI622144B - 指紋感測器裝置及其製造方法 - Google Patents

指紋感測器裝置及其製造方法 Download PDF

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Publication number
TWI622144B
TWI622144B TW105140131A TW105140131A TWI622144B TW I622144 B TWI622144 B TW I622144B TW 105140131 A TW105140131 A TW 105140131A TW 105140131 A TW105140131 A TW 105140131A TW I622144 B TWI622144 B TW I622144B
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Taiwan
Prior art keywords
substrate
sensor
layer
fingerprint sensor
chip
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TW105140131A
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English (en)
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TW201731051A (zh
Inventor
余振華
Chen-Hua Yu
陳玉芬
Yu-Feng Chen
陳志華
Chih-Hua Chen
蔡豪益
Hao-Yi Tsai
劉重希
Chung-Shi Liu
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Company Ltd.
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Publication of TW201731051A publication Critical patent/TW201731051A/zh
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
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    • G06V40/13—Sensors therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns

Abstract

本揭露係提供一種指紋感測器封裝件及其製造方法。該指紋感測器封裝件包含一指紋感測器，連同一指紋感測器材料；以及電連接，從該指紋感測器的一第一側至該指紋感測器的一第二側。一高電壓晶片係連接至該指紋感測器且接著該指紋感測器封裝件與該高電壓晶片係連接至一基板，其中該基板具有一開口，以容納該高電壓晶片的存在。

Description

指紋感測器裝置及其製造方法
本發明實施例係關於一種指紋感測器裝置及其製造方法。
由於使用者裝置變得更小且更便於攜帶，讓有不軌企圖的人變得更容易竊取使用者裝置。當此等裝置攜帶使用者的敏感資料，除非已有放置阻障到使用者裝置中，否則竊賊可能能夠存取這些資料。一旦此種阻障係指紋感測器，其可用以讀取試圖存取裝置者之指紋，若該指紋與使用者的指紋不相同，存取可能被拒絕。 然而，由於使用者裝置諸如手機變得更小，對於在使用者裝置內之個別組件之各者上也同時看到大小減小有壓力。因此，對於減少含有指紋感測器之指紋封裝件的大小但沒有看到性能減少而言有壓力。因此，需要改善以看到想要的大小減少。
根據一實施例，提供一種製造一指紋掃描器之方法，包含附接一指紋感測器表面材料在一指紋感測器上方。該指紋感測器包含一半導體基板；及一電極陣列，在該半導體基板與該指紋感測器表面材料之間。係附接一高電壓晶片與該指紋感測器電連接，其中該高電壓晶片係位在與該指紋感測器表面材料相比之該指紋感測器的一相對側上。係附接該指紋感測器至一基板，其中在該附接該指紋感測器至該基板之後，該高電壓晶片係位在該基板的一開口內。 根據另一實施例，提供一種製造一指紋掃描器之方法，該方法包含形成貫穿通路貫穿一指紋感測器基板。係形成一電極陣列在該指紋感測器基板上方，其中該電極陣列係與在該指紋感測器基板的一第一側上的主動裝置電連接，以及係附接一指紋感測器外蓋在該指紋感測器基板的該第一側上方。係附接一高電壓晶片與該主動裝置電連接，其中該高電壓晶片係位在與該電極陣列相比之該指紋感測器基板的一相對側上，及係放置該高電壓晶片至位在一第二基板內的一開口中。 根據又一實施例，提供一種半導體裝置，包含一指紋感測器。貫穿通路，電連接該指紋感測器的一第一側與位在該指紋感測器的一第二側上的一導電元件，該第二側與該第一側相對。一高電壓晶片，與該貫穿通路電連接；及一基板，與該貫穿通路電連接，其中該高電壓晶片係位在該基板的一開口內。
下列揭露提供許多用於實施本發明之不同特徵的不同實施例、或實例。為了簡化本揭露，於下描述組件及配置的具體實例。當然這些僅為實例而非意圖為限制性。例如，在下面說明中，形成第一特徵在第二特徵上方或上可包括其中第一及第二特徵係經形成為直接接觸之實施例，以及也可包括其中額外特徵可形成在第一與第二特徵之間而使得第一及第二特徵不可直接接觸之實施例。此外，本揭露可重複參考編號及/或字母於各種實例中。此重複係為了簡單與清楚之目的且其本身並不決定所討論的各種實施例及/或構形之間的關係。 再者，空間相關詞彙，諸如“在...之下”、“下面”、“下”、“上面”、“上”和類似詞彙，可為了使說明書便於描述如圖式繪示的一個元件或特徵與另一個（或多個）元件或特徵的相對關係而使用於本文中。除了圖式中所畫的方位外，這些空間相對詞彙也意圖用來涵蓋裝置在使用中或操作時的不同方位。該設備可以其他方式定向(旋轉90度或於其它方位)，據此在本文中所使用的這些空間相關說明符可以類似方式加以解釋。 實施例現將關於在封裝件中系統(system in package，SiP)解決方案中，不然在積體扇出結構(integrated fan out，InFO)中之指紋感測器描述。然而，實施例可使用在任何合適的封裝件中。 現請參照圖1A，繪示有利用載體基板101、黏著層103、聚合物層105、第一重佈線層107、第一貫穿基板通路(through substrate via，TSV)109、及指紋感測器104的實施例。在一實施例中，載體基板101包含，例如矽系材料，諸如玻璃或氧化矽；或其它材料，諸如氧化鋁；這些材料之任一者的組合；或類似物。為了容置裝置諸如指紋感測器104的附接，載體基板101係平坦。 為了協助附接上覆結構至載體基板101，黏著層103可放置在載體基板101上方。在一實施例中，黏著層103係晶粒附接膜(die attached film，DAF)，諸如環氧樹脂、酚樹脂、丙烯酸系橡膠、二氧化矽填料、或其組合，且係使用層壓技術施加。然而，可利用任何其它合適之形成材料及方法。 聚合物層105係初始形成在黏著層103上方。在一實施例中，聚合物層105可由一或多個合適的介電材料所製，諸如氧化矽、氮化矽、低k介電質諸如碳摻雜氧化物、極低k介電質諸如多孔碳摻雜二氧化矽、這些的組合、或類似物。聚合物層105可透過製程諸如化學氣相沉積(chemical vapor deposition，CVD)形成，雖然可利用任何合適的製程，且可具有厚度在約0.5 μm與約5 μm之間，諸如約9.25 KÅ。 一旦聚合物層105已形成，凸塊下金屬化層137及第一重佈線層107可形成在聚合物層105上方。在一實施例中，凸塊下金屬化層137可包含三層導電材料，諸如一層鈦、一層銅、及一層鎳。然而，本技術領域中具有通常知識者將認知到，有許多合適的材料及層的配置，諸如適合凸塊下金屬化層137形成的鉻/鉻-銅合金/銅/金配置、鈦/鈦鎢/銅配置、或銅/鎳/金配置。可用於凸塊下金屬化層137之任何合適的材料或材料層係意圖完全包括在實施例的範疇內。 在一實施例中，凸塊下金屬化層137係藉由形成各層在聚合物層105上方而產生。各層之形成可使用鍍覆製程實施，諸如電化學電鍍，雖然取決於想要的材料可替代地使用其它形成製程，諸如濺鍍、蒸發、或電漿增強型化學氣相沉積(plasma-enhanced CVD，PECVD)製程。凸塊下金屬化層137可被形成以具有厚度在約0.7 µm與約10 µm之間，諸如約5 µm。 在一實施例中，第一重佈線層107包含埋置在一系列介電層135(諸如三個介電層)內的一系列導電層133(諸如兩個導電層)。在一實施例中，一系列介電層135之第一者係形成在聚合物層105上方，且一系列介電層135之第一者可以是材料諸如聚苯并噁唑(polybenzoxazole，PBO)，雖然可利用任何合適的材料，諸如聚醯亞胺或聚醯亞胺衍生物。一系列介電層135之第一者可使用如旋轉塗佈製程放置，雖然可使用任何合適的方法。 在一系列介電層135之第一者已形成之後，可藉由移除一系列介電層135之第一者的部分製作開口通過一系列介電層135之第一者。開口可使用合適的光微影遮罩及蝕刻製程形成，雖然任何合適的一或多個製程可用以圖案化一系列介電層135之第一者。 一旦一系列介電層135之第一者已形成且圖案化之後，一系列導電層133之第一者係形成在一系列介電層135之第一者上方且通過形成在一系列介電層135之第一者內的開口。在一實施例中，一系列導電層133之第一者可藉由下列形成，透過合適的形成製程諸如CVD或濺鍍初始形成鈦銅合金之晶種層(未顯示)。接著可形成光阻(也未顯示)，以覆蓋晶種層，且接著可圖案化光阻以暴露位在一系列導電層133之第一者想要坐落處之晶種層的那些部分。 一旦光阻已形成且圖案化，導電材料諸如銅可透過沉積製程諸如鍍覆形成在晶種層上。導電材料可被形成以具有厚度在約1 µm與約10 µm之間，諸如約5 µm。然而，在所討論材料及方法係適於形成導電材料之際，這些材料僅為例示性。任何其它合適的材料諸如AlCu或Au，及任何其它合適的形成製程諸如CVD或物理氣相沉積(physical vapor deposition，PVD)可用以形成一系列導電層133之第一者。一旦導電材料已形成，光阻可透過合適的移除製程諸如灰化移除。另外，在光阻之移除之後，被光阻覆蓋之晶種層的那些部分可透過例如，使用導電材料作為遮罩之合適的蝕刻製程移除。 一旦一系列導電層133之第一者已形成，一系列介電層135之第二者及一系列導電層133之第二者可藉由重複與一系列介電層135之第一者及一系列導電層133之第一者相似之步驟形成。為了將一系列導電層133之各者電連接至一系列導電層133之下方者，這些步驟可依想要者重複，且可依想要者經常重複直到一系列導電層133之最上者及一系列介電層131之最上者已形成。在一實施例中，可持續一系列導電層133及一系列介電層135的沉積及圖案化直到第一重佈線層107具有想要數目的層，諸如兩個層，雖然可利用任何合適數目的個別層。 一旦第一重佈線層107已形成在載體基板101上方，係形成第一TSV 109與第一重佈線層107電連接。在一實施例中，第一TSV 109可藉由下列形成，起始形成晶種層(未分開繪示在圖1A中)。在一實施例中，晶種層係薄層導電材料，其有助於後續加工步驟期間較厚層之形成。晶種層可包含約1,000 Å厚的一層鈦接著約5,000 Å厚的一層銅。取決於想要的材料，晶種層可使用製程諸如濺鍍、蒸發、或PECVD製程產生。晶種層可被形成以具有厚度在約0.3 µm與約1 µm之間，諸如約0.5 µm。 一旦晶種層已形成，光阻(也未繪示在圖1A中)係放置在晶種層上方。在一實施例中，光阻可使用如旋轉塗佈技術放置在晶種層上，至高度在約50 µm與約250 µm之間，諸如約120 µm。一旦就位，光阻接著可藉由使光阻暴露於經圖案化能量源(如，經圖案化光源)以便引起化學反應，進而在曝光於經圖案化光源之光阻的那些部分中引起物理變化而圖案化。顯影劑接著係施加至曝光之光阻以利用物理變化並取決於想要的圖案選擇性移除光阻之曝光部分或光阻之未曝光部分。在一實施例中，形成至光阻中的圖案係用於第一TSV 109的圖案。第一TSV 109係以這樣的布局形成而位在後續附接裝置諸如指紋感測器104的不同側。然而，可利用任何合適之用於第一TSV 109的圖案的配置。 在一實施例中，第一TSV 109係從一或多個導電材料形成在光阻內，諸如銅、鎢、其它導電金屬、或類似物，且可藉由例如電鍍、無電式電鍍、或類似物形成。例如，係使用電鍍製程，其中晶種層及光阻係浸入或浸沒在電鍍溶液中。晶種層表面係電連接至外部直流電(direct current，DC)電源的負極側而使得晶種層在電鍍製程中作為陰極。固體導電陽極，諸如銅陽極係也浸沒在溶液中且係附接至電源的正極側。來自陽極的原子係溶解至溶液中，陰極如晶種層係從該溶液中獲取溶解之原子，進而鍍覆在光阻的開口內之晶種層之暴露的導電區。 一旦第一TSV 109已使用光阻及晶種層形成，光阻可使用合適的移除製程移除。在一實施例中，電漿灰化製程可用以移除光阻，藉此光阻的溫度可被增加直到光阻經驗熱分解且可被移除。然而，可利用任何其它合適的製程，諸如濕剝除。光阻的移除可暴露晶種層的下方部分。 一旦暴露，可實施晶種層之暴露的部分的移除。在一實施例中，晶種層之暴露的部分(如，未被第一TSV 109覆蓋的那些部分)可藉由，例如濕或乾蝕刻製程移除。例如，在乾蝕刻製程中，可使用第一TSV 109作為遮罩將反應物導向晶種層。在另一實施例中，為了移除晶種層之暴露的部分，蝕刻劑可被噴灑或以其他方式使之接觸晶種層。在晶種層之暴露的部分已蝕刻掉之後，第一重佈線層107的一部分係暴露在第一TSV 109之間。 一旦第一TSV 109已形成，指紋感測器104可放置在第一重佈線層107上。在一實施例中，指紋感測器104包含具有前側113及背側115之半導體基板111，及位在相鄰於前側113之電極陣列120。在一實施例中，半導體基板111可包含經摻雜或未經摻雜之主體矽、或絕緣體上矽(silicon-on-insulator，SOI)基板的主動層。一般，SOI基板包含一層半導體材料，諸如矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)、或其組合。可使用之其它基板包括多層基板、梯度基板、或雜合方位向基板。 另外，在未分開繪示在圖1A中之際，為了控制及接收來自電極陣列120的訊號輸入不然為了以其他方式控制指紋感測器104的功能性及最終輸出，指紋感測器104也可包含主動裝置及金屬化層。在一實施例中，指紋感測器104的主動裝置包含廣泛種類的主動裝置及被動裝置諸如電容器、電阻器、電感及類似物，其可用以產生用於指紋感測器104設計之想要的結構及功能要求。主動裝置可使用任何合適的方法形成在半導體基板111內不然在半導體基板111上。 金屬化層係形成在半導體基板111及指紋感測器104的主動裝置上方且係設計用以連接各種主動裝置以形成功能電路。在一實施例中，金屬化層係由介電及導電材料之交替層所形成且可透過任何合適的製程(諸如沉積、鑲嵌、雙鑲嵌、等)形成。在一實施例中，可能有四個金屬化層，其與第二半導體基板被至少一個層間介電層(interlayer dielectric layer，ILD)分開，但金屬化層的精確數目係取決於指紋感測器104的設計。 為了測量指紋，電極陣列120係電連接至指紋感測器104的金屬化層且係用以測量在上覆手指的不同區之間的差異。在一實施例中，電極陣列120包含導電材料諸如鋁或銅，且係使用如沉積及圖案化製程形成，藉此導電材料的整片層係使用製程諸如CVD、PVD、原子層沉積(atomic layer deposition，ALD)、或類似物沉積，且導電材料的整片層係接著使用光微影遮罩及蝕刻製程圖案化。然而，可利用任何合適之製造的材料或方法以形成電極陣列120。 另外，在已藉使用整片沉積接著後續圖案化及保護描述電極陣列120之形成之際，此製程僅意圖為例示而不是意圖為限制性。反而是，也可使用任何合適之製造電極陣列120的製程，諸如使用鑲嵌或雙鑲嵌製程。所有此等製程係意圖完全包括在實施例的範疇內。 接觸墊119係被形成以提供電連接至後續形成之第二重佈線層121(未繪示在圖1A中但於下面係關於圖1B繪示並描述)。在一實施例中，接觸墊119係由導電材料諸如鋁所形成，雖然可利用其它合適的材料，諸如銅、鎢、或類似物。接觸墊119可使用製程諸如CVD或PVD形成，雖然可利用其它合適的材料及方法。一旦用於接觸墊119的材料已沉積，可使用如光微影遮罩及蝕刻製程將材料塑形成接觸墊119。 一旦接觸墊119已形成，可放置及圖案化第一保護層122。在一實施例中，第一保護層122可以是保護材料，諸如聚苯并噁唑(PBO)、或聚醯亞胺(polyimide，PI)、氧化矽、氮化矽、氧氮化矽、苯并環丁烷(benzocyclobutene，BCB)、或任何其它合適的保護材料。第一保護層122可基於所選材料使用方法，諸如旋塗製程、沉積製程(如，化學氣相沉積)、或其它合適的製程形成，且可被形成以具有厚度在約1 µm與約100 µm之間，諸如約20 µm。 一旦形成，第一保護層122被圖案化以形成開口並暴露接觸墊119。在一實施例中，第一保護層122可使用如光微影遮罩及蝕刻製程圖案化。在此等製程中，光阻(未個別繪示在圖1B中)係施加至第一保護層122且接著曝光於經圖案化光源。光源將撞擊在光阻上並引起光阻極性的改變，該改變接著被利用以選擇性地移除曝光部分或未曝光部分並暴露第一保護層122。接著係利用光阻作為在如蝕刻製程期間之遮罩，該蝕刻製程移除第一保護層122的部分以暴露接觸墊119。一旦第一保護層122已圖案化，光阻可使用如灰化製程移除。 在另一實施例中，為了暴露接觸墊119，可薄化第一保護層122。在此實施例中，可利用平坦化製程諸如化學機械拋光製程，藉此化學品及研磨劑係施加至第一保護層122而拋光墊研磨掉材料，以移除從在接觸墊119上方之第一保護層122的材料，進而暴露接觸墊119而也與接觸墊119一起平坦化第一保護層122。可使用任何合適之形成接觸墊119及第一保護層122的方法。 指紋感測器104係使用如第二黏著層112放置在第一重佈線層107上且在第一TSV 109之間。在一實施例中，第二黏著層112可以是與黏著層103相似之材料並以相似之方式施加，雖然可使用任何合適的材料。指紋感測器104係面朝上放置而使得前側113背對載體基板101。另外，接觸墊119係連接至電極陣列120及在指紋感測器104的前側113上之指紋感測器104的金屬化層。 圖1B繪示以囊封劑125將指紋感測器104及第一TSV 109囊封。在一實施例中，囊封劑125可以是模塑料且可使用成型裝置(未繪示在圖1B中)放置。例如，指紋感測器104可放置在成型裝置的空腔內且空腔可以是氣密密封。囊封劑125可在空腔氣密密封之前放置在空腔內不然可透過注入口注入到空腔中。在一實施例中，囊封劑125可以是模塑料樹脂，諸如聚醯亞胺、聚苯硫醚(polyphenylene sulfide，PPS)、聚醚醚酮(polyether ether ketone，PEEK)、聚醚碸(Polyethersulfone，PES)、抗熱結晶樹脂、這些的組合、或類似物。 一旦囊封劑125已放置到空腔中而使得囊封劑125囊封圍繞指紋感測器104及第一TSV 109之區域，為了硬化囊封劑125以供最佳保護，囊封劑125可被固化。在確切固化製程係至少部分取決於為囊封劑125所選之具體材料之際，在其中模塑料係選作囊封劑125的一實施例中，固化可透過製程諸如加熱囊封劑125至在約100 ºC與約130 ºC之間諸如約125 ºC歷時約60秒至約3000秒諸如600秒發生。另外，起始劑及/或催化劑可包括在囊封劑125內以更佳固化製程。 然而，技術領域中具有通常知識者將認知到上述固化製程僅為例示性製程且不意味限制當前實施例。可使用其它固化製程，諸如輻射或甚至允許囊封劑125在環境溫度硬化。可使用任何合適的固化製程，且所有此等製程係意圖完全包括在本文所討論實施例的範疇內。 圖1B另外繪示為了暴露指紋感測器104的接觸墊119之囊封劑125的薄化。在一實施例中，可實施薄化，如使用機械研磨或化學機械研磨(CMP)製程，藉此利用蝕刻劑及研磨劑來反應並研磨掉囊封劑125。可薄化囊封劑125直到接觸墊119暴露。 然而，在上述CMP製程係以一個說明性實施例呈現之際，其不意圖限制實施例。可使用任何其它合適的移除製程以囊封指紋感測器104同時暴露接觸墊119。例如，可利用化學蝕刻或一系列化學蝕刻，或可利用不會覆蓋接觸墊119之囊封製程。可利用這些製程及任何其它合適的製程以施加囊封劑125，且所有此等製程係意圖完全包括在本文所討論實施例的範疇內。 圖1B也繪示為了電互連第一TSV 109與指紋感測器104的接觸墊119之第二重佈線層121的形成。在一實施例中，第二重佈線層121可以是與上面關於圖1A描述之第一重佈線層107相似。在一具體實施例中，可能有一系列導電層133之單一者被夾在一系列介電層135之兩者之間。然而，可利用導電層與介電層之任何合適的組合以互連指紋感測器104的接觸墊119與第一TSV 109。 一旦第二重佈線層121已形成，感測器表面材料123可使用如介面層136，諸如膠層或色膜層附接至第二重佈線層121。在一實施例中，感測器表面材料123可藉由下列附接：初始施加介面層136至第二重佈線層121及接著施加感測器表面材料123至介面層136。介面層136可以是與上面關於圖1A描述之黏著層103相似，雖然可使用任何合適的材料。 在一實施例中，感測器表面材料123係材料諸如藍寶石或玻璃，其允許指紋感測器104與上覆手指之間的電容式改變的測量以判定手指上指紋的輪廓。在一實施例中，感測器表面材料123可使用物理放置製程放置。另外，感測器表面材料123可具有第一厚度T1 在約50 µm與約1000 µm之間，諸如約100 µm。然而，可利用任何合適的材料及厚度。 在其中介面層136係色膜層之另一實施例中，可省略感測器表面材料。例如，在一具體實施例中，介面層136可藉其本身放置在第二重佈線層121上方，而不需要接著放置感測器表面材料至介面層136上。可利用任何合適的材料組合。 圖1C繪示為了暴露凸塊下金屬化層137之載體基板101的去接合及聚合物層105的圖案化。在一實施例中，載體基板101可藉由初始接合感測器表面材料123至如環結構152而去接合。環結構152可以是意圖在去接合製程期間及之後為結構提供支撐及安定性之金屬環。在一實施例中，感測器表面材料123可使用如紫外光膠帶154附接至環結構152，雖然可使用任何其它合適的黏著劑或附接。 一旦附接，載體基板101可使用如熱製程以改變黏著層103的黏著劑性質而從結構去接合。在一具體實施例中，係利用能量源諸如紫外光(ultraviolet，UV)雷射；二氧化碳(CO2)雷射、或紅外光(infrared，IR)雷射以輻射並加熱黏著層103直到黏著層103喪失至少一些它的黏著劑性質。一旦實施，載體基板101及黏著層103可從包含指紋感測器104及感測器表面材料123之結構實體分開並移除。 一旦去接合，為了暴露下方凸塊下金屬化層137，係圖案化聚合物層105。在一實施例中，聚合物層105可使用如雷射鑽孔方法圖案化。在此一方法中，保護層諸如光熱轉換(light-to-heat conversion，LTHC)層或水溶性保護膜(hogomax)層(未分開繪示在圖1C中)係先沉積在聚合物層105上方。一旦被保護，為了暴露下方凸塊下金屬化層137，將雷射導向想要被移除之聚合物層105的那些部分。在雷射鑽孔製程期間，鑽孔能量可以是在自0.1 mJ至約30 mJ之範圍中，且鑽孔與聚合物層105的法線夾角係約0度(垂直於聚合物層105)至約85度。在一實施例中，圖案化可被形成以在凸塊下金屬化層137上方形成開口，以具有寬度在約100 µm與300 µm約之間，諸如200 µm。 在另一實施例中，聚合物層105可藉由下列圖案化：初始施加光阻(未個別繪示在圖1C中)至聚合物層105及接著使光阻暴露於經圖案化能量源(如，經圖案化光源)以便引起化學反應，進而在曝光於經圖案化光源之光阻的那些部分中引起物理變化。顯影劑接著係施加至曝光之光阻以利用物理變化並取決於想要的圖案選擇性移除光阻之曝光部分或光阻之未曝光部分，且下方聚合物層105之暴露的部分係以如乾蝕刻製程移除。然而，可利用任何其它合適之用於圖案化聚合物層105的方法。 圖1D繪示，一旦聚合物層105已圖案化而暴露凸塊下金屬化層137，高電壓晶片141可透過聚合物層105接合至凸塊下金屬化層137透以形成第一感測器封裝件149。在一實施例中，為了放大感測器的靈敏度，高電壓晶片141係被設計與連接以供給高電壓，諸如在約5伏特(V)與約50 V之間，諸如約33 V給指紋感測器104。例如，藉由將高電壓晶片141與指紋感測器104積體而使得高電壓可供給至指紋感測器104，指紋感測器104的靈敏度可藉由從如3.3 V提高輸入電壓至33 V增加十倍。 在一實施例中，高電壓晶片141可包含第二半導體基板(未分開繪示)、主動裝置(未分開繪示)、用以互連高電壓晶片141的主動裝置之金屬化層(未分開繪示)、及為了互連高電壓晶片141至指紋感測器104之第一外部連接143。第二半導體基板可包含經摻雜或未經摻雜之主體矽、或絕緣體上矽(SOI)基板的主動層。一般，SOI基板包含一層半導體材料，諸如矽、鍺、矽鍺、SOI、絕緣體上矽鍺(SGOI)、或其組合。可使用之其它基板包括多層基板、梯度基板、或雜合方位向基板。 用於高電壓晶片141的主動裝置包含廣泛種類的主動裝置及被動裝置諸如電容器、電阻器、電感及類似物，其可用以產生用於高電壓晶片141設計之想要的結構及功能要求。主動裝置可使用任何合適的方法形成在第二半導體基板內不然在第二半導體基板上。 用於高電壓晶片141的金屬化層係形成在第二半導體基板及高電壓晶片141的主動裝置上方且係設計用以連接各種主動裝置以形成功能電路。在一實施例中，金屬化層係由介電及導電材料之交替層所形成且可透過任何合適的製程(諸如沉積、鑲嵌、雙鑲嵌、等)形成。在一實施例中，可能有四個金屬化層，其與第二半導體基板被至少一個層間介電層(ILD)分開，但金屬化層的精確數目係取決於高電壓晶片141的設計。 第一外部連接143可被形成以互連高電壓晶片141至指紋感測器104且可以是，例如接觸凸塊，雖然可利用任何合適的連接。在其中第一外部連接143係接觸凸塊的一實施例中，第一外部連接143可包含材料諸如錫、或其它合適的材料諸如銀、無鉛錫、或銅。在其中第一外部連接143係錫焊料凸塊的一實施例中，第一外部連接143可藉由下列形成，透過此等常用方法，諸如蒸發、電鍍、印刷、焊料轉移、植球、等，初始形成一層錫至厚度如在約30 µm與約100 μm之間。一但一層焊料已形成在結構上，可實施回焊以將材料塑形成想要的凸塊形狀。 高電壓晶片141可被形成以具有第一寬度W1 在約1 mm與約5 mm之間，諸如約1.5 mm，且也可被形成以具有第二厚度T2 在約70 µm與約150 µm之間，諸如約100 µm。另外，在因為它可能延伸進入且超出圖而未顯示於圖1D中之際，高電壓晶片141也可被形成以具有第一長度在約1 mm與約5 mm之間，諸如約2 mm。然而，任何合適的尺寸可利用於高電壓晶片141。 高電壓晶片141可連接至凸塊下金屬化層137，例如藉由初始施加焊料糊至暴露的凸塊下金屬化層137且接著覆晶接合高電壓晶片141至凸塊下金屬化層137。在一實施例中，高電壓晶片141可藉由依序浸漬高電壓晶片141的第一外部連接143至助焊劑中，且接著為了將高電壓晶片141的第一外部連接143與凸塊下金屬化層137之個別者實體對準使用拾取和放置工具而接合。在其中第一外部連接143係焊球的一實施例中，一旦高電壓晶片141已放置，為了接合高電壓晶片141與下方凸塊下金屬化層137，可實施回焊製程且可不實施助焊劑清潔。然而，可利用任何其它合適的連接件或連接製程，諸如金屬至金屬接合或類似物。 一旦高電壓晶片141已接合至凸塊下金屬化層137，為了幫助保護及隔離裝置，底膠材料147可放置在高電壓晶片141與指紋感測器104之間。在一實施例中，底膠材料147係保護材料，其用以緩衝及支撐高電壓晶片141免於操作及環境劣化。諸如操作期間熱的產生所造成之應力。底膠材料147可包含，例如液體環氧化物或其它保護材料，且接著被固化至硬化，及可藉由如注入分注。 另外，在第一聚合物層105已圖案化之後，第二外部連接139可被利用以提供用於電連接至第一重佈線層107之外部連接點且可以是，例如作為球柵陣列(ball grid array，BGA)之部分的接觸凸塊，雖然可利用任何合適的連接。在其中第二外部連接139係接觸凸塊的一實施例中，第二外部連接139可包含材料諸如錫、或其它合適的材料諸如銀、無鉛錫、或銅。在其中第二外部連接139係錫焊料凸塊的一實施例中，第二外部連接139可藉由下列形成，透過此等常用方法，諸如蒸發、電鍍、印刷、焊料轉移、植球、等，初始形成一層錫至厚度如約250 μm。一但一層焊料已形成在結構上，可實施回焊以將材料塑形成想要的凸塊形狀。 圖1E繪示結構接合至基板150。在一實施例中，為了提供想要的功能性給使用者，基板150可以是，如印刷電路板，其係工作以將各種電氣組件彼此互連。替代地，基板150可以是可撓性基板或包含可蝕刻成微量之各種寬度及長度且透過層間通路連接之多個導電層(未個別繪示)。線及通路可一起形成電網絡以從基板150的一側至另一側路由DC功率、接地、及訊號。技術領域中具有通常知識者將認知到基板150可從有機(層壓體)材料諸如雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)、聚合物系材料諸如液晶聚合物(liquid-crystal polymer，LCP)、陶瓷材料諸如低溫共燒製陶瓷(low-temperature co-fired ceramic，LTCC)、矽或玻璃插置件或類似物製造。技術領域中具有通常知識者也將認知到導電層及通路可從任何合適的導電材料形成，諸如銅、鋁、銀、金、其它金屬、合金、其組合、及/或類似物，且藉由任何合適的技術形成，諸如電化學電鍍(electro-chemical plating，ECP)、無電式電鍍、其他沉積方法諸如濺鍍、印刷、及化學氣相沉積(CVD)方法、或類似物。基板150可被形成或獲取以具有第三厚度T3 在約100 µm與約1000 µm之間，諸如約200 µm，雖然可利用任何合適的厚度。 在一些實施例中，基板150也可包括電氣元件，諸如電阻器、電容器、訊號分布電路、這些的組合、或類似物。這些電氣元件可以是主動、被動、或其組合。在其它實施例中，基板150係不含主動及被動電氣元件二者於其中。所有此等組合係意圖完全包括在實施例的範疇內。 另外，為了容置高電壓晶片141的存在，基板150可被形成以具有或已於其中形成有第一開口151。在一實施例中，為了容置高電壓晶片141，第一開口151被尺寸化，且因此第一開口151的尺寸係至少取決於高電壓晶片141的尺寸。然而，在其中高電壓晶片141具有第一寬度W1 、第一長度、及第二厚度T2 的一實施例中，第一開口151可被形成以具有第二寬度W2 在約2 mm與約6 mm之間，諸如約2.5 mm。另外，第一開口151可具有第二長度(由於第二長度將延伸進入且超出圖而未分開顯示於圖1E中)在約2 mm與約6 mm之間，諸如約3.5 mm。然而，可利用容置高電壓晶片141之任何合適的尺寸。 另外，在一些實施例中，且如圖1E所繪示，第一開口151將一路延伸通過基板150。因此，第一開口151將具有基板150的第三厚度T3 ，諸如係在約0.1 mm與約1 mm之間，諸如約0.2 mm。然而，可使用任何合適的尺寸。 在另一實施例中(藉由虛線繪示在圖1E中)，第一開口151可被形成以部分但不完全延伸通過基板150。在此實施例中，第一開口151可被形成以延伸進入基板150第一距離D1 係在約50 µm與約500 µm之間，諸如約100 µm。然而，可利用任何合適的深度以容置高電壓晶片141。 基板150可進一步包含允許與第二外部連接139電連接之第二接觸墊153。在一實施例中，第二接觸墊153可從與上面關於圖1A描述之接觸墊119相似之材料並使用相似之製程形成。例如，第二接觸墊153可以是使用製程諸如CVD或PVD形成之鋁接觸墊。然而，可使用任何合適之製造第二接觸墊153的材料或方法。 為了接合第二接觸墊153與第二外部連接139，第二接觸墊153與第二外部連接139係先彼此對準。例如，在一實施例中，第二外部連接139可對準並放置成與第二接觸墊153實體接觸。一旦就位且對準，為了實體接合及電接合第二外部連接139至基板150，可回焊第二外部連接139。 藉由附接指紋感測器104至基板150而使得高電壓晶片141係位在第一開口151內，結構的整體高度可減少。例如，在一實施例中，基板150連同附接指紋感測器104的整體高度可以是第一高度H1 係在約0.4 mm與約1.5 mm之間，諸如約0.5 mm。然而，可利用任何高度。 圖1F繪示另一實施例，其中替代於在指紋感測器104下面置中，高電壓晶片141可依想要者相對於指紋感測器104坐落。例如，在圖1F所繪示之實施例中，高電壓晶片141可位在距指紋感測器104的第一側(在此俯視圖中)第二距離D2 處，D2 係在約80 µm與約4000 µm之間，諸如約1000 µm，且也位在距指紋感測器104的第二側第三距離D3 處，D3 係在約80 µm與約4000 µm之間，諸如約1500µm。然而，可利用任何合適之相對於指紋感測器104之高電壓晶片141的布局。 藉由如上所述形成第一感測器封裝件149，不僅指紋感測器104的靈敏度可藉由最小化電極陣列120與手指之間的感測間隙而增進，也使用扇入及貫穿通路來積體高電壓晶片141並增加電荷(Q=CxV)。 此一增加允許感測器靈敏度的增加。 圖2A繪示另一實施例，其繪示第二感測器封裝件200，為了連接電極陣列120與第三重佈線層203，第二感測器封裝件200使用延伸通過半導體基板111之貫穿基板通路201。然而，在此實施例中，貫穿基板通路201係被利用以將電極陣列120與位在指紋感測器104的前側113上之金屬化層電連接至指紋感測器104的背側115。貫穿基板通路201可藉由下列形成，在金屬化層的形成之前，初始施加合適的光阻至半導體基板111及顯影光阻且接著蝕刻半導體基板111以產生TSV開口。在此階段，用於貫穿基板通路201之開口可被形成以便延伸進入半導體基板111中至至少大於完成之半導體基板111之最終想要的高度之深度。 一但用於貫穿基板通路201之開口已形成，用於貫穿基板通路201之開口可填充有如，阻障層及導電材料。阻障層可包含導電材料諸如氮化鈦，雖然可利用其它材料，諸如氮化鉭、鈦、介電質、或類似物。可使用CVD製程諸如PECVD形成阻障層。然而，可使用其它製程，諸如濺鍍或金屬有機化學氣相沉積(metal organic chemical vapor deposition，MOCVD)。阻障層可被形成以便仿照下方用於貫穿基板通路201之開口形狀的輪廓。 導電材料可包含銅，雖然可利用其它合適的材料，諸如鋁、合金、摻雜多晶矽、其組合、及類似物。導電材料可藉由沉積晶種層且接著電鍍銅至晶種層上、填充及上填用於貫穿基板通路201之開口而形成。一旦用於貫穿基板通路201之開口已填充，在用於貫穿基板通路201之開口外的過量阻障層及過量導電材料可透過研磨製程諸如化學機械研磨(CMP)移除，雖然可利用任何合適的移除製程。 一旦導電材料係在用於貫穿基板通路201之開口內，為了暴露用於貫穿基板通路201之開口及從延伸通過半導體基板111之導電材料形成貫穿基板通路201，可實施半導體基板111的薄化。在一實施例中，半導體基板111的薄化可藉由平坦化製程諸如CMP或蝕刻實施，使貫穿基板通路201與半導體基板111共平面。 然而，技術領域中具有通常知識者將認知到，上述用於形成貫穿基板通路201之製程僅為形成貫穿基板通路201的一個方法，且其他方法也意圖完全包括在實施例的範疇內。例如，也使用形成用於貫穿基板通路201之開口、以介電材料填充用於貫穿基板通路201之開口、薄化半導體基板111以暴露介電材料、移除介電材料、及以導體填充用於貫穿基板通路201之開口。此及所有其它合適之用於形成貫穿基板通路201至半導體基板111中的方法係意圖完全包括在實施例的範疇內。 一旦貫穿基板通路201已形成(且主動裝置及金屬化層也已如想要者完成)，為了提供貫穿基板通路201與如高電壓晶片141及第二外部連接139之間的互連性，可形成第三重佈線層203與貫穿基板通路201電連接。在一實施例中，第三重佈線層203可用與上面關於第一重佈線層107描述相似之材料並使用相似之製程形成。例如，第三重佈線層203可由使用沉積及光微影遮罩與蝕刻製程形成之多層導電及介電材料所形成。然而，可利用任何合適的形成材料或方法來形成第三重佈線層203。 一旦第三重佈線層203已形成，高電壓晶片141可接合至第三重佈線層203，且第二外部連接139可放置成與第三重佈線層203電連接。在一實施例中，高電壓晶片141及第二外部連接139可如上面關於圖1D描述般形成或放置。例如，高電壓晶片141可接合至第三重佈線層203，且可放置並回焊第一外部連接143。 另外，在高電壓晶片141與第一外部連接143已形成或放置之前或之後，感測器表面材料123可使用如介面層136附接至指紋感測器104。在一實施例中，感測器表面材料123可如上面關於圖1B描述般以介面層136附接。例如，介面層136可實體接觸感測器表面材料123與指紋感測器104二者。然而，可利用任何合適之附接感測器表面材料123的方法。 圖2B繪示基板150至第二感測器封裝件200之附接。在一實施例中，第二感測器封裝件200係如上面關於圖1E描述般接合至基板150。例如，第二外部連接139係對準第二接觸墊153，且實施回焊製程以電接合及實體接合第二外部連接139至第二接觸墊153。然而，可利用任何合適之接合第二感測器封裝件200與基板150的方法。 另外，在接合製程期間，高電壓晶片141係對準並插入在位在基板150內(或通過基板150)的第一開口151中。在一實施例中，第一開口151係被形成或坐落以便接受高電壓晶片141並允許組合之基板150與第二感測器封裝件200的整體高度被減少。例如，在此實施例中，結構的整體高度可減少到第二高度H2 ，H2 係在約370 µm與約1500 µm之間，諸如約400 µm。然而，可利用任何合適的高度。 藉由如所述形成第三重佈線層203連同貫穿基板通路201，貫穿基板通路201及第三重佈線層203可用以將來自指紋感測器104之訊號輸出成重佈訊號。另外，具有基板150及在基板150內之第一開口151的納入，可達成具有在第一開口151內部之高電壓晶片141的彈性表面安裝技術(surface mount technology，SMT)製程。 圖3A至3B繪示另一實施例，其中在沒有使用第三重佈線層203下，係形成貫穿基板通路201與第二外部連接139及高電壓晶片141電連接以形成第三感應器封裝件300。在此實施例中，替代於形成第三重佈線層203在半導體基板111的背側115上，第三接觸墊301係直接形成在貫穿基板通路201上方且與貫穿基板通路201實體連接及/或電連接。在一實施例中，第三接觸墊301可使用與上面關於接觸墊119描述相似之材料及製程形成。例如，第三接觸墊301可使用沉積及圖案化製程從鋁形成。然而，可利用任何合適之用於形成第三接觸墊301的製程。 一旦第三接觸墊301已形成，第二保護層303可形成在第三接觸墊301上方。在一實施例中，第二保護層303可以是保護材料，諸如聚苯并噁唑(PBO)或聚醯亞胺(PI)、氧化矽、氮化矽、氧氮化矽、苯并環丁烷(BCB)、或任何其它合適的保護材料。第二保護層303可基於所選材料使用方法，諸如旋塗製程、沉積製程(如，化學氣相沉積)、或其它合適的製程形成，且可被形成以具有厚度在約1 µm與約100 µm之間，諸如約20 µm。一旦就位，為了暴露第三接觸墊301，可圖案化第二保護層303。 一旦第三接觸墊301已形成，感測器表面材料123可放置在指紋感測器104上方，高電壓晶片141可接合至第三接觸墊301，且第二外部連接139可放置成與第三接觸墊301電連接。在一實施例中，感測器表面材料123、高電壓晶片141及第二外部連接139可如上面關於圖1B至1D描述般形成或放置。例如，感測器表面材料123可用第二膠層126黏附，高電壓晶片141可接合置第三接觸墊301，且可放置並回焊第二外部連接139。 圖3B繪示基板150至第三感測器封裝件300之附接。在一實施例中，第三感測器封裝件300係如上面關於圖1E描述般接合至基板150。例如，第二外部連接139係對準第二接觸墊153，且實施回焊製程以電接合及實體接合第二外部連接139至第二接觸墊153。然而，可利用任何合適之接合第三感測器封裝件300與基板150的方法。 另外，在接合製程期間，高電壓晶片141係對準並插入在位在基板150內(或通過基板150)的第一開口151中。在一實施例中，第一開口151係被形成或坐落以便接受高電壓晶片141並允許組合之基板150與第三感測器封裝件300的整體高度被減少。 藉由直接接合高電壓晶片141在貫穿基板通路201上方，可避免用於形成第三重佈線層203之製程步驟，允許更簡單且較不複雜之製造製程。另外，藉由不製造第三重佈線層203，沒有第三重佈線層203之結構的整體高度可被減少。例如，在一實施例中，整體結構可具有第三高度H3 ，H3 係在約360 µm與約1500 µm之間，諸如約390 µm。然而，可利用任何合適的高度。 圖4繪示一實施例，其中基板150及第一感測器封裝件149係併入到，如半導體裝置結構400中，具有位在半導體裝置結構400的第一側之第一感測器封裝件149及位在與第一側相對之第二側之顯示器裝置409。在一實施例中，半導體裝置結構400包括多晶片封裝件結構(multi-chip package system，MCPS)413，具有透過基板150附接至MCPS 413之指紋感測器104，具有基板150係透過如連接件417諸如焊料凸塊接合至MCPS 413，雖然可利用任何合適的連接件。 在一些實施例中，除了MCPS 413之外，其它電氣組件415a及415b也藉由連接件417附接至基板150。電氣組件415a及415b可彼此相似或不同。作為一實例，電氣組件415a可以是半導體晶粒或半導體封裝件，及電氣組件415b可以是離散電氣組件，如被動或主動裝置諸如電容器、電感、電阻器、電晶體、二極體、或類似物。技術領域中具有通常知識者將理解圖4僅為例示說明，因為不同數目的MCPS 413及電氣組件415a/415b可搭配指紋感測器104使用而不會悖離如當前揭露的精神。 如圖4中所繪示，電池411係藉由纜線419電耦合至基板150，具有MCPS 413設置在電池411與基板150之間。在一些實施例中，纜線419係可撓性纜線，諸如可撓性印刷電路(flexible printed circuit，FPC)纜線。顯示器裝置409，諸如液晶顯示器(liquid crystal display，LCD)顯示器裝置係設置在電池411旁邊，以電池411係設置在MCPS 413與顯示器裝置409之間。在一些實施例中，顯示器裝置409係藉由纜線421諸如FPC纜線電耦合至基板150。 另外，根據一些實施例，半導體裝置結構400具有殼401。在一些實施例中，半導體裝置結構400包含可穿戴式裝置，諸如智能手錶、健身裝置、或健康監測裝置。 藉由如所述附接第一感測器封裝件149至基板150，及併入該結構至半導體裝置結構400中，可減少個別組件的厚度，允許使用更大大小的電池411。例如，在一實施例中，電池411的高度可被增加以具有第四高度H4 在約3 mm與約7 mm之間，諸如約5 mm。藉由增加電池411的大小但不增加結構的大小，在充電之間，半導體裝置可運行更長一段時間。 圖5繪示一替代實施例，其中大小所省下者可能不是用於併入較大電池，而是可能用於減少半導體裝置結構400的整體大小。在此實施例中，半導體裝置結構400可被減少以具有整體第五高度H5 在約8 mm與約15 mm之間，諸如約10 mm。然而，可利用合適的大小。藉由減少大小，可達成更小的整體結構。 另外，在圖4及圖5所述實施例係關於上面關於圖1A至1F描述之第一感測器封裝件149描述之際，實施例不限於第一感測器封裝件149。反而是，也可利用任何合適的感測器封裝件，諸如第二感測器封裝件200或感測器封裝件300。所有合適的組合係意圖完全包括在實施例的範疇內。 根據一實施例，提供一種製造一指紋掃描器之方法，包含附接一指紋感測器表面材料在一指紋感測器上方。該指紋感測器包含一半導體基板；及一電極陣列，在該半導體基板與該指紋感測器表面材料之間。係附接一高電壓晶片與該指紋感測器電連接，其中該高電壓晶片係位在與該指紋感測器表面材料相比之該指紋感測器的一相對側上。係附接該指紋感測器至一基板，其中在該附接該指紋感測器至該基板之後，該高電壓晶片係位在該基板的一開口內。 根據另一實施例，提供一種製造一指紋掃描器之方法，該方法包含形成貫穿通路貫穿一指紋感測器基板。係形成一電極陣列在該指紋感測器基板上方，其中該電極陣列係與在該指紋感測器基板的一第一側上的主動裝置電連接，以及係附接一指紋感測器外蓋在該指紋感測器基板的該第一側上方。係附接一高電壓晶片與該主動裝置電連接，其中該高電壓晶片係位在與該電極陣列相比之該指紋感測器基板的一相對側上，及係放置該高電壓晶片至位在一第二基板內的一開口中。 根據又一實施例，提供一種半導體裝置，包含一指紋感測器。貫穿通路，電連接該指紋感測器的一第一側與位在該指紋感測器的一第二側上的一導電元件，該第二側與該第一側相對。一高電壓晶片，與該貫穿通路電連接；及一基板，與該貫穿通路電連接，其中該高電壓晶片係位在該基板的一開口內。 前面列述了數個實施例的特徵以便本技術領域具有通常知識者可更佳地理解本揭露之態樣。本技術領域具有通常知識者應了解它們可輕易地使用本揭露作為用以設計或修改其他製程及結構之基礎以實現本文中所介紹實施例的相同目的及/或達成本文中所介紹實施例的相同優點。本技術領域具有通常知識者也應體認到此等均等構造不會悖離本揭露之精神及範疇，以及它們可在不悖離本揭露之精神及範疇下做出各種改變、取代、或替代。
101‧‧‧載體基板
103‧‧‧黏著層
104‧‧‧指紋感測器
105‧‧‧聚合物層
107‧‧‧第一重佈線層
109‧‧‧第一貫穿基板通路
111‧‧‧半導體基板
112‧‧‧第二黏著層
113‧‧‧前側
115‧‧‧背側
119‧‧‧接觸墊
120‧‧‧電極陣列
121‧‧‧第二重佈線層
122‧‧‧第一保護層
123‧‧‧感測器表面材料
125‧‧‧囊封劑
126‧‧‧第二膠層
133‧‧‧一系列導電層
135‧‧‧一系列介電層
136‧‧‧介面層
137‧‧‧凸塊下金屬化層
139‧‧‧第二外部連接
141‧‧‧高電壓晶片
143‧‧‧第一外部連接
147‧‧‧底膠材料
149‧‧‧第一感測器封裝件
150‧‧‧基板
151‧‧‧第一開口
152‧‧‧環結構
153‧‧‧第二接觸墊
154‧‧‧紫外光膠帶
200‧‧‧第二感測器封裝件
201‧‧‧貫穿基板通路
203‧‧‧第三重佈線層
300‧‧‧第三感應器封裝件
301‧‧‧第三接觸墊
303‧‧‧第二保護層
400‧‧‧半導體裝置結構
401‧‧‧殼
409‧‧‧顯示器裝置
411‧‧‧電池
413‧‧‧多晶片封裝件結構
415a‧‧‧電氣組件
415b‧‧‧電氣組件
417‧‧‧連接件
419‧‧‧纜線
421‧‧‧纜線
W1‧‧‧ 第一寬度
W2‧‧‧ 第二寬度
T1‧‧‧ 第一厚度
T2‧‧‧ 第二厚度
T3‧‧‧ 第三厚度
D1‧‧‧ 第一距離
D2‧‧‧ 第二距離
D3‧‧‧ 第三距離
H1‧‧‧ 第一高度
H2‧‧‧ 第二高度
H3‧‧‧ 第三高度
H4‧‧‧ 第四高度
H5‧‧‧ 整體第五高度
本揭露之態樣將在與隨附圖式一同閱讀下列詳細說明下被最佳理解。請注意，根據業界標準作法，各種特徵未依比例繪製。事實上，為了使討論內容清楚，各種特徵的尺寸可刻意放大或縮小。 圖1A至1F係根據一些實施例繪示指紋感測器封裝件，其使用從感測器側向移除之貫穿通路。 圖2A至2B係根據一些實施例繪示使用延伸通過指紋感測器與重佈線層連接之貫穿通路的實施例。 圖3A至3B係根據一些實施例繪示在沒有重佈線層下使用延伸通過指紋感測器之貫穿通路的實施例。 圖4係根據一些實施例繪示併入指紋感測器封裝件至半導體裝置中。 圖5係根據一些實施例繪示併入指紋感測器封裝件至半導體裝置中。

Claims (10)

  1. 一種製造一半導體裝置之方法，該方法包含：附接一感測器表面材料在一感測器晶片上方，其中該感測器晶片包含：一半導體基板；以及一電極陣列，在該半導體基板與該感測器表面材料之間；附接一高電壓晶片與該感測器晶片電連接，其中該高電壓晶片係位在與該感測器表面材料相比之該感測器晶片的一相對側上；以及附接該感測器晶片至一基板，其中在該附接該感測器晶片至該基板之後，該高電壓晶片係位在該基板的一開口內。
  2. 如申請專利範圍第1項之方法，其中該基板的該開口一路延伸通過該基板。
  3. 如申請專利範圍第1項之方法，其中該基板的該開口僅部分延伸通過該基板。
  4. 如申請專利範圍第1項之方法，其中該感測器晶片進一步包含一重佈線層，位在該感測器表面材料與該半導體基板之間。
  5. 如申請專利範圍第1項之方法，進一步包含形成接觸墊直接實體接觸位在該感測器晶片內的貫穿基板通路。
  6. 一種製造一半導體裝置之方法，該方法包含：形成貫穿通路貫穿一感測器基板；形成一電極陣列在該感測器基板上方，其中該電極陣列係與在該感測器基板的一第一側上的主動裝置電連接；附接一感測器外蓋在該感測器基板的該第一側上方；附接一高電壓晶片與該主動裝置電連接，其中該高電壓晶片係位在與該電極陣列相比之該感測器基板的一相對側上；以及放置該高電壓晶片至位在一第二基板內的一開口中。
  7. 如申請專利範圍第6項之方法，進一步包含形成一重佈線層與該貫穿通路電連接且在與該主動裝置相比之該感測器基板的一相對側上，其中該附接該高電壓晶片附接該高電壓晶片至該重佈線層。
  8. 如申請專利範圍第6項之方法，進一步包含形成一接觸墊與該貫穿通路實體接觸，其中該附接該高電壓晶片附接該高電壓晶片至該接觸墊。
  9. 如申請專利範圍第6項之方法，其中該開口從該第二基板的一側延伸至該第二基板的一第二側，該第二側與該第一側相對。
  10. 一種半導體裝置，包含：一感測器晶片，其上附接一感測器表面材料，其中該感測器晶片包含：一半導體基板，以及一電極陣列，其位在該半導體基板與該感測器表面材料之間；貫穿通路，電連接該感測器晶片的一第一側與位在該感測器晶片的一第二側上的一導電元件，該第二側與該第一側相對；一高電壓晶片，與該貫穿通路電連接；以及一基板，與該貫穿通路電連接，其中該高電壓晶片係位在該基板的一開口內。
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