WO2020062140A1 - 芯片封装结构、方法和电子设备 - Google Patents

芯片封装结构、方法和电子设备 Download PDF

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Publication number
WO2020062140A1
WO2020062140A1 PCT/CN2018/108625 CN2018108625W WO2020062140A1 WO 2020062140 A1 WO2020062140 A1 WO 2020062140A1 CN 2018108625 W CN2018108625 W CN 2018108625W WO 2020062140 A1 WO2020062140 A1 WO 2020062140A1
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WO
WIPO (PCT)
Prior art keywords
chip
substrate
optical
image sensing
auxiliary
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Application number
PCT/CN2018/108625
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English (en)
French (fr)
Inventor
吴宝全
蒋万里
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN202011636118.5A priority Critical patent/CN112820749A/zh
Priority to PCT/CN2018/108625 priority patent/WO2020062140A1/zh
Priority to CN201880001868.XA priority patent/CN109417081B/zh
Publication of WO2020062140A1 publication Critical patent/WO2020062140A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present disclosure relates to the technical field of chip packaging, and more particularly, to a chip packaging structure, method, and electronic device.
  • an optical fingerprint chip is affected by its packaging method, and the degree of integration is greatly limited.
  • the current optical fingerprint chip generally uses a separate optical fingerprint module packaging solution.
  • the image sensor chip, auxiliary chip and connector of such optical fingerprint module are respectively pasted on different substrates, and then passed through a flexible circuit board ( Flexible Printed Circuit (FPC) electrically connects auxiliary modules, image sensor chip modules, and connectors.
  • FPC Flexible Printed Circuit
  • the present disclosure provides a chip package structure, method and electronic device, which effectively improves the chip package integration degree, reduces the volume, and improves the degree of standardization.
  • a chip packaging structure including: a substrate, a connector, an image sensing module, and an auxiliary module, wherein the image sensing module and the auxiliary module are integrally packaged by using the substrate; the image The sensing module includes an image sensing chip, the image sensing chip is packaged on a first surface of the substrate; the auxiliary module includes at least one optical auxiliary chip, and the at least one optical auxiliary chip is packaged on a first surface of the substrate.
  • the two surfaces are electrically connected to the image sensing chip through the substrate; the connector is connected to the substrate for the chip package structure to be electrically connected to an external unit.
  • the connector is connected to the first surface or the second surface of the substrate; specifically, the image sensing chip and the at least one optical assistant
  • the chips are respectively disposed on the main body portions of the first surface and the second surface of the substrate, and the connectors are connected to the edge portions of the first surface or the second surface of the substrate.
  • the substrate further includes a plurality of sides, and the connector is disposed on one of the sides of the substrate.
  • the first surface is a main surface of the substrate, and the second surface is a back surface where the substrate faces away from the main surface.
  • the image sensing module further includes a lens module, and the lens module is disposed above the image sensing chip, and is used for converging a target optical signal or Guide to the image sensing chip.
  • the lens module includes a lens barrel and an optical lens housed in the lens barrel
  • the image sensing chip includes an optical sensing array
  • the optical lens and The optical sensing array performs alignment setting of the optical path.
  • the lens module further includes a filter, and the filter is housed in the lens barrel and is located in the optical lens and the image sensor. Between the chips, the filter is used to isolate external interference light to prevent it from entering the optical sensing array.
  • the image sensing module is an optical fingerprint detection module
  • the target light signal is fingerprint detection light reflected from a finger surface, where the fingerprint detection light passes
  • the optical lens is converged or guided to the image sensing chip, and the image sensing chip is configured to detect the fingerprint detection light to perform optical fingerprint imaging.
  • the image sensing chip is attached to the first surface of the substrate through a first adhesive, and a pad on the surface thereof passes through a first metal wire.
  • An electrical connection point connected to the first surface of the substrate.
  • the optical auxiliary chip is attached to the second surface of the substrate through a second adhesive, and the pads on the surface are connected by a second metal wire.
  • the optical auxiliary chip is electrically connected to the image sensing chip through a connection line of the substrate.
  • the substrate is a silicon substrate having through silicon vias
  • the image sensing chip is connected to a first surface of the silicon substrate through a pad on a bottom surface thereof. And at least a part of the pads of the image sensing chip are electrically connected to the through silicon vias of the silicon substrate.
  • the optical auxiliary chip is connected to the second surface of the silicon substrate through flip-chip bonding through a pad on its bottom surface, and the optical auxiliary chip At least a part of the pads are electrically connected to the image sensing chip through the through silicon via.
  • the auxiliary module further includes at least one capacitor, and the at least one capacitor is connected to an edge region of the second surface of the substrate through solder.
  • the auxiliary module further includes a molding compound that seals the optical auxiliary chip and the at least one capacitor on a second surface of the substrate. And make the surface of the chip package structure flat.
  • a chip packaging method including: providing a substrate for chip packaging, the substrate including a first surface and a second surface; and packaging an image sensing chip on the first surface of the substrate; At least one optical auxiliary chip is packaged on the second surface of the substrate, wherein the at least one optical auxiliary chip is electrically connected to the image sensing chip through the substrate; and a connector is connected to the substrate, For the chip package structure to be electrically connected with an external unit.
  • the connector is connected to the first surface or the second surface of the substrate; specifically, the image sensing chip and the at least one optical assistant
  • the chips are respectively disposed on the main body portions of the first surface and the second surface of the substrate, and the connectors are connected to the edge portions of the first surface or the second surface of the substrate.
  • the substrate further includes a plurality of sides, and the connector is disposed on one of the sides of the substrate.
  • the substrate is a silicon substrate having a through silicon via, and the image sensing chip and the connector are connected to the substrate through a same surface mount process.
  • the first surface of the substrate; or, the connector and the at least one optical assistant chip are connected to the second surface of the substrate through the same surface mount process.
  • the method further includes: attaching a lens module above the image sensing chip, wherein the lens module includes a lens barrel and is housed in a housing. An optical lens and a filter of the lens barrel, and the optical paths between the optical lens and the optical sensing array of the image sensing chip are aligned after the lens module is attached.
  • the step of packaging the image sensing chip on the first surface of the substrate includes: using a first adhesive to attach the image sensing chip The first surface of the substrate is bonded to the first surface of the substrate; a wire bonding process is used to electrically connect the pads on the surface of the image sensing chip and the electrical connection points on the first surface of the substrate through a first metal wire.
  • the step of packaging at least one optically-assisted chip on the second surface of the substrate includes: using a second adhesive to encapsulate the at least one optically-assisted chip. Adhere to the second surface of the substrate; and use a wire bonding process to electrically connect the pads on the surface of the at least one optical assistant chip with the electrical connection points on the second surface of the substrate through a second metal wire.
  • the substrate is a silicon substrate having through silicon vias
  • the step of packaging the image sensing chip on the first surface of the substrate includes: The pads on the bottom surface of the image sensing chip connect the image sensing chip to the first surface of the silicon substrate, and at least part of the pads of the image sensing chip are connected with through silicon vias of the silicon substrate. Electrical connection.
  • the step of packaging at least one optical auxiliary chip on the second surface of the substrate includes: passing the pads on the bottom surface of the at least one optical auxiliary chip to The soldering method connects the at least one optical auxiliary chip to the second surface of the silicon substrate, wherein at least a part of the pads of the at least one optical auxiliary chip is electrically connected to the image sensing chip through the through silicon via. Sexual connection.
  • the method further includes: connecting at least one capacitor to an edge region of the second surface of the substrate; and using at least one optically-assisted chip with a plastic sealant. And the at least one capacitor is sealed on the second surface of the substrate and makes the surface of the chip package structure flat.
  • the at least one capacitor and the at least one optical auxiliary chip are connected to the second surface of the substrate through a same surface mount process.
  • an electronic device which includes a display screen and an optical fingerprint detection device located below the display screen.
  • the optical fingerprint detection device includes a chip package structure as described above.
  • the integrated packaging of the image sensing chip and the optical auxiliary chip can not only reduce the steps of chip packaging, but also improve The degree of integration of the chip package reduces the overall volume of the chip package module and improves the standardization of the chip package.
  • FIG. 1 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a chip packaging method according to an embodiment of the present disclosure
  • 3 to 9 are schematic diagrams of a manufacturing process of the chip package structure shown in FIG. 1;
  • FIG. 10 is a schematic diagram of a chip package structure according to another embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a chip packaging method according to another embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure.
  • the chip package structure includes a substrate 100, an auxiliary module 200, an image sensing module 300, and a connector 400.
  • the image sensing module 300, the auxiliary module 200, and the connector 400 realize an integrated high-integration package through the substrate 100.
  • the substrate 100 includes a main surface, a back surface facing away from the main surface, and a plurality of side surfaces connecting the main surface and the back surface. More specifically, the main surface and the back surface may be the substrate 100, respectively. Top and bottom surfaces.
  • the auxiliary module 200 is disposed on a lower surface of the substrate 100; the image sensing module 300 is disposed on an upper surface of the substrate 100 and is located on a main body portion of the substrate 100.
  • the connector 400 is used for the chip package structure to be electrically connected to an external unit, and may be specifically disposed on an upper surface or a lower surface of the substrate 100.
  • the connector 400 may be disposed on the upper surface of the substrate 100 and located on an edge portion of the substrate 100, as shown in FIG. 1; alternatively, in other embodiments, the connector 400 may also be disposed under the substrate 100 The edge of the surface.
  • the connector 400 may be connected to one surface of the substrate 100. That is to say, in the embodiment of the present disclosure, the installation manner and installation position of the connector 400 are not limited to the structure of FIG. 1; In addition, the specifications and outlet manners of the connector 400 can be determined according to actual needs This embodiment of the present disclosure does not limit this.
  • the substrate 100 may be a PCB substrate, a silicon substrate with a through silicon via (TSV), a ceramic substrate, or an organic material substrate, and the upper and lower surfaces thereof may be used for chip packaging at the same time.
  • TSV through silicon via
  • the image sensing module 300 and the connector 400 are packaged on the upper surface of the substrate 100
  • the auxiliary module 200 is packaged on the lower surface of the substrate 100.
  • the substrate 100 may further include functional circuits (or auxiliary circuits) and related connection lines required for the chip package structure to work; and, a plurality of electrical connection points are also made on the surface of the substrate 100 in advance.
  • the electrical connection points are used for electrical connection with the auxiliary module 200, the image sensing module 300, the connector 400, and the like by means of ordinary welding, flip-chip welding, narrow-band automatic welding, or metal wire bonding.
  • the electrical connection point may also be connected to a connection line inside the substrate 100 to achieve electrical interconnection of the entire chip package structure.
  • the image sensing module 300 may be an optical fingerprint detection module, and may include an image sensing chip 301 and a lens module 302.
  • the image sensing chip 301 may be a CMOS image sensor (CIS) chip, which is disposed on the upper surface of the substrate 100 and is located on the main body of the substrate 100.
  • the image sensing chip 301 may be through an adhesive. 502 is attached and fixed on the upper surface of the substrate 100.
  • CIS CMOS image sensor
  • the image sensing chip 301 includes an optical sensing array located in a middle region thereof and a pad 602 disposed at an edge.
  • the optical sensing array is mainly used to detect a target light signal through the lens module 302 to achieve optical imaging.
  • the target light signal may be fingerprint detection light formed by exciting a light source to reflect on a finger.
  • the fingerprint detection light is transmitted to the optical sensing array of the image sensing chip 301 through the lens module 302, and the optical sensing array can detect the fingerprint detection light to realize optical fingerprint imaging.
  • the pad 602 may be connected to an electrical connection point on the upper surface of the substrate 100 through a metal line 702 to achieve electrical interconnection between the optical sensor chip 301 and the substrate 100.
  • the lens module 302 is disposed above the image sensing chip 301 and is used to converge or guide a target optical signal to the image sensing chip 301.
  • the lens module 302 may be fixed by an adhesive 503 On the surface of the image sensor chip 301.
  • the lens module 302 may specifically include a lens barrel 303, an optical lens 304, and a filter 305; wherein the optical lens 304 and the filter 305 are accommodated and disposed It is inside the lens barrel 303, and the filter 305 is located between the optical lens 304 and the image sensor chip 301.
  • the optical lens 304 is mainly used to converge or guide the target optical signal.
  • the filter 305 may be an infrared filter, which is mainly used to isolate infrared interference light or other interference light from the external environment. This prevents the interference light from causing interference with the optical imaging of the image sensor chip 301.
  • the bottom of the lens barrel 303 may be adhered to the periphery of the optical sensing array of the image sensing chip 301 by an adhesive 503, and the pad 602 is located on the mirror.
  • the outside of the barrel 303 is connected with a wire for facilitating the wire 702.
  • the auxiliary module 200 includes an optical auxiliary chip 201, a capacitor 202 and a plastic sealing compound 203.
  • the optical auxiliary chip 201 may be one or more, which may be an auxiliary chip for assisting the image sensing module 300 to perform optical fingerprint detection or other types of optical detection.
  • the optical assistant chip 201 may be on the lower surface of the substrate 100.
  • the optical assistant chip 201 may be fixed and fixed on the lower surface of the substrate 100 by an adhesive 501, and after the optical assistant chip 201 is attached, The main surface faces away from the lower surface of the substrate 100.
  • a pad 601 is further provided on the edge region of the main surface of the optical assistant chip 201, and the pad 601 is connected to an electrical connection point with the lower surface of the substrate 100 through a metal wire 701, and the metal wire 701 is used to achieve all
  • the optical auxiliary chip 201 is electrically interconnected with a connection line of the substrate 100.
  • the capacitors 202 may be disposed on the lower surface of the substrate 100 and located on the edge of the substrate 100.
  • the capacitors 202 may be The surface mount (SMT) method is soldered and fixed to the lower surface of the substrate 100.
  • the solder 801 can be used as an electrical connection medium, so that the capacitor 202 can be connected to the electrical connection point on the lower surface of the substrate 100.
  • the plastic sealing material 203 covers the optical auxiliary chip 201 and the capacitor 202 to seal the optical auxiliary chip 201 and the capacitor 202 on the lower surface of the substrate 100 while protecting the optical auxiliary chip 201. And the capacitor 202.
  • the plastic sealing compound 203 can not only seal the components on the lower surface of the substrate 100 (including the optical assistant chip 201, the capacitor 202, the metal wire 701, etc.), but also provide a higher level for subsequent processes.
  • the flatness of the plastic packaging material 203 may be an epoxy resin material or an organic insulating material.
  • the connector 400 is mainly used for the chip package structure to be electrically connected with an external unit (such as a control unit, a processing unit, or other electrical components of an electronic device), so as to realize the image sensing module 300 and the external unit. Communication function to achieve fingerprint authentication or other functions.
  • the connector 400 is disposed on the upper surface of the substrate 100 and is located at an edge portion of the substrate 100.
  • the connector 400 may be surface-mounted by means of solder 802.
  • the solder is fixed on the substrate 100, wherein the solder 802 is connected to an electrical connection point on the upper surface of the substrate 100, which can be used as an electrical connection medium to realize the electrical interaction between the connector 400 and the substrate 100. even.
  • the adhesives 501, 502, and 503 may be adhesive substances such as glue or film, which are respectively used to attach the optical fingerprint assistant chip 201 and the image sensing chip 301. To the corresponding surface of the substrate 100, and attaching the lens barrel 303 to the image sensor chip 301 or the upper surface of the substrate 100.
  • the pad 601 of the optical assistant chip 201 is connected to the electrical connection point on the lower surface of the substrate 100 through the metal wire 701 and a wire bonding process, so as to implement the optical assistant.
  • the chip 201 is electrically connected to the substrate 100.
  • the pad 602 of the image sensing chip 301 is connected to the electrical connection point on the upper surface of the substrate 100 through the metal wire 702 and a wire bonding process, so that the image sensing chip 301 and the The electrical connection of the substrate 100 is described.
  • the metal lines 701 and 702 are electrical connection media of the chip package structure, and may specifically be metals having good conductivity, such as aluminum, copper, nickel, silver, and gold.
  • the pads 601 and 602 can be understood as the pins of the optical auxiliary chip 201 and the image sensing chip 301 connected to the substrate 100. It should be noted that one of the surfaces of the optical auxiliary chip 201 and the image sensing chip 301 may be prepared with the pads 601 and 602, respectively. As shown in FIG. 1, another of the optical auxiliary chip 201 and the image sensing chip 301 is prepared in advance. A surface is configured to be attached to the lower surface or the upper surface of the substrate 100. In the disclosed embodiment, as described above, the capacitor 202 can be bonded to the edge portion of the lower surface of the substrate 100 by using SMT process and solder 801, and the electrical connection point with the substrate 100 by solder 801 The capacitor 202 is electrically connected to the substrate 100 at this time.
  • the image sensing module 300 may be provided with one or more image sensing chips 301 according to actual needs.
  • the image sensing module 300 may include one or more lens modules 302 to cooperate with The one or more image sensing chips 301 perform optical imaging.
  • the image sensing module 300 uses multiple image sensing chips 301, at least some of the image sensing chips 301 can share a lens module 302.
  • the image sensing chip 301 is directly attached to the upper surface of the substrate 100.
  • the image sensing chip 301 may also be embedded using an embedded process.
  • an area on the upper surface of the substrate 100 for setting the image sensing chip 301 may be formed with a groove, and the image sensing chip 301 may be at least partially accommodated in The inside of the groove is adhered and fixed to the bottom surface of the groove, and the integration of the chip package structure is further improved by using the above manner.
  • the lens module 302 may be attached to the upper surface of the image sensor chip 301 by an adhesive 503. In other alternative embodiments, the lens module 302 may be attached to the upper surface of the image sensor chip 301.
  • the upper surface of the substrate 100 that is, the step of the lens barrel 303 is connected to the periphery of the image sensor chip 301 and is fixed to the substrate surface outside the image sensor chip 301.
  • the application method of the lens module 302 is not particularly limited, as long as the optical lens 304 and the filter 305 and the optical sensor array of the image sensor chip 301 can be optically aligned and set. .
  • the optical lens 304 and the filter 305 may be provided separately. As shown in FIG. 1, the filter 305 is located below the optical lens 304, and the optical lens 304 and the filter may also be disposed.
  • the sheets 305 are integrated together, or the filter 305 may be attached to the surface of the optical sensing array of the image sensing chip 301.
  • the lens module 302 of the image sensing module 300 may be provided with one or more optical lenses 304 according to actual needs.
  • the optical lens 304 may be a lens, such as an aspheric lens.
  • the optical lens 304 may also be replaced by an optical path collimator or other optical path modulator, and the optical lens 304 and the filter 305 may also be directly attached or integrated into the image.
  • the sensor module 301 has a surface or an inside, so that the lens barrel 303 does not need to be additionally provided.
  • an embodiment of the present disclosure further provides a chip packaging method.
  • the chip packaging method can be used to fabricate the chip packaging structure shown in FIG. 1.
  • FIG. 2 is a flowchart of a chip packaging method according to an embodiment of the present disclosure.
  • FIGS. 3 to 9 the fabrication of the chip packaging structure described in conjunction with FIGS. 3 to 9 is described below.
  • the schematic diagram of the process describes the chip packaging method shown in FIG. 2.
  • 3 is a schematic diagram of a substrate used in the chip packaging method
  • FIG. 4 is a schematic diagram of placing an optical auxiliary chip on a lower surface of the substrate
  • FIG. 5 is a schematic diagram of attaching a capacitor to a lower surface of the substrate; and
  • FIG. 6 is a plastic package A schematic diagram of plastic packaging the optical auxiliary chip and the capacitor on the lower surface of the substrate;
  • FIG. 7 is a schematic diagram of the image sensor chip disposed on the upper surface of the substrate;
  • FIG. 8 is a schematic diagram of the lens module disposed above the image sensor chip; Schematic diagram of attaching a connector to a substrate.
  • the chip packaging method mainly includes the following steps:
  • Step S101 providing a substrate for chip packaging, processing a required circuit on the substrate, and designing it to a required size;
  • the substrate 100 provided in step S101 may be a PCB substrate, a silicon substrate with TSV, a ceramic substrate, or an organic material.
  • the substrate 100 may be ground to a required size, including Length, width, thickness, etc., and then the required functional circuits (or auxiliary circuits) and connection lines are made by an etching process, and various electrical connection points are made in a predetermined area on the surface of the substrate 100, for the subsequent substrate 100 Prepare a typical connection with the chip or module to be packaged.
  • Step S102 attach an optical auxiliary chip to a lower surface of the substrate
  • one or more optical auxiliary chips 201 may be attached to the lower surface of the substrate 100 in a flip-chip manner by using an adhesive 501, and the substrates 100 may be bonded by a wire bonding process.
  • the pads 601 of the optical auxiliary chip 201 and the electrical connection points on the lower surface of the substrate 100 are electrically connected through a metal wire 701.
  • the adhesive 501 may be an adhesive material such as glue or an adhesive film, as long as the optical auxiliary chip 201 can be attached to the lower surface of the substrate 100.
  • the pad 601 of the optical auxiliary chip 201 can be understood as a pin connected to the optical auxiliary chip 201 and the substrate 100. It should be noted that before the optical auxiliary chip 201 is bonded to the substrate 100, the main surface (non-adhering surface) of the optical auxiliary chip 201 has been prepared with the pad 601 in advance. Therefore, in step S102, after the optical auxiliary chip 201 is attached to the lower surface of the substrate 100, a metal wire bonding process may be directly used to connect the pad 601 of the optical auxiliary chip 201 to the substrate through a metal wire 701. 100 electrical connection points on the lower surface.
  • Step S103 solder the capacitor to a lower surface edge region of the substrate
  • the capacitor 202 may be one or more, which may be SMT process and soldered to the lower surface edge region of the substrate 100 through a solder 801, wherein the solder 801 In addition to welding and fixing the capacitor 202 and the substrate 100, it also serves as an electrical connection medium to realize the electrical connection between the capacitor 202 and the electrical connection point on the lower surface of the substrate 100.
  • the capacitor 202 can also be soldered to the lower surface edge region of the substrate 100 before performing the step.
  • the optical auxiliary chip 201 is bonded and wired.
  • step S104 the optical auxiliary chip and the capacitor are sealed on the lower surface of the substrate by a plastic sealing material
  • a plastic sealing material 203 may be used and the optical auxiliary chip 201 and the optical auxiliary chip 201 and The capacitor 202 is sealed on the lower surface of the substrate 100 together with the pad 601, the metal line 701, the solder 801, and the like.
  • the plastic sealing material 203 may be an epoxy resin material or an organic insulating material.
  • Step S105 attach the image sensor chip to the upper surface of the substrate
  • the image sensor chip 301 may be attached to the main body of the upper surface of the substrate 100 by using an adhesive 502.
  • the adhesive 502 may also be glue or glue.
  • Adhesive materials such as films; and then, a wire bonding process is used to electrically connect the pads 602 of the image sensing chip 301 and the electrical connection points on the upper surface of the substrate 100 through metal wires 702.
  • the image sensing chip 301 may be a CIS chip having an optical sensing array, and the pad 602 may be fabricated in an edge area on the surface of the image sensing chip 301 in advance. Therefore, in step S105, After the image sensing chip 301 is attached to the upper surface of the substrate 100, a metal wire process can be directly used to connect the pad 602 of the optical image sensing chip 301 to the upper surface of the substrate 100 through a metal wire 702. Electrical connection point.
  • Step S106 setting a lens module above the image sensor chip
  • step S106 first, an optical lens 304 and a filter 305 are disposed inside the lens barrel 303 to form a lens module.
  • the filter 305 is disposed below the optical lens 304.
  • the optical lens 304 may include at least one aspheric lens.
  • the lens module is adhered to the surface of the image sensor chip 301 through an adhesive 503; specifically, the bottom of the lens barrel 303 of the lens module may be adhered to the image sensor chip 301.
  • the peripheral surface of the optical sensing array of the chip 301, and the bonding position of the lens module needs to ensure that the optical lens 304 and the filter 305 are aligned with the optical sensing array of the image sensing chip 301 .
  • Step S107 solder the connector to the substrate for the chip package structure to be electrically connected to an external unit
  • the connector 400 is mainly used to provide a connection port or a connection medium for the electrical connection between the chip package structure and an external unit.
  • the connector 400 may be used to implement all
  • the communication function between the image sensing chip 301 and an external unit can be SMT process and soldered to the upper surface edge portion of the substrate 100 through a solder 802, wherein the solder 802 except for the connector 400 and the substrate
  • it also serves as an electrical connection medium to achieve the electrical connection between the connector 400 and the electrical connection point on the upper surface of the substrate 100.
  • the chip packaging structure shown in FIG. 1 can be manufactured through the above steps.
  • step S107 may be performed before step S105.
  • the connector 400 and / or the image on the upper surface of the substrate 100 The sensor module may also be attached and mounted, and then the capacitor 202 and the optical auxiliary chip 201 on the lower surface of the substrate 100 may be attached.
  • the step S107 of the chip packaging method provided in the above embodiment is to mount the connector 400 to the upper surface of the substrate 100 where the image sensing chip 301 is located by a surface mount process
  • the connector 400 may also be mounted on the lower surface of the substrate 100 where the optical assistant chip 201 is located with the capacitor 202 by surface mounting or other processes.
  • the connector 400 can also be attached to one side of the substrate 100 by a single mounting step. In this case, the side of the substrate 100 needs to be made with a corresponding connection end in advance for all The connector 400 is attached and mounted.
  • FIG. 10 is a schematic diagram of a chip package structure according to another embodiment of the present disclosure.
  • the chip package structure shown in FIG. 10 is similar to the chip package structure shown in FIG. 1.
  • the main difference is that the substrate 100 of the chip package structure shown in FIG. 10 uses a silicon substrate with a through silicon via (TSV). Instead of the metal lines 701 and 702 of the chip package structure shown in FIG. 1.
  • TSV through silicon via
  • the pads of the image sensing chip 301 may be disposed at the bottom, that is, the bonding surface with the upper surface of the substrate 100, and soldered to the substrate 100 through solder 502.
  • the pads of the image sensing chip 301 may be connected to the through silicon vias of the substrate 100, and further, the connection lines between the through silicon vias and the substrate 100 or other parts of the chip package structure Electrical components (such as the optical assistant chip 201 or the connector 400) are electrically connected.
  • the image sensing chip 301 and the connector 400 are both fixed to the upper surface of the substrate 100 by soldering, the image sensing chip 301 and the connector 400 can be connected through the same connection process ( (Such as a surface mount process) to achieve soldering to the upper surface of the substrate 100 while performing electrical connection, thereby reducing process steps.
  • the pads of the optical auxiliary chip 201 can also be provided on the bonding surface of the optical assistant chip 201 and the substrate 100, and soldered to the lower surface of the substrate 100 by a flip-chip soldering process using solder 501.
  • at least a part of the pads of the optical auxiliary chip 201 may be connected to a through silicon via of the substrate 100, and further, a connection line between the through silicon via and the substrate 100 or other electrical properties of the chip package structure.
  • the components (such as the image sensing chip 301, the connector 400, and the capacitor 201) are electrically connected.
  • the optical auxiliary chip 201 and the capacitor 202 are both fixed and electrically interconnected by solder, the optical auxiliary chip 201 and the capacitor 202 can be simultaneously soldered to each other through the same flip-chip welding process.
  • the lower surface of the substrate 100 is electrically connected, thereby reducing process steps.
  • FIG. 11 is a flowchart of a chip packaging method according to an embodiment of the present disclosure.
  • the chip packaging method can be used to prepare the chip packaging structure shown in FIG. 10.
  • the chip packaging method specifically includes:
  • S204 Adopt an SMT process to attach the image sensing chip and the connector to the upper surface of the substrate, and connect to the electrical connection point on the upper surface of the substrate through solder. At least part of the pads of the image sensing chip A through-silicon via connected to the substrate through the solder;
  • the image sensing chip and the image sensing chip may be electrically connected through the through silicon vias of the substrate, that is, the image sensing chip on the upper surface of the substrate has at least A pad is electrically connected through the through silicon via and an optical auxiliary chip on the lower surface of the substrate.
  • S205 The lens module is attached to the image sensor chip by an adhesive, and the optical lens of the lens module is aligned with the image sensor chip.
  • the image sensing chip and the connector may be connected to the upper surface of the substrate through the same surface mount process; in other alternative embodiments, the connection The device can also be connected to the lower surface of the substrate through the same surface mounting process with the optical auxiliary chip, thereby reducing the process steps.
  • the connector may also be connected to one side of the substrate by using a separate laminating step.
  • an embodiment of the present disclosure further provides an electronic device, the electronic device includes a display screen and an optical fingerprint detection device disposed below the display screen, wherein the The optical fingerprint detection device may include a chip package structure as described in the above embodiments.
  • the display screen may be an OLED display screen or an LCD display screen.
  • the optical fingerprint detection device may use a part of the display pixels of the OLED display screen as an excitation light source for optical fingerprint detection.
  • the optical fingerprint detection device may be configured with an additional light source as an excitation light source for optical fingerprint detection.

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Abstract

本公开涉及芯片封装技术领域，公开了一种芯片封装结构、方法和电子设备。所述芯片封装结构包括基板、连接器、影像传感模块和辅助模块，所述影像传感模块和所述辅助模块利用所述基板进行一体式封装；所述影像传感模块包括影像传感芯片，所述影像传感芯片封装在所述基板的第一表面；所述辅助模块包括至少一个光学辅助芯片，所述至少一个光学辅助芯片封装在所述基板的第二表面，并通过所述基板与所述影像传感芯片进行电性连接；所述连接器连接在所述基板上，用于供所述芯片封装结构与外界单元进行电性连接。本公开实施例可以提高芯片封装模组的集成度并降低模组的总体积。

Description

芯片封装结构、方法和电子设备 技术领域
本公开涉及芯片封装技术领域，并且更具体地，涉及一种芯片封装结构、方法和电子设备。
背景技术
伴随着科学技术的进步以及用户需求的逐步提升，电子设备的集成度越来越高。为了适应这种发展趋势，电子设备当中使用的各类元件、器件也面临着向集成度更高、体积更小、标准化程度更高的方向转变。
然而，光学指纹芯片作为具有光学指纹识别功能的电子设备的重要组成部分，受其封装方式的影响，集成度受到了很大的限制。当前的光学指纹芯片一般使用分离式的光学指纹模组封装方案，通常此类光学指纹模组的影像传感芯片、辅助芯片和连接器分别黏贴于不同的基板上，然后通过柔性电路板(Flexible Printed Circuit，FPC)将辅助模块、影像传感芯片模块、连接器等实现电连接。此类方式集成度低，体积大，并且难以实现标准化，难以满足市场需求。
发明内容
针对背景技术中的问题，本公开提供了一种芯片封装结构、方法和电子设备，有效提高了芯片封装集成度，减小了体积，同时提高了标准化程度。
第一方面，提供了一种芯片封装结构，包括：基板、连接器、影像传感模块和辅助模块，所述影像传感模块和所述辅助模块利用所述基板进行一体式封装；所述影像传感模块包括影像传感芯片，所述影像传感芯片封装在所述基板的第一表面；所述辅助模块包括至少一个光学辅助芯片，所述至少一个光学辅助芯片封装在所述基板的第二表面，并通过所述基板与所述影像传感芯片进行电性连接；所述连接器连接在所述基板上，用于供所述芯片封装结构与外界单元进行电性连接。
作为本公开提供的芯片封装结构的一种可选实现方案，所述连接器连接在所述基板的第一表面或者第二表面；具体地，所述影像传感芯片和所述至少一个光学辅助芯片分别设置在所述基板的第一表面和第二表面的主体部，且所述连接器连接在所述基板的第一表面或者第二表面的边缘部。
作为本公开提供的芯片封装结构的一种可选实现方案，所述基板还包括多个侧面，所述连接器设置在所述基板的其中一个侧面。
作为本公开提供的芯片封装结构的一种可选实现方案，所述第一表面为所述基板的主表面，所述第二表面为所述基板与所述主表面相背离的背面。
作为本公开提供的芯片封装结构的一种可选实现方案，所述影像传感模块还包括镜头模块，所述镜头模块设置在所述影像传感芯片的上方，用于将目标光信号会聚或者导引到所述影像传感芯片。
作为本公开提供的芯片封装结构的一种可选实现方案，所述镜头模块包括镜筒和收容在所述镜筒的光学镜头，所述影像传感芯片包括光学感应阵列，所述光学镜头与所述光学感应阵列进行光路对准设置。
作为本公开提供的芯片封装结构的一种可选实现方案，所述镜头模块还包括滤光片，所述滤光片收容在所述镜筒，并位于所述光学镜头和所述影像传感芯片之间，所述滤光片用于隔离外部干扰光以阻止其进入所述光学感应阵列。
作为本公开提供的芯片封装结构的一种可选实现方案，所述影像传感模块为光学指纹检测模块，所述目标光信号为从手指表面反射的指纹检测光，其中所述指纹检测光通过所述光学镜头会聚或者导引到所述影像传感芯片，所述影像传感芯片用于检测所述指纹检测光以进行光学指纹成像。
作为本公开提供的芯片封装结构的一种可选实现方案，所述影像传感芯片通过第一粘合剂贴合到所述基板的第一表面，且其表面的焊盘通过第一金属线连接到所述基板的第一表面的电连接点。
作为本公开提供的芯片封装结构的一种可选实现方案，所述光学辅助芯片通过第二粘合剂贴合到所述基板的第二表面，且其表面的焊盘通过第二金属线连接到所述基板的第二表面的电连接点，并且所述光学辅助芯片 通过所述基板的连接线路与所述影像传感芯片进行电性连接。
作为本公开提供的芯片封装结构的一种可选实现方案，所述基板为具有硅通孔的硅基板，所述影像传感芯片通过其底面的焊盘连接到所述硅基板的第一表面，且所述影像传感芯片的至少部分焊盘与所述硅基板的硅通孔进行电性连接。
作为本公开提供的芯片封装结构的一种可选实现方案，所述光学辅助芯片通过其底面的焊盘以倒装焊接方式连接到所述硅基板的第二表面，且所述光学辅助芯片的至少部分焊盘通过所述硅通孔与所述影像传感芯片进行电性连接。
作为本公开提供的芯片封装结构的一种可选实现方案，所述辅助模块还包括至少一个电容，所述至少一个电容通过焊锡连接到所述基板的第二表面的边缘区域。
作为本公开提供的芯片封装结构的一种可选实现方案，所述辅助模块还包括塑封料，所述塑封料将所述光学辅助芯片和所述至少一个电容密封在所述基板的第二表面，并使得所述芯片封装结构的表面平整。
第二方面，提供了一种芯片封装的方法，包括：提供用于芯片封装的基板，所述基板包括第一表面和第二表面；将影像传感芯片封装在所述基板的第一表面；将至少一个光学辅助芯片封装在所述基板的第二表面，其中，所述至少一个光学辅助芯片通过所述基板与所述影像传感芯片进行电性连接；将连接器连接到所述基板，以供所述芯片封装结构与外界单元进行电性连接。
作为本公开提供的芯片封装方法的一种可选实现方案，所述连接器连接在所述基板的第一表面或者第二表面；具体地，所述影像传感芯片和所述至少一个光学辅助芯片分别设置在所述基板的第一表面和第二表面的主体部，且所述连接器连接在所述基板的第一表面或者第二表面的边缘部。
作为本公开提供的芯片封装方法的一种可选实现方案，所述基板还包括多个侧面，所述连接器设置在所述基板的其中一个侧面。
作为本公开提供的芯片封装方法的一种可选实现方案，所述基板为具有硅通孔的硅基板，所述影像传感芯片和所述连接器通过同一次表面贴装 工艺连接到所述基板的第一表面；或者，所述连接器和所述至少一个光学辅助芯片通过同一次表面贴装工艺连接到所述基板的第二表面。
作为本公开提供的芯片封装方法的一种可选实现方案，所述方法还包括：将镜头模块贴合到所述影像传感芯片的上方，其中，所述镜头模块包括镜筒和收容在所述镜筒的光学镜头和滤光片，且所述镜头模块贴合之后所述光学镜头与所述影像传感芯片的光学感应阵列之间光路对准。
作为本公开提供的芯片封装方法的一种可选实现方案，所述将影像传感芯片封装在所述基板的第一表面的步骤包括：利用第一粘合剂将所述影像传感芯片贴合到所述基板的第一表面；采用打线工艺并通过第一金属线将所述影像传感芯片表面的焊盘与所述基板的第一表面的电连接点进行电性连接。
作为本公开提供的芯片封装方法的一种可选实现方案，所述将至少一个光学辅助芯片封装所述基板的第二表面的步骤包括：利用第二粘合剂将所述至少一个光学辅助芯片贴合到所述基板的第二表面；采用打线工艺并通过第二金属线将所述至少一个光学辅助芯片表面的焊盘与所述基板的第二表面的电连接点进行电性连接。
作为本公开提供的芯片封装方法的一种可选实现方案，所述基板为具有硅通孔的硅基板，且所述将影像传感芯片封装在所述基板的第一表面的步骤包括：通过所述影像传感芯片底面的焊盘将所述影像传感芯片连接到所述硅基板的第一表面，其中所述影像传感芯片的至少部分焊盘与所述硅基板的硅通孔进行电性连接。
作为本公开提供的芯片封装方法的一种可选实现方案，所述将至少一个光学辅助芯片封装所述基板的第二表面的步骤包括：通过所述至少一个光学辅助芯片底面的焊盘以倒装焊接方式将所述至少一个光学辅助芯片连接到所述硅基板的第二表面，其中所述至少一个光学辅助芯片的至少部分焊盘通过所述硅通孔与所述影像传感芯片进行电性连接。
作为本公开提供的芯片封装方法的一种可选实现方案，所述方法还包括：将至少一个电容连接到所述基板的第二表面的边缘区域；利用塑封料将所述至少一个光学辅助芯片和所述至少一个电容密封在所述基板的第二表面，并使得所述芯片封装结构的表面平整。
作为本公开提供的芯片封装方法的一种可选实现方案，所述至少一个电容和所述至少一个光学辅助芯片通过同一次表面贴装工艺连接到所述基板的第二表面。
第三方面，提供了一种电子设备，包括显示屏和位于所述显示屏下方的光学指纹检测装置，所述光学指纹检测装置包括如上所述的芯片封装结构。
本公开实施例通过将影像传感芯片和光学辅助芯片分别封装在基板的两个表面，实现所述影像传感芯片和所述光学辅助芯片的一体式封装，不仅可以减少芯片封装的步骤，提高芯片封装的集成度，并降低芯片封装模组的总体积，同时提高了芯片封装的标准化程度。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本公开的一个实施例的芯片封装结构示意图；
图2是根据本公开的一个实施例的芯片封装方法的流程图；
图3至图9是图1所示的芯片封装结构的制作工艺的示意图；
图10是根据本公开的另一个实施例的芯片封装结构示意图；
图11是根据本公开的另一个实施例的芯片封装方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1是根据本公开的一个实施例的芯片封装结构示意图。如图1所示，该芯片封装结构，包括：基板100、辅助模块200、影像传感模块300和连接器400。所述影像传感模块300、所述辅助模块200和所述连接器400 通过所述基板100来实现一体式的高集成度封装。
其中，所述基板100包括主表面、与所述主表面相背离的背面以及连接所述主表面和背面的多个侧面，更具体地，所述主表面和背面可以为分别为所述基板100的上表面和下表面。所述辅助模块200设置在所述基板100的下表面；所述影像传感模块300设置在所述基板100的上表面，并且位于所述基板100的主体部。
所述连接器400用于供所述芯片封装结构与外部单元进行电性连接，其可以具体设置在所述基板100的上表面或者下表面，比如，在一种实施例中，所述连接器400可以设置在所述基板100的上表面，并且位于基板100的边缘部，如图1所示；可替代地，在其他实施例中，所述连接器400也可以设置在所述基板100下表面的边缘部。或者，所述连接器400还可以连接在所述基板100的其中一个表面。也即是说，在本公开的实施例中，所述连接器400的安装方式和安装位置并不限于图1的结构；另外，所述连接器400的规格以及出线方式可以根据实际需要而定，本公开实施例也对此不做限定。
本公开实施例中，所述基板100可以为PCB基板、具有硅通孔(TSV)硅基板、陶瓷基板或有机材料基板等，其上表面和下表面可以同时用来进行芯片封装。比如，在图1所示的实施例中，所述影像传感模块300和所述连接器400封装在基板100的上表面，而所述辅助模块200封装在基板100的下表面。同时，所述基板100还可以包括所述芯片封装结构工作所需的功能电路(或辅助电路)以及相关的连接线路；并且，所述基板100表面还预先制作有多个电连接点，所述电连接点用于以普通焊接、倒装焊接、窄带自动焊或者金属引线键合等方式与所述辅助模块200、所述影像传感模块300和所述连接器400等进行电性连接。所述电连接点还可以与所述基板100内部的连接线路相连接，以实现所述芯片封装结构整体的电性互连。
所述影像传感模块300可以具体为光学指纹检测模块，且其可以包括影像传感芯片301和镜头模块302。其中，所述影像传感芯片301可以为CMOS图像传感器(CIS)芯片，其设置在基板100的上表面，并且位于基板100的主体部，比如，所述影像传感芯片301可以通过粘合剂502贴合固 定在基板100的上表面。
并且，所述影像传感芯片301包括位于其中间区域的光学感应阵列以及设置在边缘的焊盘602。所述光学感应阵列主要用于检测经由所述镜头模块302的目标光信号以实现光学成像，在具体实施例中，所述目标光信号可以为激励光源在手指反射而形成的指纹检测光，所述指纹检测光经过镜头模块302传输到所述影像传感芯片301的光学感应阵列，所述光学感应阵列可以检测所述指纹检测光以实现光学指纹成像。所述焊盘602可以通过金属线702连接至基板100上表面的电连接点，以实现所述光学感应芯片301与所述基板100的电性互连。
所述镜头模块302设置在所述影像传感芯片301的上方，用于将目标光信号会聚或者导引到所述影像传感芯片301；比如，所述镜头模块302可以通过粘合剂503固定在所述影像传感芯片301的表面。在一种实施例中，如图1所示，所述镜头模块302可以具体包括镜筒303、光学镜头304和滤光片305；其中，所述光学镜头304和所述滤光片305收容设置在所述镜筒303的内部，并且所述滤光片305位于所述光学镜头304和所述影像传感芯片301的之间。所述光学镜头304主要用于对所述目标光信号进行光路会聚或者导引，所述滤光片305可以为红外滤光片，其主要用于隔离外界环境的红外干扰光或者其他干扰光，以避免上述干扰光对所述影像传感芯片301的光学成像造成干扰。
在图1所示的实施例中，所述镜筒303的底部可以通过粘合剂503贴合在所述影像传感芯片301的光学感应阵列的外围，并且所述焊盘602位于所述镜筒303的外侧与便于所述金属线702的打线连接。
所述辅助模块200包括光学辅助芯片201、电容202和塑封料203。其中，所述光学辅助芯片201可以是一个或者多个，其可以为用于辅助所述影像传感模块300进行光学指纹检测或者其他类型的光学检测的辅助芯片。所述光学辅助芯片201可以在基板100的下表面，比如，所述光学辅助芯片201可以通过粘合剂501贴合固定在基板100的下表面，且在所述光学辅助芯片201贴合之后其主表面背离所述基板100的下表面。所述光学辅助芯片201的主表面边缘区域还设置有焊盘601，所述焊盘601通过金属线701连接至与所述基板100下表面的电连接点，并通过所述金属线 701实现所述光学辅助芯片201与所述基板100的连接线路的电性互连。
所述电容202可以有一个或多个，具体数目可以根据实际电路设计需要而定，其设置在基板100的下表面，并且位于基板100的边缘部，比如，所述电容202可以通过焊锡801以表面贴装(SMT)的方式焊接固定在基板100的下表面。所述焊锡801可以作为电性连接介质，实现所述电容202与基板100下表面的电连接点相连。
所述塑封料203覆盖所述光学辅助芯片201和所述电容202，用以将所述光学辅助芯片201和所述电容202密封在所述基板100的下表面，同时保护所述光学辅助芯片201和所述电容202。所述塑封料203不仅可以实现所述基板100下表面的元部件(包括所述光学辅助芯片201、所述电容202和所述金属线701等)的密封，同时也为后续工艺提供了较高的平整度，其中所述塑封料203可以为环氧树脂材料或者有机绝缘材料等。
所述连接器400主要用于供所述芯片封装结构与外部单元(比如电子设备的控制单元、处理单元或者其他电学部件)进行电性连接，以实现所述影像传感模块300与外部单元的通信作用，从而实现指纹认证或者其他功能。在图1所示的实施例中，所述连接器400设置在基板100的上表面，并且位于所述基板100的边缘部，比如，所述连接器400可以通过焊锡802以表面贴装的方式焊接固定在所述基板100，其中，所述焊锡802与所述基板100上表面的电连接点相连，其可以作为电性连接介质，实现所述连接器400与所述基板100的电性互连。
在本公开的实施例中，所述粘合剂501、502、503可以为胶水或者胶膜等具有粘合性的物质，其分别用于将光学指纹辅助芯片201和影像传感芯片301贴合到基板100相应的表面，以及将镜筒303贴合在影像传感芯片301或者基板100的上表面。
在图1所示的实施例中，所述光学辅助芯片201的焊盘601通过所述金属线701并采用打线工艺连接至所述基板100下表面的电连接点，从而实现所述光学辅助芯片201与所述基板100的电性连接。相类似地，所述影像传感芯片301的焊盘602通过所述金属线702并采用打线工艺连接至所述基板100上表面的电连接点，从而实现所述影像传感芯片301与所述基板100的电性连接。其中，所述金属线701和702为所述芯片封装结构 的电性连接介质，具体地可以为铝、铜、镍、银、金等具有良好导电性的金属。
其中，所述焊盘601和602可以理解为所述光学辅助芯片201和所述影像传感芯片301与所述基板100连接的管脚。需要说明的是，光学辅助芯片201和影像传感芯片301的其中一个表面可以分别预先制备有所述焊盘601和602，如图1所示，光学辅助芯片201和影像传感芯片301的另一个表面，用以与所述基板100的下表面或者上表面贴合。在公开的实施例中，如上述描述，所述电容202可以采用SMT工艺并通过焊锡801贴合到所述基板100的下表面的边缘部分，并通过焊锡801与所述基板100的电连接点相连，其中，此时所述电容202与所述基板100实现电性连接。
另一方面，所述影像传感模块300可以根据实际需求设置一颗或多颗影像传感芯片301，相对应地，所述影像传感模块300可以包括一个或多个镜头模块302来配合所述一颗或多颗影像传感芯片301进行光学成像。或者，所述影像传感模块300采用多颗影像传感芯片301时，其中至少部分影像传感芯片301可以共享一个镜头模块302。在图1所示的实施例中，所述影像传感芯片301直接贴合设置在所述基板100的上表面，可替代地，所述影像传感芯片301也可以采用埋入式工艺埋入到所述基板100的上表面，具体地，所述基板100的上表面用来设置所述影像传感芯片301的区域可以形成有凹槽，且所述影像传感芯片301可以至少部分收容在所述凹槽内部并与所述凹槽的底面进行贴合固定，采用上述方式进一步提高所述芯片封装结构的集成度。
在图1所示的实施例中，所述镜头模块302可以通过粘合剂503贴合到所述影像传感芯片301的上表面；在其他替代实施例中，镜头模块302也可以贴合到所述基板100的上表面，即所述镜筒303的地步跨接在所述影像传感芯片301的外围并与所述影像传感芯片301外侧的基板表面进行贴合固定。本申请对所述镜头模块302的贴合方式无特殊限制，只要能够将所述光学镜头304和所述滤光片305与所述影像传感芯片301的光学感应阵列进行光路对准设置即可。所述光学镜头304和所述滤光片305可以分开设置，如图1所示，所述滤光片305位于所述光学镜头304的下方，也可以将所述光学镜头304和所述滤光片305集成在一起，或者，所述滤 光片305也可以贴合在所述影像传感芯片301的光学感应阵列表面。
在具体实施例中，所述影像传感模块300的镜头模块302可以根据实际需求设置一片或多片光学镜头304，所述光学镜头304可以具体为透镜，比如非球面透镜。在其他替代实施例中，所述光学镜头304还可以采用光路准直器或者其他光路调制器来代替，所述光学镜头304和所述滤光片305还可以直接贴合或者集成到所述影像传感模块301表面或者内部，从而不需要额外设置所述镜筒303。
基于图1所示的芯片封装结构，本公开实施例还提供一种芯片封装方法，所述芯片封装方法可以用于制作如图1所示的芯片封装结构。请参阅图2，其是根据本公开的一个实施例的芯片封装方法的流程图，为更好地理解本公开提供的芯片封装方法，下面结合图3至图9所述的芯片封装结构的制作工艺的示意图，对图2所示的芯片封装方法的进行描述。其中，图3为所述芯片封装方法采用的基板的示意图；图4为将光学辅助芯片设置在基板下表面的示意图；图5是将电容贴合到基板下表面的示意图；图6是采用塑封料将光学辅助芯片和电容塑封在基板下表面的示意图；图7是将影像传感芯片设置在基板上表面的示意图；图8是将镜头模块设置在影像传感芯片上方的示意图；图9是将连接器贴合到基板的示意图。
具体地，所述芯片封装方法主要包括以下步骤：
步骤S101，提供用于芯片封装的基板，并在所述基板加工所需电路，并设计为所需尺寸；
请参阅图3，步骤S101提供的基板100可以为PCB基板、具有TSV的硅基板、陶瓷基板或者有机材料基本等，在步骤S101中，可以先将所述基板100研磨至所需要的尺寸，包括长度、宽度和厚度等，再通过蚀刻工艺制作所需要的功能电路(或辅助电路)以及连接线路，同时在所述基板100的表面的预定区域制作各种电连接点，为后续所述基板100与待封装的芯片或者模组进行典型连接做准备。
步骤S102，将光学辅助芯片贴合到所述基板的下表面；
请参阅图4，在步骤S102中，可以通过粘合剂501将一颗或者多个光学辅助芯片201以倒装封装的方式贴合到所述基板100的下表面，并采用打线工艺将所述光学辅助芯片201的焊盘601与所述基板100下表面的电 连接点通过金属线701进行电性连接。
所述粘合剂501可以为胶水或者胶膜等具有粘合性的材料，只要可以将所述光学辅助芯片201贴合到所述基板100的下表面即可。所述光学辅助芯片201的焊盘601可以理解为所述光学辅助芯片201与所述基板100连接的管脚。需要说明的是，在所述光学辅助芯片201与所述基板100进行贴合之前，所述光学辅助芯片201的主表面(非贴合面)已经预先制备有所述焊盘601，因此，在步骤S102中，在所述光学辅助芯片201贴合在所述基板100的下表面之后，可以直接采用金属打线工艺将所述光学辅助芯片201的焊盘601通过金属线701连接至所述基板100的下表面的电连接点。
步骤S103，将电容焊接到所述基板的下表面边缘区域；
请参阅图5，具体地，在步骤S103中，所述电容202可以为一个或多个，其可以采用SMT工艺并通过焊锡801焊接到所述基板100的下表面边缘区域，其中所述焊锡801除了进行所述电容202和所述基板100的焊接固定以外，还同时作为电性连接介质，实现所述电容202与所述基板100下表面的电连接点的电性连接。
应当理解，在实际工艺过程中，步骤S102和步骤S103并没有严格的前后顺序，也即是说，所述电容202也可以先焊接到所述基板100的下表面边缘区域，然后再进行所述光学辅助芯片201的贴合和打线连接。
步骤S104，通过塑封料将所述光学辅助芯片和所述电容密封在所述基板的下表面；
具体地，请参阅图6，在所述光学辅助芯片201和所述电容202固定在所述基板100之后，在步骤S104中，可以采用塑封料203并利用塑封工艺将所述光学辅助芯片201和所述电容202连同所述焊盘601、所述金属线701、所述焊锡801等密封在所述基板100的下表面。所述塑封料203可以为环氧树脂材料或者有机绝缘材料等，在步骤S104执行之后，不仅完成了所述基板100的下表面密封，同时也为后续工艺提供了较高的平整度。
步骤S105，将影像传感芯片贴合到所述基板的上表面；
请参阅图7，在步骤S105中，首先可以利用粘合剂502将所述影像传 感芯片301贴合到所述基板100上表面的主体部，所述粘合剂502同样可以为胶水或者胶膜等具有粘合性的材料；接着，采用打线工艺将所述影像传感芯片301的焊盘602与所述基板100上表面的电连接点通过金属线702进行电性连接。
所述影像传感芯片301可以具体为具有光学感应阵列的CIS芯片，其中所述焊盘602可以预先制作在所述影像传感芯片301表面的边缘区域，因此，在步骤S105中，在所述影像传感芯片301贴合在所述基板100的上表面之后，可以直接采用金属打线工艺将所述光影像传感芯片301的焊盘602通过金属线702连接至所述基板100的上表面的电连接点。
步骤S106，将镜头模块设置在所述影像传感芯片的上方；
请参阅图8，在步骤S106中，首先，将光学镜头304和滤光片305设置在镜筒303内部来形成镜头模块，其中所述滤光片305设置在所述光学镜头304的下方，所述光学镜头304可以包括至少一片非球面透镜。接着，通过粘合剂503将所述镜头模块贴合到所述影像传感芯片301的表面；具体而言，可以将所述镜头模块的镜筒303的底部贴合到与所述影像传感芯片301的光学感应阵列的外围表面，并且所述镜头模块的贴合位置需要保证所述光学镜头304和所述滤光片305与所述影像传感芯片301的光学感应阵列进行光路对准设置。
步骤S107，将连接器焊接到所述基板，以供所述芯片封装结构与外部单元的电性连接；
具体地，请参阅图9，所述连接器400主要用于为所述芯片封装结构与外部单元之间的电性连接提供一个连接端口或者连接媒介，比如所述连接器400可以用于实现所述图像传感芯片301与外部单元的通信作用，其可以采用SMT工艺并通过焊锡802焊接到所述基板100的上表面边缘部，其中所述焊锡802除了进行所述连接器400和所述基板100的焊接固定以外，还同时作为电性连接介质，实现所述连接器400与所述基板100上表面的电连接点的电性连接。
在本公开上述实施例提供的芯片封装方法中，通过上述步骤，便可以制作出如图1所示的芯片封装结构。
应当理解，虽然上述实施例以影像传感模组的影像传感芯片301和镜 头模块先贴合到所述基板100之后再进行所述连接器400的焊接固定，在替他替代实施例中，所述连接器400也可以先焊接到所述基板100之后再进行所述影像传感芯片301和镜头模块的贴合固定，即步骤S107也可以在步骤S105之前执行。
除此以外，所属技术领域的技术人员可以知悉，实际上本实施例提供的芯片封装方法的大多数步骤并没有严格的前后顺序，比如，所述基板100上表面的连接器400和/或影像传感模组也可以先进行贴合安装，然后再进行所述基板100下表面的电容202以及光学辅助芯片201的贴合。
另一方面，虽然上述实施例提供的芯片封装方法的步骤S107是通过表面贴装工艺将所述连接器400安装到所述影像传感芯片301所在的所述基板100的上表面，在另一种实施例中，所述连接器400也可以通过表面贴装或者其他工艺与所述电容202安装到所述光学辅助芯片201所在的所述基板100的下表面。或者，所述连接器400也可以采用单独一个贴装步骤贴合到所述基板100的其中一个侧面，在这种情况下，所述基板100的侧面需要预先制作有相应的连接端以供所述连接器400进行贴合安装。
请参阅图10，其是根据本公开的另一个实施例的芯片封装结构示意图。图10所示的芯片封装结构与图1所示的芯片封装结构相类似，主要区别在于，在图10所示的芯片封装结构的基板100采用的是具有硅通孔(TSV)的硅基板，来代替图1所示的芯片封装结构的金属线701和702。
在图10所示的芯片封装结构中，影像传感芯片301的焊盘可以设置在底部，即其与所述基板100上表面的贴合面，并通过焊锡502焊接到所述基板100的上表面，所述影像传感芯片301的至少部分焊盘可以连接到所述基板100的硅通孔，并进一步通过所述硅通孔与所述基板100的连接线路或者所述芯片封装结构的其他电学元部件(比如光学辅助芯片201或连接器400等)进行电性连接。由于所述影像传感芯片301与所述连接器400均是通过焊锡焊接固定到所述基板100的上表面，因此所述影像传感芯片301与所述连接器400可以通过同一次连接工艺(比如表面贴装工艺)来实现焊接到所述基板100的上表面同时进行电性连接，从而减少工艺步骤。
相类似的，所述光学辅助芯片201的焊盘也同样可以设置在其与所述 基板100的贴合面，并通过焊锡501利用倒装焊接工艺焊接到所述基板100的下表面。并且，所述光学辅助芯片201的至少部分焊盘可以连接到所述基板100的硅通孔，并进一步通过所述硅通孔与所述基板100的连接线路或者所述芯片封装结构的其他电学元部件(比如所述影像传感芯片301、所述连接器400和电容201等)进行电性连接。由于所述光学辅助芯片201与所述电容202均是通过焊锡进行焊接固定及电性互连，因此所述光学辅助芯片201与所述电容202可以通过同一次倒装焊接工艺来实现同时焊接到所述基板100的下表面并进行电性连接，从而减少工艺步骤。
基于图10所示的芯片封装结构，本公开还进一步提供另一种芯片封装方法，图11是根据本公开的一个实施例的芯片封装方法的流程图。所述芯片封装方法可以用于制备图10所示的芯片封装结构。所述芯片封装方法具体包括：
S201，给基板上加工所需电路，并设计为所需尺寸；
S202，采用SMT工艺将光学辅助芯片和电容贴合到所述基板的下表面，并通过焊锡与所述基板下表面的电连接点相连，其中所述光学辅助芯片的至少部分焊盘通过所述焊锡连接到所述基板的硅通孔；
S203，采用塑封工艺通过塑封料将所述光学辅助芯片和所述电容密封在所述基板的下表面；
S204，采用SMT工艺将影像传感芯片和连接器贴合到所述基板的上表面，并通过焊锡与所述基板上表面的电连接点相连，其中所述影像传感芯片的至少部分焊盘通过所述焊锡连接到所述基板的硅通孔；
在步骤S204中，所述影像传感芯片与所述影像传感芯片之间可以通过所述基板硅通孔实现电性连接，也即是说，所述基板上表面的影像传感芯片至少有一个焊盘通过所述硅通孔和所述基板下表面的光学辅助芯片进行电性连接。
S205，通过粘合剂将镜头模块贴合到所述影像传感芯片的上方，且所述镜头模块的光学镜头与所述影像传感芯片对准设置。
在图11所示的芯片封装方法中，所述影像传感芯片与所述连接器可以通过同一次表面贴装工艺来连接到所述基板的上表面；在其他替代实施例中，所述连接器也可以与所述光学辅助芯片通过同一次表面贴装工艺来 连接到所述基板的下表面，从而减少工艺步骤。或者，所述连接器也可以采用单独的一个贴合步骤来连接到所述基板的其中一个侧面。
本公开上述各个实施例提供的芯片封装结构可以适用于光学指纹检测装置的芯片封装，特别适用于具有屏下光学指纹检测装置的电子设备。具体地，基于上述实施例提供的芯片封装结构，本公开实施例还进一步提供一种电子设备，所述电子设备包括显示屏和设置在所述显示屏下方的光学指纹检测装置，其中，所述光学指纹检测装置可以包括如以上实施例描述的芯片封装结构。更具体地，所述显示屏可以为OLED显示屏或者LCD显示屏，当采用OLED显示屏时，所述光学指纹检测装置可以利用所述OLED显示屏的部分显示像素来作为光学指纹检测的激励光源；而当采用LCD显示屏时，所述光学指纹检测装置可以配置额外的光源来作为光学指纹检测的激励光源。
虽然本公开文件包含许多细节，但是这些不应被解释为对任何发明或要求保护的范围的限制，而是被解释为可以是对特定发明的特定实施例所特有的特征的描述。本专利文件中描述的某些特征在单独实施例的上下文中还可以在单个实施例中组合实现。相反，在单个实施例的上下文中描述的各种特征还可以在多个实施例中单独实现或以任何合适的子组合形式实现。而且，虽然特征可以在上面描述为在某些组合中起作用，并且甚至最初如此要求保护，但是来自要求保护的组合的一个或多个特征在一些情况下可以从组合中删除，并且要求保护的组合可以涉及子组合或子组合的变形。
类似地，虽然在附图中以特定顺序描述了操作，但是这不应理解为要求这些操作以所示的特定顺序或按照顺序依次执行，或者要求执行所有所示的操作，以实现期望的结果。而且，在本专利文件中描述的实施例中的各种单独的系统部件不应理解为在所有实施例中需要这种分离。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的范围。

Claims (28)

  1. 一种芯片封装结构，其特征在于，包括基板、连接器、影像传感模块和辅助模块，所述影像传感模块和所述辅助模块利用所述基板进行一体式封装；
    所述影像传感模块包括影像传感芯片，所述影像传感芯片封装在所述基板的第一表面；
    所述辅助模块包括至少一个光学辅助芯片，所述至少一个光学辅助芯片封装在所述基板的第二表面，并通过所述基板与所述影像传感芯片进行电性连接；
    所述连接器连接在所述基板上，用于供所述芯片封装结构与外界单元进行电性连接。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述连接器连接在所述基板的第一表面或者第二表面。
  3. 根据权利要求2所述的芯片封装结构，其特征在于，所述影像传感芯片和所述至少一个光学辅助芯片分别设置在所述基板的第一表面和第二表面的主体部，且所述连接器连接在所述基板的第一表面或者第二表面的边缘部。
  4. 根据权利要求1所述的芯片封装结构，其特征在于，所述基板还包括多个侧面，所述连接器设置在所述基板的其中一个侧面。
  5. 根据权利要求1所述的芯片封装结构，其特征在于，所述第一表面为所述基板的主表面，所述第二表面为所述基板与所述主表面相背离的背面。
  6. 根据权利要求1所述的芯片封装结构，其特征在于，所述影像传感模块还包括镜头模块，所述镜头模块设置在所述影像传感芯片的上方，用于将目标光信号会聚或者导引到所述影像传感芯片。
  7. 根据权利要求6所述的芯片封装结构，其特征在于，所述镜头模块包括镜筒和收容在所述镜筒的光学镜头，所述影像传感芯片包括光学感应阵列，所述光学镜头与所述光学感应阵列进行光路对准设置。
  8. 根据权利要求7所述的芯片封装结构，其特征在于，所述镜头模块还包括滤光片，所述滤光片收容在所述镜筒，并位于所述光学镜头和所 述影像传感芯片之间，所述滤光片用于隔离外部干扰光以阻止其进入所述光学感应阵列。
  9. 根据权利要求7述的芯片封装结构，其特征在于，所述影像传感模块为光学指纹检测模块，所述目标光信号为从手指表面反射的指纹检测光，其中所述指纹检测光通过所述光学镜头会聚或者导引到所述影像传感芯片，所述影像传感芯片用于检测所述指纹检测光以进行光学指纹成像。
  10. 根据权利要求1所述的芯片封装结构，其特征在于，所述影像传感芯片通过第一粘合剂贴合到所述基板的第一表面，且其表面的焊盘通过第一金属线连接到所述基板的第一表面的电连接点。
  11. 根据权利要求10所述的芯片封装结构，其特征在于，所述光学辅助芯片通过第二粘合剂贴合到所述基板的第二表面，且其表面的焊盘通过第二金属线连接到所述基板的第二表面的电连接点，并且所述光学辅助芯片通过所述基板的连接线路与所述影像传感芯片进行电性连接。
  12. 根据权利要求1所述的芯片封装结构，其特征在于，所述基板为具有硅通孔的硅基板，所述影像传感芯片通过其底面的焊盘连接到所述硅基板的第一表面，且所述影像传感芯片的至少部分焊盘与所述硅基板的硅通孔进行电性连接。
  13. 根据权利要求12所述的芯片封装结构，其特征在于，所述光学辅助芯片通过其底面的焊盘以倒装焊接方式连接到所述硅基板的第二表面，且所述光学辅助芯片的至少部分焊盘通过所述硅通孔与所述影像传感芯片进行电性连接。
  14. 根据权利要求1至13中任一项所述的芯片封装结构，其特征在于，所述辅助模块还包括至少一个电容，所述至少一个电容通过焊锡连接到所述基板的第二表面的边缘区域。
  15. 根据权利要求14所述的芯片封装结构，其特征在于，所述辅助模块还包括塑封料，所述塑封料将所述光学辅助芯片和所述至少一个电容密封在所述基板的第二表面，并使得所述芯片封装结构的表面平整。
  16. 一种芯片封装方法，其特征在于，包括：
    提供用于芯片封装的基板，所述基板包括第一表面和第二表面；
    将影像传感芯片封装在所述基板的第一表面；
    将至少一个光学辅助芯片封装在所述基板的第二表面，其中，所述至少一个光学辅助芯片通过所述基板与所述影像传感芯片进行电性连接；
    将连接器连接到所述基板，以供所述芯片封装结构与外界单元进行电性连接。
  17. 根据权利要求16所述的芯片封装方法，其特征在于，所述连接器连接在所述基板的第一表面或者第二表面。
  18. 根据权利要求17所述的芯片封装方法，其特征在于，所述影像传感芯片和所述至少一个光学辅助芯片分别设置在所述基板的第一表面和第二表面的主体部，且所述连接器连接在所述基板的第一表面或者第二表面的边缘部。
  19. 根据权利要求16所述的芯片封装方法，其特征在于，所述基板还包括多个侧面，所述连接器设置在所述基板的其中一个侧面。
  20. 根据权利要求16所述的芯片封装方法，其特征在于，所述基板为具有硅通孔的硅基板，所述连接器和所述影像传感芯片通过同一次表面贴装工艺连接到所述基板的第一表面；或者，所述连接器和所述至少一个光学辅助芯片通过同一次表面贴装工艺连接到所述基板的第二表面。
  21. 根据权利要求16所述的芯片封装方法，其特征在于，还包括：将镜头模块贴合到所述影像传感芯片的上方，其中，所述镜头模块包括镜筒和收容在所述镜筒的光学镜头和滤光片，且所述镜头模块贴合之后所述光学镜头与所述影像传感芯片的光学感应阵列之间光路对准。
  22. 根据权利要求16所述的芯片封装方法，其特征在于，所述将影像传感芯片封装在所述基板的第一表面的步骤包括：
    利用第一粘合剂将所述影像传感芯片贴合到所述基板的第一表面；
    采用打线工艺并通过第一金属线将所述影像传感芯片表面的焊盘与所述基板的第一表面的电连接点进行电性连接。
  23. 根据权利要求22所述的芯片封装方法，其特征在于，所述将至少一个光学辅助芯片封装所述基板的第二表面的步骤包括：
    利用第二粘合剂将所述至少一个光学辅助芯片贴合到所述基板的第二表面；
    采用打线工艺并通过第二金属线将所述至少一个光学辅助芯片表面 的焊盘与所述基板的第二表面的电连接点进行电性连接。
  24. 根据权利要求16所述的芯片封装方法，其特征在于，所述基板为具有硅通孔的硅基板，且所述将影像传感芯片封装在所述基板的第一表面的步骤包括：
    通过所述影像传感芯片底面的焊盘将所述影像传感芯片连接到所述硅基板的第一表面，其中所述影像传感芯片的至少部分焊盘与所述硅基板的硅通孔进行电性连接。
  25. 根据权利要求24所述的芯片封装方法，其特征在于，所述将至少一个光学辅助芯片封装所述基板的第二表面的步骤包括：
    通过所述至少一个光学辅助芯片底面的焊盘以倒装焊接方式将所述至少一个光学辅助芯片连接到所述硅基板的第二表面，其中所述至少一个光学辅助芯片的至少部分焊盘通过所述硅通孔与所述影像传感芯片进行电性连接。
  26. 根据权利要求16至25中任一项所述的芯片封装方法，其特征在于，还包括：
    将至少一个电容连接到所述基板的第二表面的边缘区域；
    利用塑封料将所述至少一个光学辅助芯片和所述至少一个电容密封在所述基板的第二表面，并使得所述芯片封装结构的表面平整。
  27. 根据权利要求26所述的芯片封装方法，其特征在于，所述至少一个电容和所述至少一个光学辅助芯片通过同一次表面贴装工艺连接到所述基板的第二表面。
  28. 一种电子设备，其特征在于，包括显示屏和位于所述显示屏下方的光学指纹检测装置，所述光学指纹检测装置包括如权利要求1至15中任一项所述的芯片封装结构。
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