CN107133556B - 制造半导体装置的方法和半导体装置 - Google Patents

制造半导体装置的方法和半导体装置 Download PDF

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CN107133556B
CN107133556B CN201710096151.5A CN201710096151A CN107133556B CN 107133556 B CN107133556 B CN 107133556B CN 201710096151 A CN201710096151 A CN 201710096151A CN 107133556 B CN107133556 B CN 107133556B
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substrate
sensor
high voltage
layer
chip
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CN107133556A (zh
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余振华
陈玉芬
陈志华
蔡豪益
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露提供一种制造半导体装置的方法和半导体装置。半导体装置包括:传感器芯片;贯穿通路,电连接传感器芯片的第一侧与位在传感器芯片的第二侧上的导电元件,第二侧与第一侧相对;高电压芯片,与贯穿通路电连接;以及衬底,与贯穿通路电连接,其中高电压芯片位于衬底的开口内。

Description

制造半导体装置的方法和半导体装置
技术领域
本揭示涉及一种制造半导体装置的方法和半导体装置,具体涉及一种指纹传感器装置及其制造方法。
背景技术
由于用户装置变得更小且更便于携带,让有不轨企图的人变得更容易窃取用户装置。当这些装置携带用户的敏感数据,除非已将阻障放置到用户装置中,否则窃贼可能能够存取这些数据。一旦此种阻障是指纹传感器,其可用以读取试图存取装置者的指纹,如果所述指纹与用户的指纹不相同,存取可能被拒绝。
然而,由于用户装置例如手机变得更小,对于在用户装置内的个别组件的各者上也同时看到大小减小有压力。因此,对于减少含有指纹传感器的指纹封装件的大小但没有看到性能减少来说有压力。因此,需要改善以看到想要的大小减少。
发明内容
根据一实施例,提供一种制造半导体装置的方法,其包括:附接传感器表面材料在传感器芯片上方,其中传感器芯片包括:半导体衬底;以及电极阵列,其在半导体衬底与传感器表面材料之间;附接高电压芯片与传感器芯片电连接,其中高电压芯片位于与传感器表面材料相比的传感器芯片的相对侧上;以及附接传感器芯片到衬底,其中在附接传感器芯片到衬底之后,高电压芯片位于衬底的开口内。
根据另一实施例,提供一种制造半导体装置的方法,其包括:形成贯穿通路贯穿传感器衬底;形成电极阵列在传感器衬底上方,其中电极阵列与在传感器衬底的第一侧上的有源装置电连接;附接传感器外盖在传感器衬底的第一侧上方;附接高电压芯片与有源装置电连接,其中高电压芯片位于与电极阵列相比的传感器衬底的相对侧上;以及放置高电压芯片到位于第二衬底内的开口中。
根据又一实施例,提供一种半导体装置,其包括:传感器芯片;贯穿通路,电连接传感器芯片的第一侧与位在传感器芯片的第二侧上的导电元件,第二侧与第一侧相对;高电压芯片,与贯穿通路电连接;以及衬底,与贯穿通路电连接,其中高电压芯片位于衬底的开口内。
附图说明
本揭示的方面将在与随附图式一同阅读下列详细说明下被最好地理解。请注意,根据业界标准作法,各种特征未依比例绘制。事实上,为了使讨论内容清楚,各种特征的尺寸可刻意放大或缩小。
图1A至1F根据一些实施例说明指纹传感器封装件,其使用从传感器侧向移除的通孔。
图2A至2B根据一些实施例说明使用延伸通过指纹传感器与重布线层连接的通孔的实施例。
图3A至3B根据一些实施例说明在没有重布线层下使用延伸通过指纹传感器的通孔的实施例。
图4根据一些实施例说明将指纹传感器封装件并入到半导体装置中。
图5根据一些实施例说明将指纹传感器封装件并入到半导体装置中。
具体实施方式
下列揭示提供许多用于实施本揭示的不同特征的不同实施例、或实例。为了简化本揭示,在下文描述组件及配置的具体实例。当然这些仅为实例而非意图为限制性。例如,在下面说明中,形成第一特征在第二特征上方或上可包含其中第一及第二特征是形成为直接接触的实施例,以及也可包含其中额外特征可形成在第一与第二特征之间而使得第一及第二特征不可直接接触的实施例。此外,本揭示在各种实例中可重复参考编号及/或字母于。此重复是出于简单与清楚的目的且其本身并不决定所讨论的各种实施例及/或构形之间的关系。
再者,空间相关词汇,例如“在...之下”、“下面”、“下”、“上面”、“上”和类似词汇,可为了使说明书便于描述如图式说明的一个元件或特征与另一个(或多个)元件或特征的相对关系而使用于本文中。除了图式中所画的方位外,这些空间相对词汇也意图用来涵盖装置在使用中或操作时的不同方位。所述设备可以其它方式定向(旋转90度或于其它方位),据此在本文中所使用的这些空间相关说明符可以类似方式加以解释。
实施例现将关于在系统级封装件(system in package,SiP)解决方案中,不然在集成扇出结构(integrated fan out,InFO)中的指纹传感器描述。然而,实施例可使用于任何合适的封装件中。
现请参照图1A,说明有利用载体衬底101、粘着层103、聚合物层105、第一重布线层107、第一衬底通孔(through substrate via,TSV)109、及指纹传感器104的实施例。在一实施例中,载体衬底101包括,例如硅系材料,例如玻璃或氧化硅;或其它材料,例如氧化铝;这些材料的任一者的组合;或类似物。为了容置装置例如指纹传感器104的附接,载体衬底101为平坦的。
为了协助附接上覆结构到载体衬底101,粘着层103可放置在载体衬底101上方。在一实施例中,粘着层103为管芯裸片附接膜(die attached film,DAF),例如环氧树脂、酚树脂、丙烯酸系橡胶、二氧化硅填料、或其组合,且使用层压技术施加。然而,可利用任何其它合适的形成材料及方法。
聚合物层105初始形成在粘着层103上方。在一实施例中,聚合物层105可由一或多个合适的介电材料制成,例如氧化硅、氮化硅、低k介电质例如碳掺杂氧化物、极低k介电质例如多孔碳掺杂二氧化硅、这些的组合、或类似物。聚合物层105可透过工艺(例如,化学气相沉积(chemical vapor deposition,CVD))形成,虽然可利用任何合适的工艺,且可具有在约0.5μm与约5μm之间的厚度,例如约
Figure BDA0001230284950000031
一旦聚合物层105已形成,凸块下金属化层137及第一重布线层107可形成于聚合物层105上方。在一实施例中,凸块下金属化层137可包括三层导电材料,例如一层钛、一层铜、及一层镍。然而,所属领域的一般技术人员将认识到,有许多合适的材料及层的配置,例如适合凸块下金属化层137形成的铬/铬-铜合金/铜/金配置、钛/钛钨/铜配置、或铜/镍/金配置。可用于凸块下金属化层137的任何合适的材料或材料层意图完全包含在实施例的范围内。
在一实施例中,凸块下金属化层137通过是通过在聚合物层105上方形成各层而产生。各层的形成可使用镀敷工艺实施,例如电化学电镀,虽然取决于想要的材料可替代地使用其它形成工艺,例如溅镀、蒸发、或等离子增强化学气相沉积(plasma-enhanced CVD,PECVD)工艺。凸块下金属化层137可经形成以具有在约0.7μm与约10μm之间(例如约5μm)的厚度。
在一实施例中,第一重布线层107包括埋置在一系列介电层135(例如三个介电层)内的一系列导电层133(例如两个导电层)。在一实施例中,一系列介电层135的第一者形成在聚合物层105上方,且一系列介电层135的第一者可以是例如聚苯并恶唑(polybenzoxazole,PBO)的材料,虽然可利用任何合适的材料,例如聚酰亚胺或聚酰亚胺衍生物。一系列介电层135的第一者可使用如旋转涂布工艺放置,虽然可使用任何合适的方法。
在一系列介电层135的第一者已形成之后,可通过移除一系列介电层135的第一者的部分制作开口通过一系列介电层135的第一者。开口可使用合适的光刻掩模及蚀刻工艺形成,虽然任何合适的一或多个工艺可用以图案化一系列介电层135的第一者。
一旦一系列介电层135的第一者已形成且图案化之后,一系列导电层133的第一者形成在一系列介电层135的第一者上方且通过形成在一系列介电层135的第一者内的开口。在一实施例中,一系列导电层133的第一者可通过下列形成,透过合适的形成工艺(例如CVD或溅镀)初始形成钛铜合金的晶种层(未显示)。接着可形成光致抗蚀剂(也未显示),以覆盖晶种层,且接着可图案化光致抗蚀剂以暴露位于一系列导电层133的第一者想要坐落处的晶种层的那些部分。
一旦光致抗蚀剂已形成且图案化,导电材料例如铜可透过沉积工艺(例如,镀敷)形成在晶种层上。导电材料可被形成以具有在约1μm与约10μm之间的厚度,例如约5μm。然而,在所讨论材料及方法适于形成导电材料之际,这些材料仅为示范性的。任何其它合适的材料例如AlCu或Au,及任何其它合适的形成工艺(例如,CVD或物理气相沉积(physicalvapor deposition,PVD))可用以形成一系列导电层133的第一者。一旦导电材料已形成,光致抗蚀剂可透过合适的移除工艺(例如,灰化)移除。另外,在光致抗蚀剂的移除之后,被光致抗蚀剂覆盖的晶种层的那些部分可透过例如,使用导电材料作为遮罩的合适的蚀刻工艺移除。
一旦一系列导电层133的第一者已形成,一系列介电层135的第二者及一系列导电层133的第二者可通过重复与一系列介电层135的第一者及一系列导电层133的第一者相似的步骤形成。为了将一系列导电层133的各者电连接到一系列导电层133的下方者,这些步骤可依想要者重复,且可依想要者经常重复直到一系列导电层133的最上者及一系列介电层135的最上者已形成。在一实施例中,可持续一系列导电层133及一系列介电层135的沉积及图案化直到第一重布线层107具有想要数目的层,例如两个层,虽然可利用任何合适数目的个别层。
一旦第一重布线层107已形成在载体衬底101上方,即形成第一TSV 109与第一重布线层107电连接。在一实施例中,第一TSV 109可通过下列形成,起始形成晶种层(未分开说明在图1A中)。在一实施例中,晶种层是薄层导电材料,其有助于后续加工步骤期间较厚层的形成。晶种层可包括约
Figure BDA0001230284950000041
厚的一层钛接着约
Figure BDA0001230284950000042
厚的一层铜。取决于想要的材料,晶种层可使用工艺例如溅镀、蒸发、或PECVD工艺的工艺产生。晶种层可经形成以具有在约0.3μm与约1μm之间(例如约0.5μm)的厚度。
一旦晶种层已形成,光致抗蚀剂(也未说明在图1A中)放置在晶种层上方。在一实施例中,光致抗蚀剂可使用如旋转涂布技术放置在晶种层上,到高度在约50μm与约250μm之间,例如约120μm。一旦就位,光致抗蚀剂接着可通过使光致抗蚀剂暴露于经图案化能量源(如,经图案化光源)以便引起化学反应,进而在曝光于经图案化光源的光致抗蚀剂的那些部分中引起物理变化而图案化。接着将显影剂施加于曝光的光致抗蚀剂以利用物理变化并取决于想要的图案选择性移除光致抗蚀剂的曝光部分或光致抗蚀剂的未曝光部分。在一实施例中,形成于光致抗蚀剂中的图案是用于第一TSV 109的图案。第一TSV 109以这样的布局形成而位于后续附接装置例如指纹传感器104的不同侧。然而,可利用任何合适的用于第一TSV 109的图案的配置。
在一实施例中,第一TSV 109由一或多个导电材料形成于光致抗蚀剂内,例如铜、钨、其它导电金属、或类似物,且可通过例如电镀、无电式电镀、或类似物形成。例如,使用电镀工艺,其中晶种层及光致抗蚀剂浸入或浸没在电镀溶液中。晶种层表面电连接到外部直流电(direct current,DC)电源的负极侧而使得晶种层在电镀工艺中作为阴极。固体导电阳极,例如铜阳极也浸没在溶液中且附接到电源的正极侧。来自阳极的原子溶解于溶液中,阴极如晶种层从所述溶液中获取溶解的原子,进而镀敷在光致抗蚀剂的开口内的晶种层的暴露的导电区。
一旦第一TSV 109已使用光致抗蚀剂及晶种层形成,光致抗蚀剂可使用合适的移除工艺来移除。在一实施例中,等离子灰化工艺可用以移除光致抗蚀剂,借此光致抗蚀剂的温度可增加直到光致抗蚀剂经验热分解且可被移除。然而,可利用任何其它合适的工艺,例如湿剥除。光致抗蚀剂的移除可暴露晶种层的下方部分。
一旦暴露,可实施晶种层的暴露的部分的移除。在一实施例中,晶种层的暴露的部分(如,未被第一TSV 109覆盖的那些部分)可通过,例如湿式或干式蚀刻工艺移除。例如,在干式蚀刻工艺中,可使用第一TSV 109作为掩模将反应物导向晶种层。在另一实施例中,为了移除晶种层的暴露的部分,蚀刻剂可被喷洒或以其它方式使之接触晶种层。在晶种层的暴露的部分已蚀刻掉之后,第一重布线层107的一部分暴露在第一TSV 109之间。
一旦第一TSV 109已形成,指纹传感器104可放置在第一重布线层107上。在一实施例中,指纹传感器104包括具有前侧113及背侧115的半导体衬底111,及位于相邻于前侧113的电极阵列120。在一实施例中,半导体衬底111可包括经掺杂或未经掺杂的主体硅、或绝缘体上硅(silicon-on-insulator,SOI)衬底的有源层。一般来说,SOI衬底包括层半导体材料,例如硅、锗、硅锗、SOI、绝缘体上硅锗(silicon germanium on insulator,SGOI)、或其组合。可使用的其它衬底包含多层衬底、梯度衬底、或杂合方位向衬底。
另外,在未分开说明在图1A中之际,为了控制及接收来自电极阵列120的信号输入不然为了以其它方式控制指纹传感器104的功能性及最终输出,指纹传感器104也可包括有源装置及金属化层。在一实施例中,指纹传感器104的有源装置包括广泛种类的有源装置及无源装置例如电容器、电阻器、电感及类似物,其可用以产生用于指纹传感器104设计的想要的结构及功能要求。有源装置可使用任何合适的方法形成在半导体衬底111内不然在半导体衬底111上。
金属化层形成在半导体衬底111及指纹传感器104的有源装置上方且经设计用以连接各种有源装置以形成功能电路。在一实施例中,金属化层由介电及导电材料的交替层形成且可透过任何合适的工艺(例如沉积、镶嵌、双镶嵌、等)形成。在一实施例中,可能有四个金属化层,其与第二半导体衬底被至少一个层间介电层(interlayer dielectriclayer,ILD)分开,但金属化层的精确数目取决于指纹传感器104的设计。
为了测量指纹,电极阵列120电连接到指纹传感器104的金属化层且用以测量在上覆手指的不同区之间的差异。在一实施例中,电极阵列120包括导电材料例如铝或铜,且使用如沉积及图案化工艺形成,借此导电材料的整片层使用工艺例如CVD、PVD、原子层沉积(atomic layer deposition,ALD)、或类似物沉积,且导电材料的整片层接着使用光刻掩模及蚀刻工艺图案化。然而,可利用任何合适的制造的材料或方法以形成电极阵列120。
另外,在已通过使用整片沉积接着后续图案化及保护描述电极阵列120的形成之际,此工艺仅意图为例示而不是意图为限制性。相反地,也可使用任何合适的制造电极阵列120的工艺,例如使用镶嵌或双镶嵌工艺。所有这些工艺意图完全包含在实施例的范围内。
接触垫119经形成以将电连接提供给后续形成的第二重布线层121(未说明在图1A中但在下面关于图1B说明并描述)。在一实施例中,接触垫119由导电材料例如铝形成,虽然可利用其它合适的材料,例如铜、钨、或类似物。接触垫119可使用例如CVD或PVD的工艺形成,虽然可利用其它合适的材料及方法。一旦用于接触垫119的材料已沉积,可使用如光刻掩模及蚀刻工艺将材料塑形成接触垫119。
一旦接触垫119已形成,可放置及图案化第一保护层122。在一实施例中,第一保护层122可以是保护材料,例如聚苯并恶唑(PBO)、或聚酰亚胺(polyimide,PI)、氧化硅、氮化硅、氧氮化硅、苯并环丁烷(benzocyclobutene,BCB)、或任何其它合适的保护材料。第一保护层122可基于所选材料使用方法,例如旋涂工艺、沉积工艺(如,化学气相沉积)、或其它合适的工艺形成,且可被形成以具有在约1μm与约100μm之间(例如约20μm)的厚度。
一旦形成,第一保护层122经图案化以形成开口并暴露接触垫119。在一实施例中,第一保护层122可使用如光刻掩模及蚀刻工艺图案化。在这些工艺中,将光致抗蚀剂(未个别说明在图1B中)施加于第一保护层122且接着曝光于经图案化光源。光源将撞击在光致抗蚀剂上并引起光致抗蚀剂极性的改变,所述改变接着被利用以选择性地移除曝光部分或未曝光部分并暴露第一保护层122。接着利用光致抗蚀剂作为在如蚀刻工艺期间的掩模,所述蚀刻工艺移除第一保护层122的部分以暴露接触垫119。一旦第一保护层122已图案化,光致抗蚀剂可使用如灰化工艺移除。
在另一实施例中,为了暴露接触垫119,可薄化第一保护层122。在此实施例中,可利用平坦化工艺例如化学机械抛光工艺,借此将化学品及研磨剂施加于第一保护层122而抛光垫研磨掉材料,以移除来自在接触垫119上方的第一保护层122的材料,进而暴露接触垫119而也与接触垫119一起平坦化第一保护层122。可使用任何合适的形成接触垫119及第一保护层122的方法。
使用如第二粘着层112将指纹传感器104放置在第一重布线层107上且在第一TSV109之间。在一实施例中,第二粘着层112可以是与粘着层103相似的材料并以相似的方式施加,虽然可使用任何合适的材料。将指纹传感器104面朝上放置而使得前侧113背对载体衬底101。另外,将接触垫119连接到电极阵列120及在指纹传感器104的前侧113上的指纹传感器104的金属化层。
图1B说明以封装剂125将指纹传感器104及第一TSV 109封装。在一实施例中,封装剂125可以是模塑料且可使用成型装置(未说明在图1B中)放置。例如,指纹传感器104可放置在成型装置的空腔内且空腔可以是气密密封。封装剂125可在空腔气密密封之前放置在空腔内不然可透过注入口注入到空腔中。在一实施例中,封装剂125可以是模塑料树脂,例如聚酰亚胺、聚苯硫醚(polyphenylene sulfide,PPS)、聚醚醚酮(polyether etherketone,PEEK)、聚醚砜(Polyethersulfone,PES)、抗热结晶树脂、这些的组合、或类似物。
一旦封装剂125已放置到空腔中而使得封装剂125封装围绕指纹传感器104及第一TSV 109的区域,为了硬化封装剂125以供最优保护,封装剂125可被固化。在确切固化工艺是至少部分取决于为封装剂125所选的具体材料之际,在其中将模塑料选作封装剂125的一实施例中,固化可透过例如将封装剂125加热到约100℃与约130℃之间(例如,约125℃)历时约60秒到约3000秒(例如,600秒)的工艺发生。另外,起始剂及/或催化剂可包含在封装剂125内以更优化固化工艺。
然而,所属领域的一般技术人员将认知到,上述固化工艺仅为示范性工艺且不意味限制当前实施例。可使用其它固化工艺,例如辐射或甚至允许封装剂125在环境温度硬化。可使用任何合适的固化工艺,且所有这些工艺意图完全包含在本文所讨论实施例的范围内。
图1B另外说明为了暴露指纹传感器104的接触垫119的封装剂125的薄化。在一实施例中,可实施薄化,如使用机械研磨或化学机械研磨(CMP)工艺,借此利用蚀刻剂及研磨剂来反应并研磨掉封装剂125。可薄化封装剂125直到接触垫119暴露。
然而,在上述CMP工艺是以一个说明性实施例呈现之际,其不意图限制实施例。可使用任何其它合适的移除工艺来封装指纹传感器104同时暴露接触垫119。例如,可利用化学蚀刻或一系列化学蚀刻,或可利用不会覆盖接触垫119的封装工艺。可利用这些工艺及任何其它合适的工艺来施加封装剂125,且所有这些工艺意图完全包含在本文所讨论实施例的范围内。
图1B也说明为了电互连第一TSV 109与指纹传感器104的接触垫119的第二重布线层121的形成。在一实施例中,第二重布线层121可以是与上面关于图1A描述的第一重布线层107相似。在一具体实施例中,可能有一系列导电层133的单一者被夹在一系列介电层135的两者之间。然而,可利用导电层与介电层的任何合适的组合以互连指纹传感器104的接触垫119与第一TSV 109。
一旦第二重布线层121已形成,传感器表面材料123可使用如界面层136,例如胶层或色膜层附接到第二重布线层121。在一实施例中,传感器表面材料123可通过下列附接:初始施加界面层136到第二重布线层121及接着施加传感器表面材料123到界面层136。界面层136可以是与上面关于图1A描述的粘着层103相似,虽然可使用任何合适的材料。
在一实施例中,传感器表面材料123是例如蓝宝石或玻璃的材料,其允许指纹传感器104与上覆手指之间的电容式改变的测量以判定手指上指纹的轮廓。在一实施例中,传感器表面材料123可使用物理放置工艺放置。另外,传感器表面材料123可具有在约50μm与约1000μm之间(例如约100μm)的第一厚度T1。然而,可利用任何合适的材料及厚度。
在其中界面层136是色膜层的另一实施例中,可省略传感器表面材料。例如,在一具体实施例中,界面层136可借其本身放置在第二重布线层121上方,而不需要接着将传感器表面材料放置到界面层136上。可利用任何合适的材料组合。
图1C说明为了暴露凸块下金属化层137的载体衬底101的去接合及聚合物层105的图案化。在一实施例中,载体衬底101可通过初始接合传感器表面材料123到如环结构152而去接合。环结构152可以是意图在去接合工艺期间及之后为结构提供支撑及安定性的金属环。在一实施例中,传感器表面材料123可使用如紫外光胶带154附接到环结构152,虽然可使用任何其它合适的粘着剂或附接。
一旦附接,载体衬底101可使用如热工艺以改变粘着层103的粘着剂性质而从结构去接合。在一具体实施例中,利用能量源(例如,紫外光(ultraviolet,UV)雷射;二氧化碳(CO2)雷射、或红外光(infrared,IR)雷射)来辐射并加热粘着层103直到粘着层103丧失至少一些它的粘着剂性质。一旦实施,载体衬底101及粘着层103可从包括指纹传感器104及传感器表面材料123的结构实体分开并移除。
一旦去接合,为了暴露下方凸块下金属化层137,图案化聚合物层105。在一实施例中,聚合物层105可使用如雷射钻孔方法图案化。在这一方法中,保护层(例如,光热转换(light-to-heat conversion,LTHC)层或水溶性保护膜(hogomax)层(未分开说明在图1C中))先沉积在聚合物层105上方。一旦被保护,为了暴露下方凸块下金属化层137,将雷射导向想要被移除的聚合物层105的那些部分。在雷射钻孔工艺期间,钻孔能量可以是在从0.1mJ到约30mJ的范围中,且钻孔与聚合物层105的法线夹角为约0度(垂直于聚合物层105)到约85度。在一实施例中,图案化可经形成以在凸块下金属化层137上方形成开口,以具有在约100μm与300μm约之间(例如200μm)的宽度。
在另一实施例中,聚合物层105可通过下列图案化:初始施加光致抗蚀剂(未个别说明在图1C中)到聚合物层105及接着使光致抗蚀剂暴露于经图案化能量源(如,经图案化光源)以便引起化学反应,进而在曝光于经图案化光源的光致抗蚀剂的那些部分中引起物理变化。接着将显影剂施加到曝光的光致抗蚀剂以利用物理变化并取决于想要的图案选择性移除光致抗蚀剂的曝光部分或光致抗蚀剂的未曝光部分,且下方聚合物层105的暴露的部分以如干式蚀刻工艺移除。然而,可利用任何其它合适的用于图案化聚合物层105的方法。
图1D说明,一旦聚合物层105已图案化而暴露凸块下金属化层137,高电压芯片141可透过聚合物层105接合到凸块下金属化层137透以形成第一传感器封装件149。在一实施例中,为了放大传感器的灵敏度,高电压芯片141经设计与连接以供给高电压(例如,在约5伏特(V)与约50V之间(例如约33V))给指纹传感器104。例如,通过将高电压芯片141与指纹传感器104集成而使得高电压可供给到指纹传感器104,指纹传感器104的灵敏度可通过将输入电压从如3.3V提高到33V增加十倍。
在一实施例中,高电压芯片141可包括第二半导体衬底(未分开说明)、有源装置(未分开说明)、用以互连高电压芯片141的有源装置的金属化层(未分开说明)、及为了互连高电压芯片141到指纹传感器104的第一外部连接143。第二半导体衬底可包括经掺杂或未经掺杂的主体硅、或绝缘体上硅(SOI)衬底的有源层。一般来说,SOI衬底包括层半导体材料,例如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)、或其组合。可使用的其它衬底包含多层衬底、梯度衬底、或杂合方位向衬底。
用于高电压芯片141的有源装置包括广泛种类的有源装置及无源装置例如电容器、电阻器、电感及类似物,其可用以产生用于高电压芯片141设计的想要的结构及功能要求。有源装置可使用任何合适的方法形成在第二半导体衬底内不然在第二半导体衬底上。
用于高电压芯片141的金属化层形成在第二半导体衬底及高电压芯片141的有源装置上方且经设计用以连接各种有源装置以形成功能电路。在一实施例中,金属化层由介电及导电材料的交替层形成且可透过任何合适的工艺(例如沉积、镶嵌、双镶嵌、等)形成。在一实施例中,可能有四个金属化层,其与第二半导体衬底被至少一个层间介电层(ILD)分开,但金属化层的精确数目取决于高电压芯片141的设计。
第一外部连接143可经形成以互连高电压芯片141到指纹传感器104且可以是(例如)接触凸块,虽然可利用任何合适的连接。在其中第一外部连接143是接触凸块的实施例中,第一外部连接143可包括例如锡的材料、或其它合适的材料(例如,银、无铅锡、或铜)。在其中第一外部连接143是锡焊料凸块的实施例中,第一外部连接143可通过下列形成,透过这些常用方法,例如蒸发、电镀、印刷、焊料转移、植球、等,初始形成厚度如在约30μm与约100μm之间的一层锡。一旦一层焊料已形成在结构上,可实施回焊以将材料塑形成想要的凸块形状。
高电压芯片141可经形成以具有在约1mm与约5mm之间(例如约1.5mm)的第一宽度W1,且也可经形成以具有在约70μm与约150μm之间(例如约100μm)的第二厚度T2。另外,在因为它可能延伸进入且超出图而未显示于图1D中之际,高电压芯片141也可经形成以具有在约1mm与约5mm之间(例如约2mm)的第一长度。然而,任何合适的尺寸可用于高电压芯片141。
高电压芯片141可连接到凸块下金属化层137,例如通过初始施加焊料糊到暴露的凸块下金属化层137且接着覆晶接合高电压芯片141到凸块下金属化层137。在一实施例中,高电压芯片141可通过依序浸渍高电压芯片141的第一外部连接143到助焊剂中,且接着为了将高电压芯片141的第一外部连接143与凸块下金属化层137的个别者实体对准使用拾取和放置工具而接合。在其中第一外部连接143是焊球的一实施例中,一旦高电压芯片141已放置,为了接合高电压芯片141与下方凸块下金属化层137,可实施回焊工艺且可不实施助焊剂清洁。然而,可利用任何其它合适的连接件或连接工艺,例如金属到金属接合或类似物。
一旦高电压芯片141已接合到凸块下金属化层137,为了帮助保护及隔离装置,底胶材料147可放置在高电压芯片141与指纹传感器104之间。在一实施例中,底胶材料147是保护材料,其用以缓冲及支撑高电压芯片141免于操作及环境劣化。例如操作期间热的产生所造成的应力。底胶材料147可包括,例如液体环氧化物或其它保护材料,且接着被固化到硬化,及可通过如注入分注。
另外,在第一聚合物层105已图案化之后,第二外部连接139可被利用以提供用于电连接到第一重布线层107的外部连接点且可以是,例如作为球栅阵列(ball grid array,BGA)的部分的接触凸块,虽然可利用任何合适的连接。在其中第二外部连接139是接触凸块的一实施例中,第二外部连接139可包括例如锡的材料或其它合适的材料(例如,银、无铅锡、或铜)。在其中第二外部连接139是锡焊料凸块的一实施例中,第二外部连接139可通过下列形成,透过这些常用方法,例如蒸发、电镀、印刷、焊料转移、植球、等,初始形成厚度如约250μm的一层锡。一旦一层焊料已形成在结构上,可实施回焊以将材料塑形成想要的凸块形状。
图1E说明结构接合到衬底150。在一实施例中,为了提供想要的功能性给用户,衬底150可以是,如印刷电路板,其工作以将各种电气组件彼此互连。替代地,衬底150可以是柔性衬底或包括可蚀刻成微量的各种宽度及长度且透过层间通路连接的多个导电层(未个别说明)。线及通路可一起形成电网络以从衬底150的一侧到另一侧路由DC功率、接地、及信号。所属领域的一般技术人员将认知到,衬底150可由有机(层压体)材料例如双马来酰亚胺三嗪(bismaleimide-triazine,BT)、聚合物由材料例如液晶聚合物(liquid-crystalpolymer,LCP)、陶瓷材料例如低温共烧制陶瓷(low-temperature co-fired ceramic,LTCC)、硅或玻璃插置件或类似物制造。所属领域的一般技术人员也将认识到,导电层及通路可由任何合适的导电材料形成,例如铜、铝、银、金、其它金属、合金、其组合、及/或类似物,且通过任何合适的技术形成,例如电化学电镀(electro-chemical plating,ECP)、无电式电镀、其它沉积方法例如溅镀、印刷、及化学气相沉积(CVD)方法、或类似物。衬底150可经形成或获取以具有在约100μm与约1000μm之间(例如约200μm)的第三厚度T3,虽然可利用任何合适的厚度。
在一些实施例中,衬底150也可包含电气元件,例如电阻器、电容器、信号分布电路、这些的组合、或类似物。这些电气元件可以是有源的、无源的、或其组合。在其它实施例中,衬底150不含有源及无源电气元件二者于其中。所有这些组合意图完全包含在实施例的范围内。
另外,为了容置高电压芯片141的存在,衬底150可经形成以具有或已于其中形成有第一开口151。在一实施例中,为了容置高电压芯片141,第一开口151被尺寸化,且因此第一开口151的尺寸至少取决于高电压芯片141的尺寸。然而,在其中高电压芯片141具有第一宽度W1、第一长度、及第二厚度T2的一实施例中,第一开口151可经形成以具有在约2mm与约6mm之间(例如约2.5mm)的第二宽度W2。另外,第一开口151可具有在约2mm与约6mm之间(例如约3.5mm)的第二长度(由于第二长度将延伸进入且超出图而未分开显示于图1E中)。然而,可利用容置高电压芯片141的任何合适的尺寸。
另外,在一些实施例中,且如图1E所说明,第一开口151将一路延伸通过衬底150。因此,第一开口151将具有衬底150的第三厚度T3,例如在约0.1mm与约1mm之间,例如约0.2mm。然而,可使用任何合适的尺寸。
在另一实施例中(通过虚线说明在图1E中),第一开口151可经形成以部分但不完全延伸通过衬底150。在此实施例中,第一开口151可经形成以延伸进入衬底150第一距离D1(在约50μm与约500μm之间,例如约100μm)。然而,可利用任何合适的深度以容置高电压芯片141。
衬底150可进一步包括允许与第二外部连接139电连接的第二接触垫153。在一实施例中,第二接触垫153可由与上面关于图1A描述的接触垫119相似的材料并使用相似的工艺形成。例如,第二接触垫153可以是使用例如CVD或PVD的工艺形成的铝接触垫。然而,可使用任何合适的制造第二接触垫153的材料或方法。
为了接合第二接触垫153与第二外部连接139,第二接触垫153与第二外部连接139先彼此对准。举例来说,在一实施例中,第二外部连接139可对准并放置成与第二接触垫153物理接触。一旦就位且对准,为了物理接合及电接合第二外部连接139到衬底150,可回焊第二外部连接139。
通过附接指纹传感器104到衬底150而使得高电压芯片141位于第一开口151内,结构的整体高度可减少。例如,在一实施例中,衬底150连同附接指纹传感器104的整体高度可以是在约0.4mm与约1.5mm之间(例如约0.5mm)的第一高度H1。然而,可利用任何高度。
图1F说明另一实施例,其中替代于在指纹传感器104下面置中,高电压芯片141可依想要者相对于指纹传感器104坐落。例如,在图1F所说明的实施例中,高电压芯片141可位于距指纹传感器104的第一侧(在此俯视图中)第二距离D2处,D2在约80μm与约4000μm之间,例如约1000μm,且也位于距指纹传感器104的第二侧第三距离D3处,D3在约80μm与约4000μm之间,例如约1500μm。然而,可利用任何合适的相对于指纹传感器104的高电压芯片141的布局。
通过如上所描述形成第一传感器封装件149,不仅指纹传感器104的灵敏度可通过最小化电极阵列120与手指之间的感测间隙而增进,也使用扇入及通孔来集成高电压芯片141并增加电荷(Q=CxV)。此增加允许传感器灵敏度的增加。
图2A说明另一实施例,其说明第二传感器封装件200,为了连接电极阵列120与第三重布线层203,第二传感器封装件200使用延伸通过半导体衬底111的衬底通孔201。然而,在此实施例中,衬底通孔201被利用以将电极阵列120与位于指纹传感器104的前侧113上的金属化层电连接到指纹传感器104的背侧115。衬底通孔201可通过下列形成,在金属化层的形成之前,初始施加合适的光致抗蚀剂到半导体衬底111及显影光致抗蚀剂且接着蚀刻半导体衬底111以产生TSV开口。在此阶段,用于衬底通孔201的开口可经形成以便延伸进入半导体衬底111中到至少大于完成的半导体衬底111的最终想要的高度的深度。
一旦用于衬底通孔201的开口已形成,用于衬底通孔201的开口可填充有如,阻障层及导电材料。阻障层可包括导电材料例如氮化钛,虽然可利用其它材料,例如氮化钽、钛、介电质、或类似物。可使用CVD工艺例如PECVD形成阻障层。然而,可使用其它工艺,例如溅镀或金属有机化学气相沉积(metal organic chemical vapor deposition,MOCVD)。阻障层可经形成以便仿照下方用于衬底通孔201的开口形状的轮廓。
导电材料可包括铜,虽然可利用其它合适的材料,例如铝、合金、掺杂多晶硅、其组合、及类似物。导电材料可通过沉积晶种层且接着电镀铜到晶种层上、填充及上填用于衬底通孔201的开口而形成。一旦用于衬底通孔201的开口已填充,在用于衬底通孔201的开口外的过量阻障层及过量导电材料可透过研磨工艺例如化学机械研磨(CMP)移除,虽然可利用任何合适的移除工艺。
一旦导电材料在用于衬底通孔201的开口内,为了暴露用于衬底通孔201的开口及从延伸通过半导体衬底111的导电材料形成衬底通孔201,可实施半导体衬底111的薄化。在一实施例中,半导体衬底111的薄化可通过平坦化工艺例如CMP或蚀刻实施,使衬底通孔201与半导体衬底111共平面。
然而,所属领域的一般技术人员将认知到,上述用于形成衬底通孔201的工艺仅为形成衬底通孔201的一个方法,且其它方法也意图完全包含在实施例的范围内。例如,也使用形成用于衬底通孔201的开口、以介电材料填充用于衬底通孔201的开口、薄化半导体衬底111以暴露介电材料、移除介电材料、及以导体填充用于衬底通孔201的开口。此及所有其它合适的用于形成衬底通孔201到半导体衬底111中的方法意图完全包含在实施例的范围内。
一旦衬底通孔201已形成(且有源装置及金属化层也已如想要者完成),为了提供衬底通孔201与如高电压芯片141及第二外部连接139之间的互连性,可形成第三重布线层203与衬底通孔201电连接。在一实施例中,第三重布线层203可用与上面关于第一重布线层107描述相似的材料并使用相似的工艺形成。例如,第三重布线层203可由使用沉积及光刻掩模与蚀刻工艺形成的多层导电及介电材料形成。然而,可利用任何合适的形成材料或方法来形成第三重布线层203。
一旦第三重布线层203已形成,高电压芯片141可接合到第三重布线层203,且第二外部连接139可放置成与第三重布线层203电连接。在一实施例中,高电压芯片141及第二外部连接139可如上面关于图1D描述般形成或放置。例如,高电压芯片141可接合到第三重布线层203,且可放置并回焊第一外部连接143。
另外,在高电压芯片141与第一外部连接143已形成或放置之前或之后,传感器表面材料123可使用如界面层136附接到指纹传感器104。在一实施例中,传感器表面材料123可如上面关于图1B描述般以界面层136附接。例如,界面层136可物理接触传感器表面材料123与指纹传感器104二者。然而,可利用任何合适的附接传感器表面材料123的方法。
图2B说明衬底150到第二传感器封装件200的附接。在一实施例中,第二传感器封装件200如上面关于图1E描述般接合到衬底150。例如,第二外部连接139对准第二接触垫153,且实施回焊工艺以电接合及实体接合第二外部连接139到第二接触垫153。然而,可利用任何合适的接合第二传感器封装件200与衬底150的方法。
另外,在接合工艺期间,高电压芯片141对准并插入在位于衬底150内(或通过衬底150)的第一开口151中。在一实施例中,第一开口151被形成或坐落以便接受高电压芯片141并允许组合的衬底150与第二传感器封装件200的整体高度被减少。例如,在此实施例中,结构的整体高度可减少到第二高度H2,H2在约370μm与约1500μm之间,例如约400μm。然而,可利用任何合适的高度。
通过如所描述形成第三重布线层203连同衬底通孔201,衬底通孔201及第三重布线层203可用以将来自指纹传感器104的信号输出成重布信号。另外,具有衬底150及在衬底150内的第一开口151的纳入,可达成具有在第一开口151内部的高电压芯片141的弹性表面安装技术(surface mount technology,SMT)工艺。
图3A至3B说明另一实施例,其中在没有使用第三重布线层203下,形成衬底通孔201与第二外部连接139及高电压芯片141电连接以形成第三感应器封装件300。在此实施例中,替代于形成第三重布线层203在半导体衬底111的背侧115上,第三接触垫301直接形成在衬底通孔201上方且与衬底通孔201物理连接及/或电连接。在一实施例中,第三接触垫301可使用与上面关于接触垫119描述相似的材料及工艺形成。例如,第三接触垫301可使用沉积及图案化工艺由铝形成。然而,可利用任何合适的用于形成第三接触垫301的工艺。
一旦第三接触垫301已形成,第二保护层303可形成在第三接触垫301上方。在一实施例中,第二保护层303可以是保护材料,例如聚苯并恶唑(PBO)或聚酰亚胺(PI)、氧化硅、氮化硅、氧氮化硅、苯并环丁烷(BCB)、或任何其它合适的保护材料。第二保护层303可基于所选材料使用方法,例如旋涂工艺、沉积工艺(如,化学气相沉积)、或其它合适的工艺形成,且可经形成以具有在约1μm与约100μm之间(例如约20μm)的厚度。一旦就位,为了暴露第三接触垫301,可图案化第二保护层303。
一旦第三接触垫301已形成,传感器表面材料123可放置在指纹传感器104上方,高电压芯片141可接合到第三接触垫301,且第二外部连接139可放置成与第三接触垫301电连接。在一实施例中,传感器表面材料123、高电压芯片141及第二外部连接139可如上面关于图1B至1D描述般形成或放置。例如,传感器表面材料123可用第二胶层126粘附,高电压芯片141可接合置第三接触垫301,且可放置并回焊第二外部连接139。
图3B说明衬底150到第三传感器封装件300的附接。在一实施例中,第三传感器封装件300如上面关于图1E描述般接合到衬底150。例如,第二外部连接139对准第二接触垫153,且实施回焊工艺以电接合及物理接合第二外部连接139到第二接触垫153。然而,可利用任何合适的接合第三传感器封装件300与衬底150的方法。
另外,在接合工艺期间,高电压芯片141对准并插入在位于衬底150内(或通过衬底150)的第一开口151中。在一实施例中,第一开口151被形成或坐落以便接受高电压芯片141并允许组合的衬底150与第三传感器封装件300的整体高度减少。
通过直接接合高电压芯片141在衬底通孔201上方,可避免用于形成第三重布线层203的工艺步骤,允许更简单且较不复杂的制造工艺。另外,通过不制造第三重布线层203,没有第三重布线层203的结构的整体高度可减少。例如,在一实施例中,整体结构可具有第三高度H3,H3在约360μm与约1500μm之间,例如约390μm。然而,可利用任何合适的高度。
图4说明一实施例,其中衬底150及第一传感器封装件149并入到,如半导体装置结构400中,具有位于半导体装置结构400的第一侧的第一传感器封装件149及位于与第一侧相对的第二侧的显示器装置409。在一实施例中,半导体装置结构400包含多芯片封装件系统(multi-chip package system,MCPS)413,具有透过衬底150附接到MCPS413的指纹传感器104,具有衬底150透过如连接件417例如焊料凸块接合到MCPS 413,虽然可利用任何合适的连接件。
在一些实施例中,除了MCPS 413之外,其它电气组件415a及415b也通过连接件417附接到衬底150。电气组件415a及415b可彼此相似或不同。作为一实例,电气组件415a可以是半导体管芯或半导体封装件,及电气组件415b可以是离散电气组件,如无源或有源装置例如电容器、电感、电阻器、电晶体、二极体、或类似物。所属领域的一般技术人员将理解,图4仅为例示说明,因为不同数目的MCPS 413及电气组件415a/415b可搭配指纹传感器104使用而不会脱离如当前揭示的精神。
如图4中所说明,电池411通过电缆419电耦合到衬底150,具有MCPS 413设置在电池411与衬底150之间。在一些实施例中,电缆419柔性电缆,例如柔性印刷电路(flexibleprinted circuit,FPC)电缆。显示器装置409,例如液晶显示器(liquid crystal display,LCD)设置在电池411旁边,以电池411设置在MCPS 413与显示器装置409之间。在一些实施例中,显示器装置409通过电缆421例如FPC电缆电耦合到衬底150。
另外,根据一些实施例,半导体装置结构400具有壳401。在一些实施例中,半导体装置结构400包括可穿戴装置,例如智能手表、健身装置、或健康监测装置。
通过如所描述附接第一传感器封装件149到衬底150,及并入所述结构到半导体装置结构400中,可减少个别组件的厚度,允许使用更大大小的电池411。例如,在一实施例中,电池411的高度可增加以具有在约3mm与约7mm之间(例如约5mm)的第四高度H4。通过增加电池411的大小但不增加结构的大小,在充电之间,半导体装置可运行更长一段时间。
图5说明一替代实施例,其中大小所省下者可能不是用于并入较大电池,而是可能用于减少半导体装置结构400的整体大小。在此实施例中,半导体装置结构400可减少以具有在约8mm与约15mm之间(例如约10mm)的整体第五高度H5。然而,可利用合适的大小。通过减少大小,可达成更小的整体结构。
另外,在图4及5所描述实施例是关于上面关于图1A至1F描述的第一传感器封装件149描述之际,实施例不限于第一传感器封装件149。相反地,也可利用任何合适的传感器封装件,例如第二传感器封装件200或传感器封装件300。所有合适的组合意图完全包含在实施例的范围内。
根据一实施例,提供一种制造指纹扫描器的方法,包括附接指纹传感器表面材料在一指纹传感器上方。所述指纹传感器包括半导体衬底;及电极阵列,其在所述半导体衬底与所述指纹传感器表面材料之间。附接高电压芯片与所述指纹传感器电连接,其中所述高电压芯片位于与所述指纹传感器表面材料相比的所述指纹传感器的相对侧上。附接所述指纹传感器到衬底,其中在所述附接所述指纹传感器到所述衬底之后,所述高电压芯片位于所述衬底的开口内。
根据另一实施例,提供一种制造指纹扫描器的方法,所述方法包括形成通孔贯穿指纹传感器衬底。形成电极阵列在所述指纹传感器衬底上方,其中所述电极阵列与在所述指纹传感器衬底的第一侧上的有源装置电连接,以及附接指纹传感器外盖在所述指纹传感器衬底的所述第一侧上方。附接一高电压芯片与所述有源装置电连接,其中所述高电压芯片位于与所述电极阵列相比的所述指纹传感器衬底的相对侧上,及放置所述高电压芯片到位于第二衬底内的开口中。
根据又一实施例,提供一种半导体装置,包括指纹传感器。通孔,电连接所述指纹传感器的第一侧与位于所述指纹传感器的第二侧上的导电元件,所述第二侧与所述第一侧相对。高电压芯片,与所述通孔电连接;及衬底,与所述通孔电连接,其中所述高电压芯片位于所述衬底的开口内。
前面列述了数个实施例的特征以便所属领域的一般技术人员可更好地理解本揭示的方面。所属领域的一般技术人员应了解,其可轻易地使用本揭示作为用以设计或修改其它工艺及结构的基础以实现本文中所介绍实施例的相同目的及/或达成本文中所介绍实施例的相同优点。所属领域的一般技术人员也应认识到,这些均等构造不会脱离本揭示的精神及范围,以及它们可在不脱离本揭示的精神及范围下做出各种改变、取代、或替代。
元件符号
101 载体衬底
103 粘着层
104 指纹传感器
105 聚合物层
107 第一重布线层
109 第一衬底通孔
111 半导体衬底
112 第二粘着层
113 前侧
115 背侧
119 接触垫
120 电极阵列
121 第二重布线层
122 第一保护层
123 传感器表面材料
125 封装剂
126 第二胶层
133 一系列导电层
135 一系列介电层
136 界面层
137 凸块下金属化层
139 第二外部连接
141 高电压芯片
143 第一外部连接
147 底胶材料
149 第一传感器封装件
150 衬底
151 第一开口
152 环结构
153 第二接触垫
154 紫外光胶带
200 第二传感器封装件
201 衬底通孔
203 第三重布线层
300 第三感应器封装件
301 第三接触垫
303 第二保护层
400 半导体装置结构
401 壳
409 显示器装置
411 电池
413 多芯片封装件结构
415a 电气组件
415b 电气组件
417 连接件
419 电缆
421 电缆
W1 第一宽度
W2 第二宽度
T1 第一厚度
T2 第二厚度
T3 第三厚度
D1 第一距离
D2 第二距离
D3 第三距离
H1 第一高度
H2 第二高度
H3 第三高度
H4 第四高度
H5 整体第五高度

Claims (20)

1.一种制造半导体装置的方法,所述方法包括:
附接传感器表面材料在传感器芯片上方,其中所述传感器芯片包括:
半导体衬底;以及
电极阵列,其在所述半导体衬底与所述传感器表面材料之间;
附接高电压芯片与所述传感器芯片电连接,其中所述高电压芯片位于与所述传感器表面材料相比的所述传感器芯片的相对侧上;以及
附接所述传感器芯片到衬底,其中在所述附接所述传感器芯片到所述衬底之后,所述高电压芯片位于所述衬底的开口内。
2.根据权利要求1所述的方法,其中所述衬底的所述开口一路延伸通过所述衬底。
3.根据权利要求1所述的方法,其中所述衬底的所述开口仅部分延伸通过所述衬底。
4.根据权利要求1所述的方法,其中所述传感器芯片进一步包括重布线层,其位于所述传感器表面材料与所述半导体衬底之间。
5.根据权利要求4所述的方法,进一步包括:
在所述附接所述传感器表面材料之前,形成通路;
放置所述传感器芯片在所述通路内;以及
在所述放置所述传感器芯片之后,封装所述通路及所述传感器芯片。
6.根据权利要求1所述的方法,其进一步包括形成接触垫直接物理接触位于所述传感器芯片内的贯穿衬底通路。
7.一种制造半导体装置的方法,所述方法包括:
形成贯穿通路贯穿传感器衬底;
形成电极阵列在所述传感器衬底上方,其中所述电极阵列与在所述传感器衬底的第一侧上的有源装置电连接;
附接传感器外盖在所述传感器衬底的所述第一侧上方;
附接高电压芯片与所述有源装置电连接,其中所述高电压芯片位于与所述电极阵列相比的所述传感器衬底的相对侧上;以及
放置所述高电压芯片到位于第二衬底内的开口中。
8.根据权利要求7所述的方法,其进一步包括形成重布线层与所述贯穿通路电连接且在与所述有源装置相比的所述传感器衬底的相对侧上,其中所述附接所述高电压芯片附接所述高电压芯片到所述重布线层。
9.根据权利要求8所述的方法,其进一步包括附接第一外部连接到所述重布线层。
10.根据权利要求7所述的方法,其进一步包括形成接触垫与所述贯穿通路物理接触,其中所述附接所述高电压芯片附接所述高电压芯片到所述接触垫。
11.根据权利要求10所述的方法,进一步包括附接第一外部连接到所述接触垫。
12.根据权利要求7所述的方法,其中所述开口从所述第二衬底的一侧延伸到所述第二衬底的第二侧,所述第二侧与所述第一侧相对。
13.根据权利要求7所述的方法,其中所述开口延伸进入所述第二衬底在50μm与500μm之间的距离。
14.根据权利要求7所述的方法,其中所述第二衬底是印刷电路板。
15.一种半导体装置,其包括:
传感器芯片;
贯穿通路,电连接所述传感器芯片的第一侧与位在所述传感器芯片的第二侧上的导电元件,所述第二侧与所述第一侧相对;
高电压芯片,与所述贯穿通路电连接;以及
衬底,与所述贯穿通路电连接,其中所述高电压芯片位于所述衬底的开口内。
16.根据权利要求15所述的半导体装置,其中所述导电元件是重布线层。
17.根据权利要求15所述的半导体装置,其中所述导电元件是接触垫。
18.根据权利要求15所述的半导体装置,其中所述贯穿通路贯穿半导体衬底。
19.根据权利要求15所述的半导体装置,其中所述贯穿通路贯穿封装剂且与所述传感器芯片分开,所述封装剂物理接触所述贯穿通路。
20.根据权利要求15所述的半导体装置,其中所述衬底是印刷电路板。
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Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101419600B1 (ko) * 2012-11-20 2014-07-17 앰코 테크놀로지 코리아 주식회사 지문인식센서 패키지 및 그 제조 방법
US9875388B2 (en) 2016-02-26 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US11003884B2 (en) * 2016-06-16 2021-05-11 Qualcomm Incorporated Fingerprint sensor device and methods thereof
US10183858B2 (en) * 2016-11-29 2019-01-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TWI672779B (zh) * 2016-12-28 2019-09-21 曦威科技股份有限公司 指紋辨識裝置、使用其之行動裝置以及指紋辨識裝置的製造方法
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
CN109711229B (zh) * 2017-10-26 2021-12-21 中芯国际集成电路制造(上海)有限公司 一种指纹识别芯片及其制造方法和电子装置
CN109918966B (zh) * 2017-12-12 2021-02-05 中芯国际集成电路制造(北京)有限公司 指纹识别装置及其制造方法、移动终端及指纹锁
US20200051938A9 (en) * 2017-12-18 2020-02-13 China Wafer Level Csp Co., Ltd. Fingerprint chip packaging method and fingerprint chip package
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10832985B2 (en) * 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
CN109417081B (zh) * 2018-09-29 2021-01-22 深圳市汇顶科技股份有限公司 芯片封装结构、方法和电子设备
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
TWI768294B (zh) * 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
TWI739546B (zh) * 2020-02-20 2021-09-11 神盾股份有限公司 光感測元及使用其的光學生物特徵感測器
US11145580B1 (en) * 2020-03-25 2021-10-12 International Business Machines Corporation IoT and AI system package with solid-state battery enhanced performance
US11239150B2 (en) 2020-03-25 2022-02-01 International Business Machines Corporation Battery-free and substrate-free IoT and AI system package
TWI768552B (zh) * 2020-11-20 2022-06-21 力成科技股份有限公司 堆疊式半導體封裝結構及其製法
US11785707B2 (en) * 2021-01-21 2023-10-10 Unimicron Technology Corp. Circuit board and manufacturing method thereof and electronic device
TWM612841U (zh) * 2021-02-19 2021-06-01 安帝司股份有限公司 指紋辨識智慧卡
KR20230056474A (ko) * 2021-10-20 2023-04-27 삼성전자주식회사 지문 센서 패키지 및 센서 패키지
KR20240018865A (ko) 2022-08-03 2024-02-14 삼성전자주식회사 지문 센서 패키지 및 이를 포함하는 스마트 카드

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200705699A (en) * 2005-07-21 2007-02-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and fabrication method thereof
CN201477732U (zh) * 2009-09-08 2010-05-19 上海工程技术大学 一种指纹遥控装置
TW201126681A (en) * 2010-01-21 2011-08-01 Unimicron Technology Corp Package structure having embedded chip and method for making the same
US20130069188A1 (en) * 2011-09-16 2013-03-21 Omnivision Technologies, Inc. Dual-facing camera assembly
CN103456750A (zh) * 2012-06-01 2013-12-18 台湾积体电路制造股份有限公司 具有高占空因数的图像传感器
TW201421754A (zh) * 2012-11-30 2014-06-01 Ind Tech Res Inst 光電元件封裝體
CN104218034A (zh) * 2013-06-04 2014-12-17 三星电机株式会社 半导体封装
KR20150018358A (ko) * 2013-08-08 2015-02-23 삼성전자주식회사 지문인식장치와 그 제조방법 및 전자기기
CN104615979A (zh) * 2015-01-27 2015-05-13 华进半导体封装先导技术研发中心有限公司 指纹识别模块及封装方法、指纹识别模组及封装方法
TWI485821B (zh) * 2014-02-24 2015-05-21 Dynacard Co Ltd 指紋辨識晶片封裝模組及其製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NO315017B1 (no) * 2000-06-09 2003-06-23 Idex Asa Sensorbrikke, s¶rlig for måling av strukturer i en fingeroverflate
US6672174B2 (en) * 2001-07-23 2004-01-06 Fidelica Microsystems, Inc. Fingerprint image capture device with a passive sensor array
US9095072B2 (en) 2010-09-18 2015-07-28 Fairchild Semiconductor Corporation Multi-die MEMS package
US9898645B2 (en) * 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US9589941B1 (en) 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US9875388B2 (en) * 2016-02-26 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200705699A (en) * 2005-07-21 2007-02-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and fabrication method thereof
CN201477732U (zh) * 2009-09-08 2010-05-19 上海工程技术大学 一种指纹遥控装置
TW201126681A (en) * 2010-01-21 2011-08-01 Unimicron Technology Corp Package structure having embedded chip and method for making the same
US20130069188A1 (en) * 2011-09-16 2013-03-21 Omnivision Technologies, Inc. Dual-facing camera assembly
CN103456750A (zh) * 2012-06-01 2013-12-18 台湾积体电路制造股份有限公司 具有高占空因数的图像传感器
TW201421754A (zh) * 2012-11-30 2014-06-01 Ind Tech Res Inst 光電元件封裝體
CN104218034A (zh) * 2013-06-04 2014-12-17 三星电机株式会社 半导体封装
KR20150018358A (ko) * 2013-08-08 2015-02-23 삼성전자주식회사 지문인식장치와 그 제조방법 및 전자기기
TWI485821B (zh) * 2014-02-24 2015-05-21 Dynacard Co Ltd 指紋辨識晶片封裝模組及其製造方法
CN104615979A (zh) * 2015-01-27 2015-05-13 华进半导体封装先导技术研发中心有限公司 指纹识别模块及封装方法、指纹识别模组及封装方法

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