TWI528515B - 形成用於覆晶半導體晶粒的墊佈局的半導體裝置及方法 - Google Patents

形成用於覆晶半導體晶粒的墊佈局的半導體裝置及方法 Download PDF

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TWI528515B
TWI528515B TW100102446A TW100102446A TWI528515B TW I528515 B TWI528515 B TW I528515B TW 100102446 A TW100102446 A TW 100102446A TW 100102446 A TW100102446 A TW 100102446A TW I528515 B TWI528515 B TW I528515B
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pad
bump
substrate
die
semiconductor die
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TW100102446A
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TW201250958A (en
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拉簡德拉Ｄ 潘斯
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史達晶片有限公司
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Description

形成用於覆晶半導體晶粒的墊佈局的半導體裝置及方法 【優先權主張】
本申請案是2009年4月29日申請的美國申請案號12/432,137的一部分接續案，並且根據美國專利法第120條主張前述申請案的優先權。
本發明係有關於半導體裝置，並且更具體而言係有關於一種形成用於覆晶半導體晶粒的墊佈局的半導體裝置及方法。
半導體裝置常見於現代的電子產品中。半導體裝置在電性構件的數目及密度上有所不同。離散的半導體裝置一般包含一種類型的電性構件，例如，發光二極體(LED)、小信號的電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(MOSFET)。積體化半導體裝置通常包含數百個到數百萬個電性構件。積體化半導體裝置的例子包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池以及數位微鏡裝置(DMD)。
半導體裝置可執行廣大範圍的功能，例如：信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力以及產生用於電視顯示器之可見的投影。半導體裝置可見於娛樂、通訊、電力轉換、網路、電腦以及消費性產品的領域中。半導體裝置亦可見於軍事應用、航空、汽車、工業用控制器以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的原子結構係容許其導電度可藉由一電場或基極電流的施加或是透過摻雜的製程來操控。摻雜係將雜質引入半導體材料中以操控及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電氣結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流施加的位準，電晶體不是提升就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係產生執行各種電氣功能所必要的一種電壓及電流間之關係。被動及主動結構係電連接以形成電路，此係使得半導體裝置能夠執行高速的計算以及其它有用的功能。
半導體裝置一般是利用兩種複雜的製程，亦即，前端製造及後端製造來製成，每一種都牽涉到可能有數百道的步驟。前端製造係牽涉到在一半導體晶圓的表面上複數個晶粒的形成。每個晶粒通常是相同的並且包含由電連接主動及被動構件所形成的電路。後端製造係牽涉到從晶圓成品單切(singulating)個別的晶粒及封裝該晶粒以提供結構的支撐及環境的隔離。
半導體製造的一項目標是生產出更小的半導體裝置。越小的裝置通常消耗更低的電力，具有更高的效能，並且可更有效率地被生產出。此外，越小的半導體裝置具有更小的覆蓋區(footprint)，此係為更小的最終產品所期望的。更小的晶粒尺寸可藉由在前端製程中以更小及更高密度的主動及被動構件來產生晶粒的改良而達成。後端製程可藉由在電氣互連及封裝材料上的改良以產生更小的覆蓋區之半導體裝置封裝。
在一覆晶封裝中，一半導體晶粒通常是以該晶粒的主動側面對一封裝基板來安裝到該基板。半導體晶粒中的電路與基板中的電路之互連係藉由凸塊來完成，該些凸塊係附接到該晶粒上之一陣列的互連墊，並且連結到該基板上之一對應互補的陣列的互連墊。
半導體晶粒上用於信號、電源及接地功能的墊傳統上是分佈在該陣列的各處，並且基板上對應的墊係連接至適當的電路而到外部的第二層級的互連。該第二層級的互連具有比覆晶的互連大的間距，因此基板上的繞線傳統上是成扇形展開。在半導體晶粒上的墊以及封裝的外部接腳之間扇形展開的繞線係被形成在該封裝基板內的多個金屬層上。
多層的基板係昂貴的，並且在習知的覆晶建構中，光是基板通常就佔去超過一半的封裝成本。多層基板的高成本一直都是限制覆晶技術在主流產品中繁衍的一項因數。在習知的覆晶建構中，該逸散的(escape)繞線圖案通常會帶來額外的電性寄生現象，因為該繞線包含在信號傳送路徑中短的路線之無屏蔽的佈線以及佈線層間的貫孔(via)。電性寄生現象可能嚴重地限制封裝的效能。
在一習知的覆晶封裝中，半導體晶粒13上的輸入/輸出墊(統稱為信號墊)係被配置在一實質覆蓋該晶粒的主動表面12的區域陣列中，即如在大致於圖1中的10之平面圖中所示者。分別有關半導體晶粒13的信號、電源及接地功能的信號墊18及19、電源墊14以及接地墊16係分佈在該陣列內的多個列與行的各個地方。尤其，某些信號墊18係被配置在該陣列的周邊，而其它信號墊19則否。通常會做某種設計上的努力以配置該些墊，使得各種的信號墊係被電源墊及/或接地墊所圍繞、或至少是與電源墊及/或接地墊相鄰的。
許多習知的覆晶封裝是利用陶瓷基板做成的。陶瓷基板可以相對廉價地用大數量的層做成，並且盲貫孔可在陶瓷層中毫無困難地做成。在被做成配合習知的陶瓷基板來使用之習知的晶片中，墊的間距通常是在150微米(μm)至250μm的範圍中，並且許多晶片典型是225μm的格距。
基板中扇形展開的繞線(亦即，連接基板上對應的墊與封裝的外部端子之基板上的佈線)係以多個被圖案化以提供信號佈線以及電源及接地佈線的金屬層來加以實施。一對應於晶粒的墊佈局10之基板墊的配置係被展示在一大致於圖2中的20之平面圖中。信號墊28及29、電源墊24以及接地墊26係以一互補陣列配置在基板表面22上，因而它們可以分別接收及連結到附接至該晶粒上對應的墊之信號、電源以及接地凸塊。在習知的配置中，某些與信號繞線相關連的墊28係位在該陣列的周邊，而其它墊29則否。用於在該陣列的周邊的信號墊之逸散的繞線可能直接橫過在下方的晶粒邊緣23而為該基板的最上面的金屬層中之線路30。該基板上之不在該陣列的周邊的墊係藉由短的線路以及貫孔而連接到該基板中較深的金屬層。信號墊29係藉由短的線路(信號短線段(stub)或凸出(jog))32透過信號貫孔34連接至下方的數個金屬層之一金屬層中的信號線路。同樣地，電源墊24係藉由短的線路(電源短線段或凸出)36透過電源貫孔38連接至下方的一金屬層中的電源線路，並且接地墊26係藉由短的線路(接地短線段或凸出)40透過接地貫孔42連接至下方的一金屬層中的電源線路。
在一具有大約1000個外部端子的典型習知的封裝中，有至少2或3層的信號佈線以及至少4或5層的電源及接地佈線在基板中，此係導致有總數大約是6或8或是更多的層。一般而言，信號佈線層數目的增加需要電源及接地層之伴隨的增加，因為需要在封裝中維持一傳輸線的電氣環境，此進一步增加總層數。該對於額外層的需要亦產生較長的信號路徑以及許多層至層的貫孔，再加上不希望有的電性寄生現象及效能的劣化。
對於一種容納信號墊以及電源墊及接地墊的晶粒墊佈局存在著需求，其為覆晶半導體晶粒所需且增加繞線密度及最小化必要的互連層數目。於是，在一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下的步驟：提供一具有一晶粒墊佈局的半導體晶粒，其中信號墊主要位在該半導體晶粒的一周邊區域中，並且電源墊及接地墊主要位在該半導體晶粒的該些信號墊的一內側的區域中；在該些信號墊、電源墊以及接地墊之上形成複數個凸塊；提供一基板；以及在該基板之上形成複數個具有互連位置的導電線路。該些凸塊係比該些互連位置寬。該方法進一步包含以下步驟：將該些凸塊連結至該些互連位置使得該些凸塊覆蓋該些互連位置的一頂表面及多個側表面，以及在該半導體晶粒及基板之間的該些凸塊的周圍沉積一封裝材料。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一半導體晶粒；提供一基板；在該基板之上形成複數個具有互連位置的導電線路，其係以一其中信號位置係位在靠近該基板的一周邊並且電源位置及接地位置係位在該些信號位置的內側之佈局來配置；以及在該半導體晶粒及基板之間形成一互連結構使得該些互連結構覆蓋該些互連位置的一頂表面及多個側表面。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括以下步驟：提供一半導體晶粒；提供一基板；在該基板之上形成複數個具有互連位置的導電線路，其係以一其中信號位置主要位在該基板的一周邊區域中並且電源位置及接地位置主要位在該基板的該些信號墊之一內側的區域中之佈局來配置；將該半導體晶粒連結至該些互連位置；以及在該半導體晶粒及基板之間沉積一封裝材料。
在另一實施例中，本發明是一種半導體裝置，其係包括一具有一晶粒墊佈局的半導體晶粒，其中信號墊主要位在該半導體晶粒的一周邊區域中，並且電源墊及接地墊主要位在該半導體晶粒的該些信號墊的一內側的區域中。複數個具有互連位置的導電線路係被形成在一基板之上。該半導體晶粒係連結到該些互連位置。一封裝材料係沉積在該半導體晶粒及基板之間。
本發明在以下參考圖式的說明中係以一或多個實施例加以描述，其中相同元件符號代表相同或類似元件。儘管本發明是依據達成本發明目的之最佳模式描述，但熟習此項技術者將瞭解本發明欲涵蓋如隨附申請專利範圍所界定之可內含於本發明之精神及範疇內的替代物、修改及等效物以及如以下揭示內容及圖式所支持之其等效物。
半導體裝置一般是使用兩個複雜的製程來製造：前端製造與後端製造。前端製造係牽涉到在半導體晶圓表面上形成多個晶粒。該晶圓上之各晶粒含有主動及被動電性構件，其係電連接以形成功能電路。諸如電晶體及二極體之主動電性構件係具有控制電流流動之能力。諸如電容器、電感器、電阻器及變壓器之被動電性構件係產生執行電路功能所必要的一種電壓及電流間之關係。
被動及主動構件藉由一系列製程步驟形成於半導體晶圓表面上，包括摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由諸如離子植入或熱擴散之技術將雜質引入半導體材料中。摻雜製程改變主動裝置中半導體材料之導電度，從而將該半導體材料轉變成絕緣體、導體，或是響應於電場或基極電流而動態地改變該半導體材料之導電度。電晶體含有摻雜類型及程度不同之區域，其視需要來加以配置以使該電晶體能夠在施加電場或基極電流時促進或限制電流流動。
主動及被動構件係由具有不同電特性之材料層形成。該等層可藉由多種沉積技術形成，該些沉積技術部分是由所沉積之材料類型決定的。舉例而言，薄膜沉積可包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍及無電的電鍍製程。每個層一般是經圖案化以形成主動構件、被動構件或各構件間電連接的部分。
該些層可使用微影進行圖案化，其牽涉到使光敏材料(例如光阻)沉積於待圖案化的層之上。使用光以將圖案自光罩轉印於光阻上。使用一溶劑移除光阻圖案曝光之部分，露出待圖案化之下層部分。移除該光阻之其餘部分，留下一經圖案化的層。或者，某些類型的材料係使用諸如無電的電鍍及電解的電鍍之技術藉由使材料直接沉積於由先前沉積/蝕刻製程所形成的區域或空隙中而加以圖案化。
在現有圖案之上沉積一材料薄膜可能會放大下面的圖案且產生非均勻平坦的表面。生產較小且較密集封裝之主動及被動構件需要均勻平坦的表面。可使用平坦化以自晶圓表面移除材料且產生均勻平坦的表面。平坦化係牽涉到用拋光墊拋光晶圓的表面。在拋光期間將研磨材料及腐蝕性化學品添加至晶圓的表面。研磨劑的機械作用與化學品的腐蝕作用組合可移除任何不規則的表面構形，從而產生均勻平坦的表面。
後端製造係指將晶圓成品切割或單切成個別晶粒且接著封裝該晶粒以提供結構的支撐及環境的隔離。為了單切晶粒，沿著晶圓非功能區(稱為切割道或劃線)將晶圓劃痕並切斷。使用雷射切割工具或鋸條單切晶圓。在單切之後，將個別晶粒安裝於一封裝基板上，該封裝基板包括接腳或接觸墊以供與其他系統構件互連。接著使半導體晶粒上所形成之接觸墊連接至封裝內之接觸墊。該電連接可由焊料凸塊、柱形凸塊、導電膏或焊線(wirebond)形成。使一封裝材料或其它模製材料沉積於封裝之上以提供物理支撐及電隔離。接著將成品封裝插入一電系統中，且使半導體裝置之功能可供其他系統構件利用。
圖3係描繪具有多個安裝於其表面上之半導體封裝的晶片載體基板或印刷電路板(PCB)52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖3中。
電子裝置50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子裝置50可以是一較大系統之子構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊裝置的一部份。或者是，電子裝置50可以是一可插入電腦中之顯示卡、網路介面卡或其他信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其他半導體晶粒或電性構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體裝置間的距離必須縮短以達到更高的密度。
在圖3中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中，一半導體裝置具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中，一半導體裝置可以只有該第一層級的封裝，其中晶粒是直接機械及電氣地安裝到PCB上。
為了說明之目的，包含打線接合封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第二層級的封裝類型的任意組合來組態的半導體封裝的任何組合及其它電子構件可連接至PCB 52。在某些實施例中，電子裝置50包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子裝置及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子裝置。所產生的裝置不太可能發生故障且製造費用較低，從而降低消費者成本。
圖4a-4c係展示範例的半導體封裝。圖4a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的主動區域，該些類比或數位電路係被實施為形成在晶粒內之主動裝置、被動裝置、導電層及介電層並且根據該晶粒的電設計而電互連。例如，該電路可包含形成在半導體晶粒74的主動區域內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多層的導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著劑材料而被安裝至一中間載體78。封裝主體係包含一種例如是聚合物或陶瓷的絕緣封裝材料。導線80及焊線82係在半導體晶粒74及PCB 52之間提供電互連。封裝材料84係為了環境保護而沉積在該封裝之上以防止濕氣及微粒進入該封裝且污染晶粒74或焊線82。
圖4b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安裝在載體90之上。焊線94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或封裝材料100係沉積在半導體晶粒88及焊線94之上以提供物理支撐及電氣隔離給該裝置。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖4c中，半導體晶粒58係以覆晶型第一層級的封裝方式面向下安裝到中間載體106。半導體晶粒58的主動區域108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動裝置、被動裝置、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及主動區域108內之其它電路元件。半導體晶粒58係透過凸塊110電氣及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝方式利用凸塊112電氣及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112電連接至PCB 52中的導電信號線路54。一種模製化合物或封裝材料116係沉積在半導體晶粒58及載體106之上以提供物理支撐及電氣隔離給該裝置。該覆晶半導體裝置係提供從半導體晶粒58上的主動裝置到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳播距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
在一覆晶互連墊佈局中，所有或是基本上所有的信號墊都是位在半導體晶粒及對應的封裝基板的邊緣部份中。該些晶粒的信號墊係被配置在接近半導體晶粒的周邊之晶粒表面上，並且該些晶粒的電源及接地墊係被配置在晶粒表面上信號墊的內側。在對應的封裝基板上之信號墊係以一種與該晶粒墊佈局互補的方式被配置。信號線係從晶粒邊緣下方的信號墊被繞線(routed)離開晶粒覆蓋區，並且電源及接地線係被繞線至該晶粒覆蓋區下方的貫孔。
該些墊佈局係在晶片邊緣處提供高的信號線路逸散的繞線密度。該封裝基板具有較少的金屬層，因而利用該墊佈局建構的封裝可用更低的成本製成。因為金屬層較少，且因為貫孔的數目減少或是完全從信號傳送路徑消除，電性寄生現象係被降低並且該封裝可具有改良的效能。
一用於覆晶互連的晶粒墊佈局可以使得信號墊主要位在接近半導體晶粒的周邊，並且接地及電源墊主要位在該些信號墊的內側。該些信號墊可用一大致平行於該晶粒邊緣的列被配置。或者是，該些信號墊係以一個陣列的兩個或是多個平行於該晶粒邊緣的列被配置。在某些實施例中，在相鄰列中的墊是交錯的。半導體晶粒上設置該列或陣列的信號墊的區域係被稱為該晶粒的一周邊區域。
在其它實施例中，該些接地及電源墊係以一接近該半導體晶粒的中心之矩形陣列被配置。或者是，該半導體晶粒的一中央區域沒有墊。該些電源及接地墊亦可用一平行於該晶粒邊緣且靠近該些信號墊的列被配置、或可用一陣列的兩個或是多個平行於該晶粒邊緣且靠近該些信號墊的列被配置。半導體晶粒上設置該列或陣列的電源及接地墊的區域係被稱為該晶粒的一內側的區域。
圖5係展示晶粒墊佈局120的一實施例。信號墊122係以平行於晶粒邊緣126的列被配置在晶粒表面124上靠近該半導體晶粒的周邊處。信號墊122具有比圖1的習知混合的墊陣列中之墊更細的間距。電源墊128及接地墊130係以一陣列被配置在晶粒表面124的一內側的區域上。晶粒表面124的一中央區域132不包含任何墊(包括電源墊128及接地墊130在內)。
一對應於圖5的晶粒墊佈局120之基板墊的配置係被展示在一大致於圖6中的134之平面圖中。信號墊136、電源墊138及接地墊140係以一互補陣列被配置在基板表面142上，因而其可接收且分別連結至該些附接到該半導體晶粒上之對應墊的信號、電源及接地凸塊。在此配置中，所有與信號繞線相關連的墊136係位在該陣列的周邊，並且用於該陣列的周邊上的信號墊之逸散的繞線可直接橫過在下方的晶粒邊緣144以作為在該基板之最上面的金屬層中的線路146。在該基板上未在該陣列的周邊之信號墊136及電源墊138係藉由短的線路及貫孔連接至該基板中較深的金屬層。電源墊138係藉由短的線路(電源短線段或凸出)148透過電源貫孔150連接至下方的一金屬層中的電源線路，並且接地墊140係藉由短的線路(接地短線段或凸出)152透過接地貫孔154連接至下方的一金屬層中的電源線路。
在圖5及6中，所有的信號線都從信號墊136繞線穿離晶粒覆蓋區，並且所有的電源及接地線都繞線至晶粒覆蓋區下方的貫孔。於是，信號路徑中不需要短線段或貫孔，因而避免了信號傳送中的寄生現象。在可利用的線路形成技術所容許下，信號線路可以盡可能靠近地繞線，儘管若信號線路做的太靠近，信號干擾可能發生在相鄰的線中。在可利用的線路形成及凸塊連結技術所容許下，信號墊136可被做成盡可能的靠近。
圖7係展示覆晶封裝156的一部份，該覆晶封裝156具有一安裝在基板158的一表面的一晶粒附接區域上之半導體晶粒157。包含信號墊159、電源墊160及接地墊161的晶粒墊係被形成在半導體晶粒157的主動側155上或是在主動側155中。導電球或凸塊係附接到該些晶粒墊，並且至基板158的覆晶互連是藉由將該些球或凸塊連結到該基板之上方的金屬層162中對應的經圖案化的線路的互連位置上而達成。信號凸塊163係附接到信號墊159且連結到信號線路164上之互連位置。電源凸塊165係附接到電源墊160且連結到電源線路166上之互連位置，並且接地凸塊167係附接到接地墊161且連結到接地線路168上之互連位置。
基板158可以是一增層(build-up)型基板，其具有一或多層較薄之交替的介電層及金屬層黏貼到一較厚之中間的兩層的基板(稱為核心)的上表面及下表面的每個表面上。增層式基板158在頂端與底端上通常有相同數目的單一金屬層。因此，一種1-2-1增層式基板係具有一較薄的單一金屬層和一介電層一起黏貼到該核心的頂端與底端上，此總共有四個金屬層。一種2-2-2增層式基板係具有兩個較薄的單一金屬層和介電層一起黏貼到該核心的頂端與底端上，此總共有六個金屬層。一種3-2-3增層式基板係具有三個較薄的單一金屬層基板和介電層一起黏貼到該核心的頂端與底端上，此總共有八個金屬層。每一組額外的增層式的層會顯著地升高增層式基板的成本，因此需要較少層的電路佈局是所期望的。
該增層式製程可能需要藉由一種旋轉塗佈製程，以一層的方式施加一種介電材料在該核心的表面上、或是在一先前建立的增層式的層的表面上，接著金屬化該介電質的表面並且藉由一光罩及蝕刻製程來圖案化該金屬化。
基板158係包含作為核心的一印刷電路板，該印刷電路板在一介電質的頂表面及底表面上具有經圖案化的金屬層，亦即為一種兩金屬層的基板。該介電質在印刷電路板中的厚度通常是約500μm。實務上，在該核心上之金屬層中的特徵間距具有在大約100μm的範圍中之下限，並且貫孔抓取(capture)墊直徑具有在大約300μm的範圍中之下限。相對地，在該較薄的單一增層式的層中之介電質的厚度通常是約50μm。在增層式的層上之金屬層通常是比在該較厚的核心上之金屬層薄。在增層式的層內之金屬層中的特徵間距具有在大約50μm的範圍中之下限，並且貫孔抓取墊直徑具有在大約120μm的範圍中之下限。
在圖7的實施例中之基板158是一個增層式1-2-1類型的四金屬層基板。換言之，基板158係包含形成在中間較厚的兩金屬層基板172上之上方及下方薄的單一金屬層基板170及171。該兩金屬層基板172具有經圖案化的上方及下方的金屬層173及174。該單一金屬層基板170及171具有經圖案化的金屬層162及176。每個經圖案化的金屬層162、173、174及176都具有用於信號、電源及接地電路的線路。例如，金屬層173係包含專用於接地電路的線路177以及專用於電源電路的線路178，並且金屬層174係包含電源線路179及接地線路180。
下方的金屬層176係被圖案化以提供用於該封裝安裝在一例如是裝置的主機板的印刷電路板上的第二層級焊料凸塊互連的連結位置。尤其，接地凸塊181、信號凸塊182及電源凸塊183係附接到排列在封裝基板158的底面邊緣上的接地凸塊位置184、信號凸塊位置185及電源凸塊位置186。核心接地凸塊187及核心電源凸塊188係附接到排列在封裝基板158的底面上之晶粒下方的核心接地凸塊位置189及核心電源凸塊位置190。
上方的接地線路168及電源線路166係包含用於接地及電源凸塊167、165的覆晶安裝之位置，並且藉由在晶粒覆蓋區下方的貫孔191及192連接至金屬層173中的線路177及178。線路177及178係藉由貫孔198及193連接至金屬層174中的線路180及194。於是，線路180及194係藉由貫孔而連接至第二層級互連位置189及190(核心接地及核心電源)與184及186(接地及電源)。
晶粒信號墊159係被配置在靠近半導體晶粒的周邊處，並且在基板158上之對應的信號線路導線164係繞線在晶粒邊緣195的下方而離開晶粒覆蓋區。信號線路164係直接繞線到基板158大致覆蓋該些第二層級信號凸塊位置185的區域，因而上方的金屬層162中的信號線路至凸塊位置185的連接可被縮短並且主要是藉由貫孔196及197達成的，而在下方的金屬層173、174及176內具有最小的信號電路。該些第二層級信號凸塊以及該些向下延伸的貫孔可位在接地及電源凸塊及貫孔之間並且靠近接地及電源凸塊及貫孔。
一般而言，封裝基板中的接地線與信號線隔開的距離較佳是具有至少相當於和相鄰信號線間的距離相同的數量級，因而由信號產生的電場線走到接地而不是干擾到其它信號。因此，該第二金屬層173較佳是主要運作為一接地面，並且在上方的金屬層中的介電質厚度約等於或小於在上方的層上之相鄰信號線間的最小間隔。於是，用於封裝156的扇形展開的接地電路大部份是形成在該第二金屬層173中，該第二金屬層173係僅藉由該薄的上方層的介電質以和該上方的金屬層162隔開。在該上方及下方的單一金屬層基板中的介電質厚度可以是約50μm，因此在相鄰的信號線間之標稱距離是約50μm或更大的情況中，接地線及信號線之所期望的間隔係可獲得，而提供一穩定的微帶(microstrip)控制的阻抗傳輸線環境給信號。
如下所論述，有一些情況是小數目之選定的信號墊係位在晶粒的一內側的區域中(換言之，在晶粒的核心電路區域內)之接地及電源墊間。在設計需要時、或是晶粒電路使其為更佳的情況中，一位在半導體晶粒的核心電路區域內之接地或電源墊間的信號墊可具有一在基板上且在該晶粒的核心電路區域的覆蓋區內之對應的墊，並且可在一貫孔中直接進一步向下穿過該基板核心而繞線到一底層。
其它增層式基板亦可被利用，儘管如上指出的，隨著額外的層增加，成本會升高，因而具有較少層的基板可能是較佳的。在一種2-2-2基板被使用的情形中，頂端及底端增層式的層可幾乎是如同以上針對1-2-1基板所描述地被圖案化。在中間的基板上之金屬層可主要被利用於電源繞線，並且在該中間的基板之上及之下的增層式的層上之金屬層可主要被利用作為接地面。在增層式基板採用較多數量的層之情形中，在基板層上之佈局可被配置成使得信號貫孔在可行的範圍內被接地貫孔及電源貫孔所圍繞，以降低信號因電性寄生現象的劣化。
一種四層的增層型0-4-0積層(laminate)基板可在無增層式的層之情形下被利用，此係提供符合核心基板之粗略設計規則的特徵間距及貫孔抓取墊設計。避免對於增層的需要可在積層製備中提供顯著的成本降低。
其它的晶粒墊佈局可被做成為晶粒信號墊是配置在靠近晶粒的周邊處，並且晶粒電源及接地墊是配置在該些信號墊的內側上。在其它佈局配置中，信號墊係以一種與晶粒墊佈局互補的方式被配置、或是以信號線從信號墊在晶粒邊緣下方繞線離開晶粒覆蓋區並且電源及接地線繞線到在晶粒覆蓋區下方的貫孔的方式被配置。圖8a-8b、9a-9b、10a-10b以及11a-11b係展示墊佈局及對應的基板之四個說明的例子。
在圖8a的晶粒墊佈局200中，信號墊202係以一陣列的兩個平行於晶粒邊緣206之交錯的列被配置在晶粒表面204上靠近半導體晶粒的周邊處。信號墊202係被展示具有大約和例如圖5的單一列的實施例中之墊相同的間距，並且因此可在半導體晶粒的周邊上容納更多數目的信號墊。或者是，和單一列的實施例中之墊相同數目的墊可容納在兩列中並且交錯，因而墊間距及墊直徑以及對應的互連凸塊或球可以是較大的，此降低了製造成本。類似於圖5，電源墊208及接地墊210係以一陣列被配置在晶粒表面的一內側的區域上，該陣列具有一沒有墊的中央區域。應注意到的是，在一典型的晶粒中可存在比圖式中展示者多更多的晶粒墊，其中某些晶粒具有數百個墊。例如，半導體晶粒可具有總共500個墊，包含150個電源及接地墊以及350個信號墊。
一對應於圖8a的晶粒墊佈局200之基板墊的配置係被展示在一大致於圖8b的212處之平面圖中。信號墊214、電源墊216以及接地墊218係以一互補於圖8a的晶粒墊佈局之陣列被配置在基板表面220上，因而其可接收並且分別連結至該些附接到半導體晶粒204上對應的墊之信號、電源及接地凸塊。在此配置中，所有與信號繞線相關連的墊214係以一陣列的兩個交錯的列被配置在該陣列的周邊處，並且用於該陣列的周邊上之信號墊的逸散的繞線可直接橫過在下方的晶粒邊緣222而成為該基板之最上面的金屬層中的線路224。儘管信號墊214具有大約和圖6中的墊相同的間距，但信號線路224具有的間距大約是信號線路146間距的一半。換言之，對於一特定的墊間距而言，逸散密度可加倍。在基板220上未在該陣列的周邊之信號墊214及電源墊216係藉由短的線路及貫孔連接至該基板中較深的金屬層。在圖8b中，電源墊216係藉由電源短線段或凸出226透過電源貫孔228連接至在下方的一金屬層中之電源線路。接地墊218係藉由接地短線段或凸出230透過接地貫孔232連接至在下方的一金屬層中之電源線路。
圖9a係展示晶粒墊佈局234，其中信號墊236係以一平行於晶粒邊緣240的列配置在晶粒表面238上靠近該晶粒的周邊處。信號墊236係被展示具有和圖5中的墊大約相同的間距。電源墊242及接地墊244亦以一平行於晶粒邊緣240且在該列的信號墊236內側的列配置。在該列中，電源墊242可以和接地墊244為交替的。所有的墊可藉由交錯安排內側列中的墊與外側列中的信號墊而更緊密地形成。
通常，晶粒的主動層中的輸入/輸出電路係沿著該晶粒周邊且靠近一或多個邊緣被配置。將所有的墊限制到靠近半導體晶粒的周邊的列而形成一墊環，此係容許藉由減少在晶粒上的繞線量而在晶粒成本上有所降低，並且晶片設計工具可被利用在建構該晶粒上。
一對應於圖9a的晶粒墊佈局234的基板墊的配置係被展示在一大致於圖9b的250處之平面圖中。信號墊252、電源墊254及接地墊256係以一互補於圖9a的晶粒墊佈局234的陣列被配置在基板表面258上，因而其可接收並且分別連結至該些附接到半導體晶粒238上對應的墊之信號、電源及接地凸塊。在此配置中，所有與信號繞線相關連的墊252係以一列被配置在該陣列的周邊處，並且用於該陣列的周邊上的信號墊之逸散的繞線可直接橫過在下方的晶粒邊緣260以作為該基板之最上面的金屬層中的線路262。在基板258上該些信號墊的內側且靠近該陣列的周邊處之接地墊256及電源墊254係藉由短的線路及貫孔而連接至該基板中較深的金屬層。在圖9b中，電源墊254係藉由電源短線段或凸出264透過電源貫孔266連接到在下方的一金屬層中之電源線路。接地墊256係藉由接地短線段或凸出268透過接地貫孔269連接到在下方的一金屬層中之電源線路。
在圖9a與9b中，小數目的接地墊及/或小數目的電源墊可以位在該外側列中，較靠近晶粒邊緣處。在該基板中，接地墊及/或電源墊可用一對應的方式被配置。配置係可以具有最多10%、較通常是小於約5%、更通常是0%或小於約2%的接地及電源墊在外側列中，但是將電源或接地墊設置在外側列中會導致在信號墊逸散密度上的降低。該信號墊逸散密度可藉由最小化電源或接地墊在墊的外圍中的數目來最大化。在某些實施例中，在外側列中並沒有電源墊或接地墊。類似地，小數目的信號墊可設置在該晶粒的外圍內側的電源及接地墊之間，並且在該基板中，該些信號墊可用一對應的方式被配置。然而，此種配置可能需要利用到一下方的基板層，需要使用貫孔且增加了信號路徑長度。
如上所指出的，信號墊逸散密度係在接地及/或電源墊在外側列中的數目最小化時為最大化，於是該逸散密度可在沒有接地墊或電源墊在外側列中為最大值。然而，為了信號的電磁屏蔽，一用於射頻(RF)信號的信號墊可能在一側有一相鄰的接地墊、或是可在兩側旁邊有一信號墊以及一接地墊。信號墊逸散密度可被折衷到一有限的範圍，並且在一靠近晶粒的外圍之信號墊的兩側或三側上配置電源及/或接地墊可提供有用的折衷方案。
在圖10a的晶粒墊佈局270中，信號墊271係以一平行於晶粒邊緣273的列配置在晶粒表面272上靠近該晶粒的周邊處。信號墊271係被展示具有和圖5中的墊大約相同的間距。電源墊274及接地墊275係以一平行於晶粒邊緣273且在該列的信號墊271內側的列被配置。電源墊274及接地墊275已經減少。換言之，約具有如同在圖9a中所示的電源及接地墊的一半。電源墊274在該列中係與接地墊275交替。所有的墊可藉由交錯安排內側列中的墊與外側列中的信號墊而更緊密地形成。
如在圖10b中所繪，減少電源及接地墊係容許一佈局能夠在半導體晶粒的覆蓋區下具有更大的接地貫孔及電源貫孔，其係在大致於276處之平面圖中展示一對應於圖10a的晶粒墊佈局270之基板墊的配置。信號墊278、電源墊279及接地墊280係以一互補於圖10a的晶粒墊佈局的陣列被配置在基板表面281上，因而其可接收並且分別連結至該些附接到半導體晶粒272上對應的墊之信號、電源及接地凸塊。在此配置中，所有與信號繞線相關連的墊278係以一列被配置在該陣列的周邊處，並且用於該陣列的周邊上的信號墊之逸散的繞線可直接橫過在下方的晶粒邊緣282以作為基板281最上面的金屬層中的線路283。在基板281上信號墊內側且靠近該陣列的周邊的接地墊280及電源墊279係藉由短的線路及貫孔連接至該基板中較深的金屬層。電源墊279係藉由電源短線段或凸出284透過電源貫孔285連接到在下方的一金屬層中之電源線路。接地墊280係藉由接地短線段或凸出286透過接地貫孔287連接到在下方的一金屬層中之電源線路。
接地及電源貫孔的直徑一般是做成大約是線間距的2到3倍。對於較大的電源及接地貫孔尺寸而言，交替的短線段可具有不同的長度，因而如同在圖10b中所示，該電源及接地貫孔係以一交錯的陣列被配置。對於大約100μm的信號線逸散間距而言，在該接地貫孔及電源貫孔間之有效的貫孔間距可以是約220μm，並且該貫孔直徑可以是大到約250μm。具有較大貫孔的基板可以較不昂貴地製造，並且此種配置可在成品封裝的成本上提供顯著的降低。
在圖11a的晶粒墊佈局288中，信號墊289係以一大致正交的陣列的兩個平行於晶粒邊緣291的列被配置在晶粒表面290上靠近該半導體晶粒的周邊處。每個列中的信號墊289係被展示具有大約和圖8a的外側列中之墊相同的間距，並且該內側及外側列係被隔成比圖5中的單一列內的相鄰墊稍微開一些。換言之，在圖11a的正交的周邊陣列中有和圖8a之交錯的周邊陣列相同數目的信號墊289。在圖11a中，該正交的周邊信號間距陣列所占的面積稍大於圖8a之交錯的周邊信號間距陣列所占的面積；然而，該正交的陣列中最相近的墊間的間距係小於該交錯的陣列中最相近的墊間的間距，因而互連的幾何(亦即墊間距及墊直徑)以及對應的互連凸塊或球可更大降低製造成本。電源墊292及接地墊293係類似於圖5及8a以一陣列被配置在該晶粒表面之一內側的區域上，該陣列具有一沒有墊的中央區域。
一對應於晶粒墊佈局288之基板墊的配置係被展示在一大致於圖11b中的294處之平面圖中。信號墊295、電源墊296及接地墊297係以一互補於圖11a的晶粒墊佈局288的陣列被配置在基板表面298上，因而其可接收並且分別連結至該些附接到半導體晶粒290上對應的墊之信號、電源及接地凸塊。在此配置中，所有與信號繞線相關連的墊295係以一正交的陣列的兩個列被配置在該陣列的周邊處，並且用於該陣列的周邊上的信號墊之逸散的繞線可直接橫過在下方的晶粒邊緣300以作為該基板最上面的金屬層中的線路302。在基板298上未在該陣列的周邊之信號墊295及電源墊296係藉由短的線路及貫孔連接至該基板中較深的金屬層。電源墊296係藉由電源短線段或凸出304透過電源貫孔306連接至在下方的一金屬層中之電源線路。接地墊297係藉由接地短線段或凸出310透過接地貫孔312連接至在下方的一金屬層中之電源線路。
在圖8b、9b、10b及11b的實施例中的信號線係從信號墊繞線穿離晶粒覆蓋區，並且所有的電源及接地線係繞線到晶粒覆蓋區下方的貫孔。信號線路可全部繞線在該基板上之單一上方的金屬層中。於是，在信號路徑中不需要短線段或貫孔，因而避免信號傳送中的寄生現象。在可利用的線路形成的技術容許下，該些信號線路可做成盡可能的靠近。在可利用的線路形成及凸塊連結的技術容許下，該些信號墊可做成盡可能的靠近。
先前的例子係描繪其中沒有接地互連或電源互連是位在最靠近晶粒及基板上之晶粒覆蓋區的周邊的信號互連之間的實施例。沒有信號互連是位在該核心陣列相當內側而大約在晶粒及晶粒覆蓋區的中間之電源及接地互連之間。在某些情況中，一或一些信號互連可被設置在該核心陣列之內，通常是與接地互連相鄰的，於是用以將基板中的一或一些信號線繞線到在晶粒覆蓋區下方的貫孔，以和該基板中之下方的金屬層連接、或是將該基板上方的金屬層中的此種信號線從該晶粒覆蓋區的相當內側而在晶粒邊緣之下向外繞線。在某些情況中，在信號互連間的一或一些電源互連、或較通常是較外圍的一或一些接地互連可被設置在靠近該晶粒的周邊，因而靠近該基板上之晶粒覆蓋區的周邊。某些電路設計係將一時脈信號互連設置成較靠近一接地互連。
所有或實質所有的晶粒信號墊係以一列或是以一陣列被配置在靠近晶粒周邊處。所有或實質所有的晶粒電源及接地墊係設置在實質所有的晶粒信號墊的內側。尤其，分開靠近周邊的信號墊與核心中的接地及電源墊的優點可能會隨著未分開的墊數目或比例增加而顯著地劣化。未在一周邊列或一周邊陣列中的信號墊比例通常是小於所有信號墊的約10%，較通常是小於所有信號墊的約5%，並且更通常是所有信號墊的0%或是在0%至約2%的範圍中。未在信號墊的周邊列或周邊陣列內側的接地或電源墊比例通常是小於所有電源及接地墊的約10%，較通常是小於所有電源及接地墊的大約5%，並且更通常是所有信號墊的0%或是在0%至約2%的範圍中。
信號墊係以一列或是以一陣列沿著晶粒的整個周邊，亦即，沿著矩形晶粒所有四個邊緣被配置。在某些實施例中，信號墊係沿著比所有的晶粒邊緣少的邊緣被配置，並且特別可在其中信號墊是以一周邊列或是一周邊陣列沿著四個晶粒邊緣的任兩個或多個邊緣被配置的實施例中實現優點。
覆晶封裝可利用具有較少層的基板做成，並且在各種的層上之電路可有效地根據功能來配置，此係降低基板成本且改進效能。
圖12-17係描述其它具有各種互連結構的實施例，該些互連結構可和如圖5-11中所述的包含信號墊、電源墊及接地墊的晶粒墊佈局結合而被利用。更明確地說，半導體晶粒的接觸墊以及對應的互連導電線路可對應於晶粒墊佈局中的信號墊、電源墊或接地墊。圖12a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或碳化矽的主體基板材料322以供結構支撐的半導體晶圓320。複數個半導體晶粒或構件324係形成在晶圓320上且藉由如上所述的切割道326分開。
圖12b係展示半導體晶圓320的一部份的橫截面圖。每個半導體晶粒324具有一背表面328以及包含類比或數位電路的主動表面330，該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能電互連的主動裝置、被動裝置、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在主動表面330內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒324亦可包含整合被動裝置(IPD)，例如電感器、電容器及電阻器，以供RF信號處理使用。在一實施例中，半導體晶粒324是一覆晶類型的半導體晶粒。
一導電層332係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在主動表面330之上。導電層332可以是Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料的一或多層。導電層332係運作為電連接至主動表面330上的電路之接觸墊。
圖12c係展示具有一形成在接觸墊332之上的互連結構的半導體晶圓320的一部份。一導電凸塊材料334係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落(ball drop)、或是網版印刷製程而沉積在接觸墊332之上。凸塊材料334可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其組合，其具有一選配的助熔(flux)溶劑。例如，凸塊材料334可以是共晶Sn/Pb、高鉛的焊料或是無鉛的焊料。凸塊材料334是大致順應的(compliant)並且在相當於約200克的垂直荷重的力下進行大於約25μm的塑性變形。凸塊材料334係利用一合適的附著或連結製程連結到接觸墊332。例如，凸塊材料334可以壓縮連結到接觸墊332。凸塊材料334亦可藉由加熱該材料超過其熔點來進行回焊以形成球或凸塊336，即如同在圖12d中所示者。在某些應用中，凸塊336係進行二次回焊以改善至接觸墊332的電連接。凸塊336係代表一種可形成在接觸墊332之上的互連結構類型。該互連結構亦可以使用柱形凸塊、微凸塊或是其它電互連。
圖12e係展示互連結構的另一實施例，其係以複合的凸塊338形成在接觸墊332之上，該凸塊338包含一不可熔或不可分解的部份340以及可熔或可分解的部份342。該可熔或可分解的特質以及不可熔或不可分解的特質係針對凸塊338關於回焊條件所界定的。該不可熔的部份340可以是Au、Cu、Ni、高鉛的焊料、或是鉛錫合金。該可熔的部份342可以是Sn、無鉛的合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-銦(In)合金、共晶焊料、錫和Ag、Cu或Pb的合金、或是其它相對低溫熔化的焊料，在一實施例中，給定一接觸墊332 100μm的寬度或直徑，該不可熔的部份340高度大約是45μm並且可熔的部份342高度大約是35μm。
圖12f係展示互連結構的另一實施例，其係形成在接觸墊332之上而成為導電柱346之上的凸塊344。凸塊344是可熔或可分解的，並且導電柱346是不可熔或不可分解的。該可熔或可分解的特質以及不可熔或不可分解的特質係相關於回焊條件加以界定。凸塊344可以是Sn、無鉛的合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-In合金、共晶焊料、錫和Ag、Cu或Pb的合金、或是其它相對低溫熔化的焊料。導電柱346可以是Au、Cu、Ni、高鉛的焊料、或是鉛錫合金。在一實施例中，導電柱346是一Cu柱，並且凸塊344是一焊料蓋。給定一接觸墊332 100μm的寬度或直徑，導電柱346高度大約是45μm，並且凸塊344高度大約是35μm。
圖12g係展示互連結構的另一實施例，其係形成在接觸墊332之上而為具有突點(asperity)350的凸塊材料348。類似於凸塊材料334，凸塊材料348在回焊條件下是軟的且可變形的，具有低的屈伏強度(yield strength)以及高的致衰壞伸長率(elongation to failure)。突點350係以電鍍的表面處理而形成，並且為了說明之目的係在圖式中被誇大展示。突點350的等級一般是在大約1-25μm的數量級。該突點亦可形成在凸塊336、複合的凸塊338以及凸塊344上。
在圖12h中，半導體晶圓320係利用一鋸條或雷射切割工具352透過切割道326被單切為個別的半導體晶粒324。
圖13a係展示一具有導電線路356的基板或PCB 354。基板354可以是單面FR5層壓板或是雙面BT-樹脂層壓板。半導體晶粒324係被設置以使得凸塊材料334係和導電線路356上之互連位置對準，請參見圖21a-21g。或者是，凸塊材料334可和形成在基板354上的導電墊或是其它互連位置對準。凸塊材料334係比導電線路356寬。在一實施例中，對於150μm的凸塊間距，凸塊材料334具有小於100μm的寬度，並且導電線路或墊356具有35μm的寬度。接觸墊332及導電線路356可對應於圖5-11的晶粒墊佈局中之信號墊、電源墊或接地墊。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料334壓到導電線路356之上。該力F可在高溫下施加。由於凸塊材料334之順應的本質，該凸塊材料係變形或突出在導電線路356的頂表面及側表面周圍，被稱為導線上的凸塊(BOL)。尤其，在相當於大約200克的垂直荷重之力F下，壓力的施加係使得凸塊材料334進行大於約25μm的塑性變形並且覆蓋導電線路的頂表面及側表面，即如同在圖13b中所示者。凸塊材料334亦可藉由將該凸塊材料和導電線路實體接觸並且接著在一回焊溫度下回焊該凸塊材料以冶金連接至導電線路356。
藉由使得導電線路356比凸塊材料334窄，導電線路的間距可被降低以增加繞線密度以及I/O數目。較窄的導電線路356係降低使凸塊材料334變形在導電線路的周圍所需的力F。例如，該必要的力F可以是使凸塊材料抵靠比凸塊材料寬的導電線路或墊變形所需的力之30-50%。較小的壓力F對於細間距互連及小的晶粒維持具有一指定容限之共面性以及達成均勻的z向變形及高可靠度的互連結合是有用的。此外，將凸塊材料334變形在導電線路356的周圍係將該凸塊機械式鎖到該線路以避免在回焊期間晶粒移動或是晶粒浮接。
圖13c係展示形成在半導體晶粒324的接觸墊332之上的凸塊336。半導體晶粒324係被設置以使得凸塊336和導電線路356上的互連位置對準。或者是，凸塊336可和形成在基板354上的導電墊或其它互連位置對準。凸塊336係比導電線路356寬。接觸墊332及導電線路356可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊336壓到導電線路356之上。該力F可在高溫下施加。由於凸塊336之順應的本質，該凸塊係變形或突出在導電線路356的頂表面及側表面周圍。尤其，壓力的施加係使得凸塊材料336進行塑性變形並且覆蓋導電線路356的頂表面及側表面。凸塊336亦可藉由在回焊溫度下使該凸塊和該導電線路實體接觸以冶金連接至導電線路356。
藉由使得導電線路356比凸塊336窄，導電線路的間距可被降低以增加繞線密度及I/O數目。較窄的導電線路356係降低將凸塊336變形在導電線路的周圍所需的力F。例如，該必要的力F可以是使一凸塊抵靠一比該凸塊寬的導電線路或墊變形所需的力之30-50%。較低的壓力F對於細間距互連及小的晶粒維持在一指定容限內的共面性以及達成均勻的z向變形及高可靠度的互連結合是有用的。此外，將凸塊336變形在導電線路356的周圍係將該凸塊機械式鎖到該線路以避免在回焊期間的晶粒移動或晶粒浮接。
圖13d係展示形成在半導體晶粒324的接觸墊332之上的複合的凸塊338。半導體晶粒324係被設置以使得複合的凸塊338和導電線路356上的互連位置對準。或者是，複合的凸塊338可和形成在基板354上的導電墊或其它互連位置對準。複合的凸塊338係比導電線路356寬。接觸墊332及導電線路356可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
一壓力或力F係被施加至半導體晶粒324的背表面328以將可熔的部份342壓到導電線路356之上。該力F可在高溫下施加。由於可熔的部份342之順應的本質，該可熔的部份係變形或突出在導電線路356的頂表面及側表面周圍。尤其，壓力的施加係使得可熔的部份342進行塑性變形並且覆蓋導電線路356的頂表面及側表面。複合的凸塊338亦可藉由在回焊溫度下使可熔的部份342和該導電線路實體接觸以冶金連接至導電線路356。該不可熔的部份340在壓力或溫度的施加期間並不熔化或變形，並且保持其高度及形狀而作為在半導體晶粒324及基板354間之一垂直的間隙。該在半導體晶粒324及基板354間之額外的位移係在配接的表面之間提供較大的共面性容限。
在一回焊製程期間，半導體晶粒324上之大數目的(例如，數千個)複合的凸塊338係附接到基板354的導電線路356上之互連位置。某些凸塊338可能未能夠適當地連接到導電線路356，特別是當晶粒324被扭曲時。回想起複合的凸塊338係比導電線路356寬。在施加一適當的力之下，該可熔的部份342係變形或突出在導電線路356的頂表面及側表面周圍，並且將複合的凸塊338機械式鎖到該導電線路。該機械式緊密連接係藉由該可熔的部份342的本質而形成，該本質是比導電線路356軟且更順應，因而變形在該導電線路的頂表面之上以及在該導電線路的側表面周圍以得到較大的接觸表面積。在複合的凸塊338以及導電線路356之間的機械式緊密連接係在回焊期間將該凸塊保持在該導電線路，亦即，該凸塊及導電線路並不失去接觸。於是，複合的凸塊338配接到導電線路356係減少凸塊互連的失敗。
圖13e係展示形成在半導體晶粒324的接觸墊332之上的導電柱346及凸塊344。半導體晶粒324係被設置以使得凸塊344和導電線路356上之互連位置對準。或者是，凸塊344可和形成在基板354上的導電墊或其它互連位置對準。凸塊344係比導電線路356寬。接觸墊332及導電線路356可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊344壓到導電線路356之上。該力F可在高溫下施加。由於凸塊344之順應的本質，該凸塊係變形或突出在導電線路356的頂表面及側表面周圍。尤其，壓力的施加係使得凸塊344進行塑性變形並且覆蓋導電線路356的頂表面及側表面。導電柱346及凸塊344亦可藉由在回焊溫度下使該凸塊和該導電線路實體接觸以冶金連接至導電線路356。導電柱346在壓力或溫度的施加期間並不熔化或變形，並且保持其高度及形狀而成為在半導體晶粒324及基板354間之一垂直的間隙。該在半導體晶粒324及基板354間之額外的位移係在配接的表面之間提供較大的共面性容限。該較寬的凸塊344及較窄的導電線路356具有類似以上針對凸塊材料334及凸塊336所述的低必要的壓力及機械式鎖住的特點及優點。
圖13f係展示形成在半導體晶粒324的接觸墊332之上的具有突點350的凸塊材料348。半導體晶粒324係被設置以使得凸塊材料348係和導電線路356上的互連位置對準。或者是，凸塊材料348可和形成在基板354上的導電墊或其它互連位置對準。凸塊材料348係比導電線路356寬。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料348壓到導電線路356之上。該力F可在高溫下施加。由於凸塊材料348之順應的本質，該凸塊係變形或突出在導電線路356的頂表面及側表面周圍。尤其，壓力的施加係使得凸塊材料348進行塑性變形並且覆蓋導電線路356的頂表面及側表面。此外，突點350係冶金連接至導電線路356。突點350的尺寸係做成大約1-25μm的數量級。
圖13g係展示基板或PCB 358具有成角度或傾斜的側邊之梯形導電線路360。凸塊材料361係被形成在半導體晶粒324的接觸墊332之上。半導體晶粒324係被設置以使得凸塊材料361和導電線路360上的互連位置對準。或者是，凸塊材料361可和形成在基板358上的導電墊或其它互連位置對準。凸塊材料361係比導電線路360寬。接觸墊332及導電線路360可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料361壓到導電線路360之上。該力F可在高溫下施加。由於凸塊材料361之順應的本質，該凸塊材料係變形或突出在導電線路360的頂表面及側表面周圍。尤其，壓力的施加係使得凸塊材料361在力F下進行塑性變形，以覆蓋導電線路360的頂表面以及傾斜的側表面。凸塊材料361亦可藉由將該凸塊材料和導電線路實體接觸並且接著在一回焊溫度下回焊該凸塊材料以冶金連接至導電線路360。
圖14a-14d係展示半導體晶粒324以及具有一不可熔或不可分解的部份364及可熔或可分解的部份366之細長複合的凸塊362之一BOL實施例。該不可熔的部份364可以是Au、Cu、Ni、高鉛的焊料、或是鉛錫合金。該可熔的部份366可以是Sn、無鉛的合金、Sn-Ag合金、Sn-Ag-Cu合金、Sn-Ag-In合金、共晶焊料、錫和Ag、Cu或Pb的合金、或是其它相對低溫熔化的焊料。該不可熔的部份364比該可熔的部份366構成複合的凸塊362之較大的一部分。該不可熔的部份364係固定到半導體晶粒324的接觸墊332。
半導體晶粒324係被設置以使得複合的凸塊362係和形成在基板370上之導電線路368上的互連位置對準，即如同在圖14a中所示者。複合的凸塊362係沿著導電線路368漸縮，亦即，該複合的凸塊具有楔形，沿著導電線路368的長度方向上較長，而橫跨該導電線路的方向上較窄。複合的凸塊362之漸縮特點係出現在沿著導電線路368的長度方向上。圖14a中的繪圖係展示該較短的特點或變窄的漸縮是與導電線路368共線的。垂直於圖14a的圖14b中的繪圖係展示該楔形複合的凸塊362之較長的特點。複合的凸塊362之較短的特點係比導電線路368寬。該可熔的部份366在壓力施加及/或以熱回焊時分解在導電線路368的周圍，即如圖14c及14d中所示者。該不可熔的部份364在回焊期間並不熔化或變形，並且保持其外形及形狀。該不可熔的部份364的尺寸可被設為在半導體晶粒324及基板370之間提供一間隙距離。一例如是Cu OSP的處理可施加到基板370。接觸墊332及導電線路368可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
在一回焊製程期間，半導體晶粒324上之大數目的(例如，數千個)複合的凸塊362係附接到基板370的導電線路368上之互連位置。某些凸塊362可能未能夠適當地連接到導電線路368，特別是半導體晶粒324被扭曲時。回想起複合的凸塊362係比導電線路368寬。在施加一適當的力之下，該可熔的部份366係變形或突出在導電線路368的頂表面及側表面周圍，並且將複合的凸塊362機械式鎖到該導電線路。該機械式緊密連接係藉由該可熔的部份366之本質而形成，該本質係比導電線路368軟且較順應的，因而變形在該導電線路的頂表面及側表面周圍以得到較大的接觸面積。複合的凸塊362的楔形係增加在該凸塊及導電線路間的接觸面積，例如，沿著圖14b及14d之較長的特徵方向增加，而沒有犧牲到沿著圖14a及14c之較短的特徵方向上的間距。在複合的凸塊362及導電線路368間之機械式緊密連接係在回焊期間將該凸塊保持在該導電線路，亦即，該凸塊及導電線路並不失去接觸。於是，配接到導電線路368之複合的凸塊362係減少凸塊互連的失敗。
圖15a-15d係展示半導體晶粒324的一BOL實施例，其中類似於圖12c，凸塊材料374係形成在接觸墊332之上。在圖15a中，凸塊材料374是大致順應的，並且在一相當於大約200克的垂直荷重之力下進行大於約25μm的塑性變形。凸塊材料374係比基板378上的導電線路376寬。複數個突點380係以一大約1-25μm的數量級之高度形成在導電線路376上。
半導體晶粒324係被設置以使得凸塊材料374和導電線路376上的互連位置對準。或者是，凸塊材料374可和形成在基板378上的導電墊或其它互連位置對準。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料374壓到導電線路376及突點380之上，即如同在圖15b中所示者。該力F可在高溫下施加。由於凸塊材料374之順應的本質，該凸塊材料係變形或突出在導電線路376的頂表面及側表面以及突點380周圍。尤其，壓力的施加係使得凸塊材料374進行塑性變形並且覆蓋導電線路376的頂表面及側表面以及突點380。凸塊材料374的塑性流動係在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間產生巨觀的機械式緊密連接點。凸塊材料374的塑性流動係發生在導電線路376的頂表面及側表面以及突點380周圍，但並不過度地延伸到基板378之上，否則可能造成電氣短路及其它缺陷。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械式緊密連接係在不顯著增加連結力之下，提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械式緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。接觸墊332及導電線路376可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
圖15c係展示其中凸塊材料374比導電線路376窄的另一BOL實施例。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料374壓到導電線路376及突點380之上。該力F可在高溫下施加。由於凸塊材料374之順應的本質，該凸塊材料係變形或突出在導電線路376的頂表面及突點380之上。尤其，壓力的施加係使得凸塊材料374進行塑性變形並且覆蓋導電線路376的頂表面及突點380。凸塊材料374的塑性流動係在該凸塊材料以及導電線路376的頂表面及突點380之間產生巨觀的機械式緊密連接點。在該凸塊材料以及導電線路376的頂表面及突點380之間的機械式緊密連接係在不顯著增加連結力之下，提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料以及導電線路376的頂表面及突點380之間的機械式緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。
圖15d係展示另一BOL實施例，其中凸塊材料374形成在導電線路376的一邊緣之上，亦即，部份的凸塊材料在該導電線路之上，而部份的凸塊材料則不在該導電線路之上。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料374壓到導電線路376及突點380之上。該力F可在高溫下施加。由於凸塊材料374之順應的本質，該凸塊材料係變形或突出在導電線路376的頂表面及側表面及突點380之上。尤其，壓力的施加係使得凸塊材料374進行塑性變形並且覆蓋導電線路376的頂表面及側表面及突點380。凸塊材料374的塑性流動係在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間產生巨觀的機械式緊密連接。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械式緊密連接係在不顯著增加連結力之下提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料與導電線路376的頂表面及側表面以及突點380之間的機械式緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。
圖16a-16c係展示半導體晶粒324的一BOL實施例，其中類似於圖12c，凸塊材料384形成在接觸墊332之上。一尖端386係從凸塊材料384的主體延伸成為一階梯形凸塊，其中尖端386比凸塊材料384的主體窄，即如同在圖16a中所示者。半導體晶粒324係被設置以使得凸塊材料384和基板390上的導電線路388上之互連位置對準。更明確地說，尖端386係被設置在導電線路388上的互連位置之中央上。或者是，凸塊材料384及尖端386可和形成在基板390上的導電墊或其它互連位置對準。凸塊材料384係比基板390上的導電線路388寬。
導電線路388是大致順應的，並且在一相當於大約200克的垂直荷重的力之下進行大於約25μm的塑性變形。一壓力或力F係被施加至半導體晶粒324的背表面328以將尖端384壓到導電線路388之上。該力F可在高溫下施加。由於導電線路388之順應的本質，該導電線路係變形在尖端386的周圍，即如同在圖16b中所示者。尤其，壓力的施加係使得導電線路388進行塑性變形並且覆蓋尖端386的頂表面及側表面。接觸墊332及導電線路388可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
圖16c係展示另一BOL實施例，其中圓形的凸塊材料394係形成在接觸墊332之上。一尖端396係從凸塊材料394的主體延伸以形成一柱形凸塊，其中該尖端比凸塊材料394的主體窄。半導體晶粒324係被設置以使得凸塊材料394和基板400上的導電線路398上之互連位置對準。更明確地說，尖端396係被設置在導電線路398上的互連位置之中央上。或者是，凸塊材料394及尖端396可和形成在基板400上的導電墊或其它互連位置對準。凸塊材料394係比基板400上的導電線路398寬。
導電線路398是大致順應的，並且在一相當於大約200克的垂直荷重的力之下進行大於約25μm的塑性變形。一壓力或力F係被施加至半導體晶粒324的背表面328以將尖端396壓到導電線路398之上。該力F可在高溫下施加。由於導電線路398之順應的本質，該導電線路係變形在尖端396周圍。尤其，壓力的施加係使得導電線路398進行塑性變形，並且覆蓋尖端396的頂表面及側表面。接觸墊332及導電線路398可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
圖13a-13g、14a-14d及15a-15d中所述的導電線路亦可以是如圖16a-16c中所述之順應的材料。
圖17a-17b係展示半導體晶粒324的一BOL實施例，其中類似於圖11c，凸塊材料404係形成在接觸墊332之上。凸塊材料404是大致順應的，並且在一相當於大約200克的垂直荷重的力之下進行大於約25μm的塑性變形。凸塊材料404係比基板408上的導電線路406寬。一具有開口412及導電的側壁414之導電貫孔410係穿過導電線路406而形成，即如同在圖17a中所示者。接觸墊332及導電線路406可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。
半導體晶粒324係被設置以使得凸塊材料404和導電線路406上的互連位置對準，請參見圖21-21g。或者是，凸塊材料404可和形成在基板408上的導電墊或其它互連位置對準。一壓力或力F係被施加至半導體晶粒324的背表面328以將凸塊材料404壓到導電線路406之上並且壓入導電貫孔410的開口412中。該力F可在高溫下施加。由於凸塊材料404之順應的本質，該凸塊材料係變形或突出在導電線路406的頂表面及側表面周圍且進入到導電貫孔410的開口412中，即如同在圖17b中所示者。尤其，壓力的施加係使得凸塊材料404進行塑性變形並且覆蓋導電線路406的頂表面及側表面且進入到導電貫孔410的開口412中。因此，凸塊材料404係電連接至導電線路406及導電的側壁414以供穿過基板408的z向垂直的互連使用。凸塊材料404的塑性流動係在該凸塊材料與導電線路406的頂表面及側表面以及導電貫孔410的開口412之間產生機械式緊密連接。在該凸塊材料與導電線路406的頂表面及側表面以及導電貫孔410的開口412之間的機械式緊密連接係在不顯著增加連結力之下提供一具有個別的表面間較大的接觸面積之強健的連接。在該凸塊材料與導電線路406的頂表面及側表面以及導電貫孔410的開口412之間的機械式緊密連接亦降低在例如是封裝的後續製程期間橫向的晶粒移動。由於導電貫孔410係和凸塊材料404一起被形成在該互連位置之內，因此總基板互連面積係減少。
在圖13a-13g、14a-14d、15a-15d、16a-16c及17a-17b的BOL實施例中，藉由使導電線路比互連結構窄，導電線路的間距可被降低以增加繞線密度及I/O數目。較窄的導電線路係降低將互連結構變形在導電線路的周圍所需的力F。例如，該必要的力F可以是使一凸塊抵靠一比該凸塊寬的導電線路或墊變形所需的力之30-50%。該較低的壓力F對於細間距互連及小的晶粒維持在一指定容限內的共面性以及達成均勻的z向變形及高可靠度的互連結合是有用的。此外，將互連結構變形在導電線路的周圍係將該凸塊機械式鎖到該線路以避免在回焊期間的晶粒移動或晶粒浮接。
圖18a-18c係展示一種模具底膠填充(MUF)製程以將封裝材料沉積在半導體晶粒及基板間的凸塊周圍。圖18a係展示半導體晶粒324利用圖13b的凸塊材料334而安裝到基板354，並且被設置在凹槽(chase)模具420的上方模具支撐件416及下方模具支撐件418之間。圖13a-13g、14a-14d、15a-15d、16a-16c及17a-17b之其它的半導體晶粒及基板之組合亦可設置在凹槽模具420的上方模具支撐件416及下方模具支撐件418之間。該上方模具支撐件416係包含可壓縮的離型膜(releasing film)422。
在圖18b中，上方模具支撐件416及下方模具支撐件418被放在一起以封入半導體晶粒324及基板354，其具有一開放空間在該基板之上且在該半導體晶粒及基板之間。可壓縮的離型膜422係貼合半導體晶粒324的背表面328及側表面以阻擋封裝材料在這些表面上的形成。一種處於液態的封裝材料424係利用噴嘴426而被注入到凹槽模具420的一側中，而一選配的真空輔助428從相反的側邊吸壓以將該封裝材料均勻地填入基板354之上的開放空間以及在半導體晶粒324及基板354之間的開放空間。封裝材料424可以是聚合物複合材料(例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯)、或是具有適合的填充劑之聚合物。封裝材料424是非導電的並且在環境上保護半導體裝置免於接觸到外部的元素及污染物。可壓縮的材料422係避免封裝材料424流到半導體晶粒324的背表面328之上及側表面的周圍。封裝材料424係被固化。半導體晶粒324的背表面328及側表面係保持露出自封裝材料424。
圖18c係展示MUF及模具過度填充(MOF)，亦即，在沒有可壓縮的材料422下的一實施例。半導體晶粒324及基板354係被設置在凹槽模具420的上方模具支撐件416及下方模具支撐件418之間。該上方模具支撐件416及下方模具支撐件418係被放在一起以封入半導體晶粒324及基板354，其具有一開放空間在該基板之上、在該半導體晶粒的周圍且在該半導體晶粒及基板之間。處於液態的封裝材料424係利用噴嘴426而被注入到凹槽模具420的一側中，而一選配的真空輔助428係從相反的側邊吸壓以將該封裝材料均勻地填入在半導體晶粒324的周圍且在基板354之上的開放空間以及在半導體晶粒324及基板354之間的開放空間。封裝材料424係被固化。
圖19係展示將封裝材料沉積在半導體晶粒324的周圍且在半導體晶粒324及基板354之間的間隙中的另一實施例。半導體晶粒324及基板354係藉由屏障(dam)430圍住。封裝材料432係以液態從噴嘴434分配到屏障430中，以填入基板354之上的開放空間以及在半導體晶粒324及基板354之間的開放空間。從噴嘴434分配的封裝材料432的量係被控制在不覆蓋半導體晶粒324的背表面328或側表面下填入屏障430。封裝材料432係被固化。
圖20係展示在圖18a、18c及19的MUF製程之後的半導體晶粒324及基板354。封裝材料424係均勻地散佈在基板354之上且在半導體晶粒324及基板354之間的凸塊材料334的周圍。
圖21a-21g係展示在基板或PCB 440上之各種的導電線路佈局的俯視圖。在圖21a中，導電線路442是一形成在基板440上具有一體型(integrated)凸塊墊或互連位置444之直的導體。基板凸塊墊444的側邊可以是和導電線路442共線的。在習知技術中，一焊料對準開口(SRO)通常是形成在該互連位置之上，以在回焊期間限制凸塊材料。該SRO會增加互連間距且減少I/O數目。相對地，遮罩層446可形成在基板440的一部份之上；然而，該遮罩層並未形成在導電線路442的基板凸塊墊444的周圍。換言之，導電線路442中被設計來和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層446的任何SRO。
半導體晶粒324係被設置在基板440之上，並且凸塊材料係和基板凸塊墊444對準。凸塊材料係藉由使該凸塊材料和該凸塊墊實體接觸並且接著在一回焊溫度下回焊該凸塊材料以電氣且冶金連接至基板凸塊墊444。
在另一實施例中，一導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或網版印刷製程以沉積在基板凸塊墊444之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及其組合，其具有一選配的助熔溶劑。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一合適的附著或連結製程來連結到基板凸塊墊444。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來回焊，以形成凸塊或互連448，即如同在圖21b中所示者。在某些應用中，凸塊448係進行二次回焊以改善到基板凸塊墊444的電氣接觸。在該窄的基板凸塊墊444周圍的凸塊材料係在回焊期間維持晶粒的位置。
在高繞線密度的應用中，最小化導電線路442的逸散間距是所期望的。在導電線路442之間的逸散間距可藉由消除用於回焊限制目的之遮罩層，亦即，藉由在沒有遮罩層下回焊凸塊材料而被減少。由於沒有SRO被形成在晶粒凸塊墊332或基板凸塊墊444的周圍，所以導電線路442可用較細的間距形成，亦即，導電線路442可被設置成較靠在一起或是較靠近附近的結構。在基板凸塊墊444周圍沒有SRO之下，導電線路442間的間距係給定為P=D+PLT+W/2，其中D是凸塊448的基底直徑，PLT是晶粒設置容限，並且W是導電線路442的寬度。在一實施例中，給定100μm的凸塊基底直徑、10μm的PLT、以及30μm的線路線寬，導電線路442之最小的逸散間距是125μm。該無遮罩的凸塊形成係免去需要考量到如習知技術中可見的相鄰開口間之遮罩材料的孔帶(ligament)間隔、焊料遮罩對準容限(SRT)、以及最小可解析的SRO。
當該凸塊材料在沒有遮罩層下被回焊以將晶粒凸塊墊332冶金且電連接至基板凸塊墊444時，潤濕及表面張力係使得該凸塊材料維持自我局限(self-confinement)且被保持在晶粒凸塊墊332與基板凸塊墊444及基板440中緊鄰導電線路442且實質在該凸塊墊的覆蓋區中的部份之間的空間內。
為了達成該所要的自我局限性質，凸塊材料可在置放於晶粒凸塊墊332或基板凸塊墊444上之前被浸沒在一助熔溶劑中，以選擇性地使得該凸塊材料所接觸的區域比導電線路442周圍的區域更濕潤。該熔化的凸塊材料係由於該助熔溶劑的可濕性而維持局限在實質由凸塊墊所界定的區域內。該凸塊材料並不溢出到較不濕潤的區域。一薄的氧化層或是其它絕緣層可形成在其中不打算有凸塊材料的區域之上，以使該區域較不濕潤。因此，晶粒凸塊墊332或基板凸塊墊444周圍並不需要有遮罩層440。
圖21c係展示平行的導電線路452為直的導體之另一實施例，其中一體型矩形凸塊墊或互連位置454形成在基板450上。在此例中，基板凸塊墊454係比導電線路452寬，但是小於配接的凸塊寬度。基板凸塊墊454的側邊可以是平行於導電線路452。遮罩層456可形成在基板450的一部份之上；然而，該遮罩層並未形成在導電線路452的基板凸塊墊454的周圍。換言之，導電線路452中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層446的任何SRO。
圖21d係展示以多個列的一陣列配置的導電線路460及462的另一實施例，其中偏置的一體型凸塊墊或互連位置464形成在基板466上以得到最大的互連密度及容量。交替的導電線路460及462係包含一用於繞線到凸塊墊464的肘部。每個基板凸塊墊464的側邊係和導電線路460及462共線的。遮罩層468可形成在基板466的一部份之上；然而，遮罩層468並未形成在導電線路460及462的基板凸塊墊464的周圍。換言之，導電線路460及462中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層468的任何SRO。
圖21e係展示以多個列的一陣列配置的導電線路470及472的另一實施例，其中偏置的一體型凸塊墊或互連位置474形成在基板476上以得到最大的互連密度及容量。交替的導電線路470及472係包含一用於繞線到凸塊墊474的肘部。在此例中，基板凸塊墊474是圓形的並且比導電線路470及472寬，但是小於配接的互連凸塊材料的寬度。遮罩層478可形成在基板476的一部份之上；然而，遮罩層478並未形成在導電線路470及472的基板凸塊墊474的周圍。換言之，導電線路470及472中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層478的任何SRO。
圖21f係展示以多個列的一陣列配置的導電線路480及482的另一實施例，其中偏置的一體型凸塊墊或互連位置484形成在基板486上以得到最大的互連密度及容量。交替的導電線路480及482係包含一用於繞線到凸塊墊484的肘部。在此例中，基板凸塊墊484是矩形的並且比導電線路480及482寬，但是小於配接的互連凸塊材料的寬度。遮罩層488可形成在基板486的一部份之上；然而，遮罩層488並未形成在導電線路480及482的基板凸塊墊484的周圍。換言之，導電線路480及482中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層488的任何SRO。
作為互連製程的一例子，半導體晶粒324係被設置在基板466之上，並且凸塊材料334係和圖21d的基板凸塊墊464對準。凸塊材料334係藉由如同圖13a-13g、14a-14d、15a-15d、16a-16c及17a-17b所述，加壓該凸塊材料或是藉由使該凸塊材料和該凸塊墊實體接觸並且接著在一回焊溫度下回焊該凸塊材料，以電氣及冶金連接至基板凸塊墊464。
在另一實施例中，一導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落或網版印刷的製程沉積在基板凸塊墊464之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及其組合，其具有一選配的助熔溶劑。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一合適的附著或連結製程連結到基板凸塊墊464。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點而被回焊以形成凸塊或互連490，即如同在圖21g中所示者。在某些應用中，凸塊490係進行二次回焊以改善到基板凸塊墊464的電氣接觸。該窄的基板凸塊墊464周圍的凸塊材料係維持在回焊期間晶粒的置放。凸塊材料334或凸塊490亦可形成在圖21a-21g的基板凸塊墊配置上。
在高繞線密度的應用中，最小化圖21a-21g的導電線路460及462或是其它導電線路配置的逸散間距是所期望的。在導電線路460及462之間的逸散間距可藉由消除用於回焊限制目的之遮罩層，亦即，藉由在沒有遮罩層下回焊凸塊材料而被減少。由於沒有SRO被形成在晶粒凸塊墊332或基板凸塊墊464的周圍，所以導電線路460及462可用較細的間距形成，亦即，導電線路460及462可被設置成較靠在一起或是較靠近附近的結構。在基板凸塊墊464周圍沒有SRO之下，導電線路460及462間的間距係給定為P=D/2+PLT+W/2，其中D是凸塊490的基底直徑，PLT是晶粒設置容限，並且W是導電線路460及462的寬度。在一實施例中，給定100μm的凸塊基底直徑、10μm的PLT、以及30μm的線路線寬，導電線路460及462之最小的逸散間距是125μm。該無遮罩的凸塊形成係免去需要考量到如習知技術中可見的相鄰開口間之遮罩材料的孔帶間隔、SRT、以及最小可解析的SRO。
當該凸塊材料在沒有遮罩層下被回焊以將晶粒凸塊墊332冶金且電連接至基板凸塊墊464時，潤濕及表面張力係使得該凸塊材料維持自我局限且被保持在晶粒凸塊墊332與基板凸塊墊464及基板466中緊鄰導電線路460及462且實質在該凸塊墊的覆蓋區中的部份之間的空間內。
為了達成該所要的自我局限性質，凸塊材料可在置放於晶粒凸塊墊332或基板凸塊墊464上之前被浸沒在一助熔溶劑中，以選擇性地使得該凸塊材料所接觸的區域比導電線路460及462周圍的區域更濕潤。該熔化的凸塊材料係由於該助熔溶劑的可濕性而維持局限在實質由凸塊墊所界定的區域內。該凸塊材料並不溢出到較不濕潤的區域。一薄的氧化層或是其它絕緣層可形成在其中不打算有凸塊材料的區域之上，以使該區域較不濕潤。因此，晶粒凸塊墊332或基板凸塊墊464周圍並不需要有遮罩層468。
在圖22a中，遮罩層492係沉積在導電線路494及496的一部份之上。然而，遮罩層492並未形成在一體型凸塊墊498之上。因此，在基板500上的每個凸塊墊498都沒有SRO。一非濕性遮罩補片(patch)502係被形成在基板500上且在一體型凸塊墊498的陣列內的空隙中，亦即，在相鄰的凸塊墊之間。該遮罩補片502亦可形成在半導體晶粒324上且在晶粒凸塊墊498的陣列內的空隙中。更一般而言，該遮罩補片係被形成在任何配置中的一體型凸塊墊附近，以避免溢出到較不濕潤的區域。
半導體晶粒324係被設置在基板500之上，並且凸塊材料係和基板凸塊墊498對準。該凸塊材料係藉由如同圖13a-13g、14a-14d、15a-15d、16a-16c及17a-17b所述地壓下該凸塊材料或是藉由使該凸塊材料和該凸塊墊實體接觸並且接著在一回焊溫度下回焊該凸塊材料，以電氣且冶金連接至基板凸塊墊498。
在另一實施例中，一導電凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷的製程沉積在晶粒的一體型凸塊墊498之上。該凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其組合，其具有一選配的助熔溶劑。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一合適的附著或連結製程連結到一體型凸塊墊498。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來進行回焊，以形成球或凸塊504。在某些應用中，凸塊504係進行二次回焊以改善至一體型凸塊墊498的電氣接觸。該凸塊亦可壓縮連結到一體型凸塊墊498。凸塊504係代表一種可形成在一體型凸塊墊498之上的互連結構的類型。該互連結構亦可以使用柱形凸塊、微凸塊、或其它電互連。
在高繞線密度的應用中，最小化逸散間距是所期望的。為了減少在導電線路494及496間的間距，該凸塊材料係在一體型凸塊墊498周圍沒有遮罩層之下進行回焊。在導電線路494及496之間的逸散間距可藉由消除用於回焊限制目的之遮罩層以及該一體型凸塊墊周圍相關的SRO，亦即，藉由在沒有遮罩層下回焊凸塊材料而被減少。遮罩層492可形成在導電線路494及496以及基板500中遠離一體型凸塊墊498的一部份之上；然而，遮罩層492並未形成在一體型凸塊墊498的周圍。換言之，導電線路494及496中被設計以和凸塊材料配接的部份並沒有原本用於在回焊期間凸塊限制的遮罩層492的任何SRO。
此外，遮罩補片502係被形成在基板500上且在一體型凸塊墊498的陣列內的空隙中。遮罩補片502是非濕性材料。遮罩補片502可以是和遮罩層492相同的材料並且在相同的處理步驟期間施加、或為不同的材料而在不同的處理步驟期間施加。遮罩補片502可藉由對於一體型凸塊墊498的陣列內之線路或墊的部份選擇性的氧化、電鍍、或其它處理來加以形成。遮罩補片502係限制凸塊材料流到一體型凸塊墊498且避免導電凸塊材料滲到相鄰的結構。
當該凸塊材料係利用設置在一體型凸塊墊498的陣列內之空隙的遮罩補片502進行回焊時，潤濕及表面張力係使得該凸塊材料局限且保持在晶粒凸塊墊332與一體型凸塊墊498及基板500中緊鄰導電線路494及496且實質在該一體型凸塊墊498的覆蓋區中的部份之間的空間內。
為了達成所要的局限性質，該凸塊材料可在置放於晶粒凸塊墊332或一體型凸塊墊498上之前被浸沒在一助熔溶劑中，以選擇性地使得該凸塊材料所接觸的區域比導電線路494及496的周圍區域更濕潤。該熔化的凸塊材料係由於該助熔溶劑的可濕性而維持局限在實質由凸塊墊所界定的區域內。該凸塊材料並不溢出到較不濕潤的區域。一薄的氧化層或是其它絕緣層可形成在其中不打算有凸塊材料的區域之上，以使該區域較不濕潤。因此，晶粒凸塊墊332或一體型凸塊墊498的周圍並不需要遮罩層492。
由於晶粒凸塊墊332或一體型凸塊墊498的周圍沒有形成SRO，所以導電線路494及496可用較細的間距形成，亦即，導電線路可較靠近相鄰的結構來設置，而不會接觸且形成電氣短路。假設相同的焊料對準設計規則，導電線路494及496之間的間距係給定為P=(1.1D+W)/2，其中D是凸塊504的基底直徑，並且W是導電線路494及496的寬度。在一實施例中，給定100μm的凸塊直徑以及20μm的線路線寬，導電線路494及496之最小的逸散間距是65μm。該凸塊形成係免去需要考量到如習知技術中可見的相鄰開口間之遮罩材料的孔帶間隔、以及最小可解析的SRO。
圖23係展示堆疊封裝(PoP)505，其中半導體晶粒506係利用晶粒附接黏著劑510而堆疊在半導體晶粒508上。半導體晶粒506及508分別具有一包含類比或數位電路的主動表面，該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能來電互連的主動裝置、被動裝置、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在該主動表面內之電路元件以實施類比電路或數位電路，例如：DSP、ASIC、記憶體或其它信號處理電路。半導體晶粒506及508亦可包含例如是電感器、電容器及電阻器的IPD，以供RF信號處理使用。
半導體晶粒506係利用圖13a-13g、14a-14d、15a-15d、16a-16c及17a-17b的實施例中之任一實施例，利用形成在接觸墊518上之凸塊材料516而被安裝到形成在基板514上的導電線路512。接觸墊518及導電線路512可對應於圖5-11的晶粒墊佈局中的信號墊、電源墊或接地墊。半導體晶粒508係利用焊線522電連接至形成在基板514上之接觸墊520。焊線522之相反端係連結到半導體晶粒506上之接觸墊524。
遮罩層526係被形成在基板514之上且開口超過半導體晶粒506的覆蓋區。儘管遮罩層526在回焊期間並不限制凸塊材料516到導電線路512，該開放的遮罩可運作為一屏障以避免在MUF期間封裝材料528遷移到接觸墊520或焊線522。封裝材料528係類似於圖18a-18c沉積在半導體晶粒508及基板514之間。遮罩層526係阻擋MUF封裝材料528到達接觸墊520及焊線522，否則可能會造成缺陷。遮罩層526係容許較大的半導體晶粒被設置在一特定的基板上，而無封裝材料528流出到接觸墊520之上的風險。
儘管本發明的一或多個實施例已詳細地解說，熟習此項技術者將會體認到可在不脫離如以下的申請專利範圍中所闡述之本發明的範疇下，對於該些實施例進行修改及調適。
10．．．晶粒墊佈局
12．．．主動表面
13．．．半導體晶粒
14．．．電源墊
16．．．接地墊
18．．．信號墊
19．．．信號墊
20．．．基板墊的配置
22．．．基板表面
23．．．在晶粒邊緣的下方
24．．．電源墊
26．．．接地墊
28．．．信號墊
29．．．信號墊
30．．．線路
32．．．短的線路
34．．．信號貫孔
36．．．短的線路
38．．．電源貫孔
40．．．短的線路
42．．．接地貫孔
50．．．電子裝置
52．．．印刷電路板
54．．．線路
56．．．打線接合封裝
58．．．覆晶
60．．．球狀柵格陣列
62．．．凸塊晶片載體
64．．．雙排型封裝
66．．．平台柵格陣列
68．．．多晶片模組
70．．．四邊扁平無引腳封裝
72．．．四邊扁平封裝
74．．．半導體晶粒
76．．．接觸墊
78．．．中間載體
80．．．導線
82．．．焊線
84．．．封裝材料
88．．．半導體晶粒
90．．．載體
92．．．底膠填充或環氧樹脂黏著材料
94．．．焊線
96．．．接觸墊
98．．．接觸墊
100．．．模製化合物或封裝材料
102．．．接觸墊
104．．．凸塊
106．．．中間載體
108．．．主動區域
110．．．凸塊
112．．．凸塊
114．．．信號線
116．．．模製化合物或封裝材料
120．．．晶粒墊佈局
122．．．信號墊
124．．．晶粒表面
126．．．晶粒邊緣
128．．．電源墊
130．．．接地墊
132．．．中央區域
134．．．基板墊的配置
136．．．信號墊
138．．．電源墊
140．．．接地墊
142．．．基板表面
144．．．在晶粒邊緣的下方
146．．．線路
148．．．短的線路
150．．．電源貫孔
152．．．短的線路
154．．．接地貫孔
155．．．主動側
156．．．覆晶封裝
157．．．半導體晶粒
158．．．基板
160．．．電源墊
161．．．接地墊
162．．．上方的金屬層
163．．．信號凸塊
164．．．信號線路
165．．．電源凸塊
166．．．電源線路
167．．．接地凸塊
168．．．接地線路
170．．．單一金屬層基板
171．．．單一金屬層基板
172．．．兩金屬層基板
173．．．上方的金屬層
174．．．下方的金屬層
176．．．經圖案化的金屬層
177．．．線路
178．．．線路
179．．．電源線路
180．．．接地線路
181．．．接地凸塊
182．．．信號凸塊
183．．．電源凸塊
184．．．接地凸塊位置
185．．．信號凸塊位置
186．．．電源凸塊位置
187．．．核心接地凸塊
188．．．核心電源凸塊
189．．．核心接地凸塊位置
190．．．核心電源凸塊位置
191．．．貫孔
192．．．貫孔
193．．．貫孔
194．．．線路
195．．．在晶粒邊緣的下方
196．．．貫孔
197．．．貫孔
198．．．貫孔
200．．．晶粒墊佈局
202．．．信號墊
204．．．晶粒表面
206．．．晶粒邊緣
208．．．電源墊
210．．．接地墊
212．．．基板墊的配置
214．．．信號墊
216．．．電源墊
218．．．接地墊
220．．．晶粒墊佈局
222．．．在晶粒邊緣的下方
224．．．線路
226．．．電源短線段或凸出
228．．．電源貫孔
230．．．接地短線段或凸出
232．．．接地貫孔
234．．．晶粒墊佈局
236．．．信號墊
238．．．晶粒表面
240．．．晶粒邊緣
242．．．電源墊
244．．．接地墊
250．．．基板墊的配置
252．．．信號墊
254．．．電源墊
256．．．接地墊
258．．．基板表面
260．．．在晶粒邊緣的下方
262．．．線路
264．．．電源短線段或凸出
266．．．電源貫孔
268．．．接地短線段或凸出
269．．．接地貫孔
270．．．晶粒墊佈局
271．．．信號墊
272．．．晶粒表面
273．．．晶粒邊緣
274．．．電源墊
275．．．接地墊
276．．．基板墊的配置
278．．．信號墊
279．．．電源墊
280．．．接地墊
281．．．基板表面
282．．．在晶粒邊緣的下方
283．．．線路
284．．．電源短線段或凸出
285．．．電源貫孔
286．．．接地短線段或凸出
287．．．接地貫孔
288．．．晶粒墊佈局
289．．．信號墊
290．．．晶粒表面
291．．．晶粒邊緣
292．．．電源墊
293．．．接地墊
294．．．基板墊的配置
295．．．信號墊
296．．．電源墊
297．．．接地墊
298．．．基板表面
300．．．在晶粒邊緣的下方
302．．．線路
304．．．電源短線段或凸出
306．．．電源貫孔
310．．．接地短線段或凸出
312．．．接地貫孔
320．．．半導體晶圓
322．．．主體基板材料
324．．．半導體晶粒或構件
326．．．切割道
328．．．背表面
330．．．主動表面
332．．．導電層
334．．．凸塊材料
336．．．球或凸塊
338．．．複合的凸塊
340．．．不可熔的部份
342．．．可熔的部份
344．．．凸塊
346．．．導電柱
348．．．凸塊材料
350．．．突點
352．．．鋸條或雷射切割工具
354．．．基板
356．．．導電線路
358．．．基板或PCB
360．．．導電線路
361．．．凸塊材料
362．．．複合的凸塊
364．．．不可熔或不可分解的部份
366．．．可熔或可分解的部份
368．．．導電線路
370．．．基板
374．．．凸塊材料
376．．．導電線路
378．．．基板
380．．．突點
384．．．凸塊材料
386．．．尖端
388．．．導電線路
390．．．基板
394．．．凸塊材料
396．．．尖端
398．．．導電線路
400．．．基板
404．．．凸塊材料
406．．．導電線路
408．．．基板
410．．．導電貫孔
412．．．開口
414．．．導電的側壁
416．．．上方模具支撐件
418．．．下方模具支撐件
420．．．凹槽模具
422．．．可壓縮的離型膜
424．．．封裝材料
426．．．噴嘴
428．．．輔助
430．．．屏障
432．．．封裝材料
434．．．噴嘴
440．．．基板
442．．．導電線路
444．．．基板凸塊墊
446．．．遮罩層
448．．．凸塊或互連
450．．．基板
452．．．導電線路
454．．．基板凸塊墊
456．．．遮罩層
460．．．導電線路
462．．．導電線路
464．．．基板凸塊墊
466．．．基板
468．．．遮罩層
470．．．導電線路
472．．．導電線路
474．．．基板凸塊墊
476．．．基板
478．．．遮罩層
480．．．導電線路
482．．．導電線路
484．．．基板凸塊墊
486．．．基板
488．．．遮罩層
490．．．凸塊或互連
492．．．遮罩層
494．．．導電線路
496．．．導電線路
498．．．凸塊墊
500．．．基板
502．．．遮罩補片
504．．．球或凸塊
505．．．堆疊封裝
506．．．半導體晶粒
508．．．半導體晶粒
510．．．晶粒附接黏著劑
512．．．導電線路
514．．．基板
516．．．凸塊材料
518．．．接觸墊
520．．．接觸墊
522．．．焊線
524．．．接觸墊
526．．．遮罩層
528．．．封裝材料
圖1係以平面圖描繪在一晶粒上用於一覆晶封裝之一習知的墊佈局；
圖2係以平面圖描繪在一覆晶基板上的墊及繞線的配置；
圖3係描繪一安裝到其表面之不同類型的封裝的PCB；
圖4a-4c係描繪安裝到該PCB的半導體封裝之進一步細節；
圖5係描繪在一晶粒上用於一覆晶封裝之一墊佈局；
圖6係描繪在一覆晶基板上的墊及繞線之一配置；
圖7係描繪安裝在一基板上的一覆晶之一部份，其係具有一晶粒墊佈局以及基板墊配置；
圖8a-8b係描繪在一晶粒上用於一覆晶封裝之一第一墊佈局；
圖9a-9b係描繪在一晶粒上用於一覆晶封裝之一第二墊佈局；
圖10a-10b係描繪在一晶粒上用於一覆晶封裝之一第三墊佈局；
圖11a-11b係描繪在一晶粒上用於一覆晶封裝之一第四墊佈局；
圖12a-12h係描繪形成在一半導體晶粒之上用於連結至一基板上的導電線路之各種的互連結構；
圖13a-13g係描繪該半導體晶粒以及連結到該些導電線路的互連結構；
圖14a-14d係描繪具有一連結到該些導電線路之楔形的互連結構的半導體晶粒；
圖15a-15d係描繪該半導體晶粒以及連結到該些導電線路的互連結構的另一實施例；
圖16a-16c係描繪連結到該些導電線路的階梯形凸塊以及柱形凸塊互連結構；
圖17a-17b係描繪具有導電貫孔的導電線路；
圖18a-18c係描繪在該半導體晶粒及基板之間的模具底膠填充；
圖19係描繪在該半導體晶粒及基板之間的另一模具底膠填充；
圖20係描繪在模具底膠填充後之半導體晶粒及基板；
圖21a-21g係描繪具有開放的焊料對準的導電線路之各種配置；
圖22a-22b係描繪具有在導電線路間的補片之開放的焊料對準；並且
圖23係描繪具有遮罩層屏障以在模具底膠填充期間抑制封裝材料之POP。
120．．．晶粒墊佈局
122．．．信號墊
124．．．晶粒表面
126．．．晶粒邊緣
128．．．電源墊
130．．．接地墊
132．．．中央區域

Claims (18)

  1. 一種製造半導體裝置之方法，其包括：提供具有晶粒墊佈局的半導體晶粒，其中信號墊位在該半導體晶粒的周邊區域中的不超過兩個的周邊列中，並且電源墊及接地墊主要位在該半導體晶粒的該信號墊的內側的區域中；在該半導體晶粒的該信號墊、該電源墊以及該接地墊之上形成複數個凸塊；提供基板；在該基板之上形成具有互連位置的複數個導電線路，該互連位置係配置於沿著該導電線路的長度的中間位置處，其中該導電線路自該互連位置以相反方向延伸，並且在該半導體晶粒的該信號墊、該電源墊及該接地墊上方的該凸塊係比該導電線路的該互連位置寬；藉由將在該半導體晶粒的該信號墊、該電源墊及該接地墊上方的該凸塊連結至該基板上方的該互連位置而將該半導體晶粒設置於該基板，使得該凸塊覆蓋該互連位置的頂表面及側表面；以及在與該凸塊相對的該半導體晶粒的表面之上和該半導體晶粒及基板之間的該凸塊的周圍沉積封裝材料。
  2. 如申請專利範圍第1項之方法，其中該凸塊係包含可熔的部份以及不可熔的部份。
  3. 如申請專利範圍第1項之方法，其進一步包含以大致平行於該半導體晶粒的邊緣配置該信號墊。
  4. 如申請專利範圍第1項之方法，其中少於10%的該電源墊及該接地墊係位在該周邊區域之內，並且少於10%的該信號墊係位在該內側的區域之內。
  5. 如申請專利範圍第1項之方法，其進一步包含在該基板遠離該互連位置的區域之上形成遮罩層。
  6. 如申請專利範圍第1項之方法，其進一步包含在該基板之上在該互連位置之間空隙地形成複數個遮罩補片而將該互連位置物理地分離。
  7. 如申請專利範圍第1項之方法，其中沿著該互連位置的該凸塊的長度是比橫跨該互連位置的該凸塊的寬度還大，其中該凸塊的寬度垂直於該凸塊的長度。
  8. 如申請專利範圍第7項之方法，其中該凸塊的寬度係沿著該凸塊的長度漸縮以在該半導體晶粒附近為較寬且在與該半導體晶粒相對的該凸塊的端部附近為較窄。
  9. 一種製造半導體裝置之方法，其包括：提供半導體晶粒；提供基板；形成具有互連位置的複數個導電線路，其中該互連位置在該導電線路上且沉積在該基板之上，其係以信號墊主要位在該基板的周邊區域中並且電源位置及接地位置主要位在該基板的該信號墊之內側的區域中之佈局來配置；藉由比在該導電線路上的該互連位置還寬的凸塊將該半導體晶粒連結至該互連位置；以及在與該凸塊相對的該半導體晶粒的表面之上和該半導 體晶粒及該基板之間沉積封裝材料。
  10. 如申請專利範圍第9項之方法，其中少於10%的該電源位置及該接地位置係位在該周邊區域之內。
  11. 如申請專利範圍第9項之方法，其中少於10%的該信號墊係位在該內側的區域之內。
  12. 如申請專利範圍第9項之方法，其進一步包含以大致平行於該基板的邊緣的周邊列或是周邊陣列來配置該信號墊。
  13. 如申請專利範圍第9項之方法，其進一步包含以陣列配置該電源位置及該接地位置在靠近該基板的中心處。
  14. 一種半導體裝置，其包括：具有晶粒墊佈局的半導體晶粒，其中信號墊主要位在該半導體晶粒的周邊區域中，並且電源墊及接地墊主要位在該半導體晶粒的該信號墊的內側的區域中；基板；形成在該基板之上的具有互連位置的複數個導電線路；複數個凸塊，其連結到該半導體晶粒以及複數個該互連位置的頂表面及側表面；以及沉積在與該凸塊相對的該半導體晶粒的表面之上和該半導體晶粒及該基板之間的封裝材料。
  15. 如申請專利範圍第14項之半導體裝置，其中該凸塊包含可熔的部份以及不可熔的部份。
  16. 如申請專利範圍第14項之半導體裝置，其中少於 10%的該電源墊及該接地墊係位在該周邊區域之內。
  17. 如申請專利範圍第14項之半導體裝置，其中少於10%的該信號墊係位在該內側的區域之內。
  18. 如申請專利範圍第14項之半導體裝置，其中該信號墊係以交錯的配置或是正交的配置來加以配置在相鄰的列中。
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US8853001B2 (en) 2014-10-07
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US20150054167A1 (en) 2015-02-26
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