TWI508200B - 半導體元件以及在無焊料遮罩的回焊期間的導電凸塊材料的自我封閉之方法 - Google Patents

半導體元件以及在無焊料遮罩的回焊期間的導電凸塊材料的自我封閉之方法 Download PDF

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Publication number
TWI508200B
TWI508200B TW099114339A TW99114339A TWI508200B TW I508200 B TWI508200 B TW I508200B TW 099114339 A TW099114339 A TW 099114339A TW 99114339 A TW99114339 A TW 99114339A TW I508200 B TWI508200 B TW I508200B
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Taiwan
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bump
substrate
semiconductor
pad
conductive
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TW099114339A
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English (en)
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TW201104769A (en
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Rajendra D Pendse
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Stats Chippac Ltd
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Publication of TW201104769A publication Critical patent/TW201104769A/zh
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description

半導體元件以及在無焊料遮罩的回焊期間的導電凸塊材料的自我封閉之方法
本發明大體上關於半導體元件，且更特別地，關於一種半導體元件以及不使用焊料遮罩而於回焊期間提供導電凸塊材料的自我封閉之方法。
半導體元件常見於現代電子產品中。半導體元件在電性構件之數量及密度上有所變化。分立式半導體元件大體上包含某類型電性構件，例如，發光二極體(LED)、小訊號電晶體、電阻器、電容器、電感器及功率式金氧半導體場效電晶體(MOSFET)。整合式半導體元件典型地包含成千上萬個電性構件。整合式半導體元件範例包含微控制器、微處理機、電荷耦合元件(CCD)、太陽能蓄電池及數位微型反射鏡元件(DMD)。
半導體元件執行廣泛功能，例如，高速計算、傳輸並接收電磁波訊號、控制電子元件、轉換光線成為電力及產生電視顯示器之視覺投影。半導體元件見於娛樂、通訊、電力轉換、網路、電腦及消費產品領域中。半導體元件也見於軍事應用、航空、汽車、工業控制及辦公設備中。
半導體元件利用半導體材料之電特性。半導體材料之原子結構讓它的導電性可受到施加電場或透過摻雜製程來操控。摻雜技術將雜質引入該半導體材料內以操控該半導體元件之導電性。
一半導體元件包含主動及被動電性結構。包含二極體及場效電晶體之主動結構控制電流流動。藉由改變摻雜位準及施加電場或基極電流，該電晶體不是增加就是限制該電流流動。包含電阻器、電容器及電感器之被動結構在執行各種電性功能所需電壓與電流間產生某種關係。該些被動及主動結構被電性連接以執行高速計算和其它有用功能。
半導體元件大體上為使用二複合製程，也就是前端製程和後端製程來製造之，每一個製程可能涉及數百個步驟。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。每一個晶粒典型地一模一樣且內含電性連接之主動及被動構件所形成之電路。後端製程涉及單粒化來自該已完成晶圓之個別晶粒並構裝該晶粒以提供結構支撐及環境隔離。
半導體製程之一目標為製造較小的半導體元件。較小的元件典型地消耗較少電力、具有較高執行效率且可更有效率地被製造。此外，較小的半導體元件具有一較小佔用空間，其可期待提供較小的終端產品。一較小晶粒尺寸可經由改善該前端製程以產生內含較小、較高密度主動和被動構件之晶粒而得。後端製程可經由改善電性連接和構裝材料而產生具有一較小佔用空間之半導體元件構裝。
圖1說明使用焊料遮罩15之具有冶金及電性地連接於凸塊墊片14及軌跡線20間之內連線12之覆晶型半導體元件10中其中一部分。如圖2所示，一環狀焊料遮罩或對位開口(SRO)16形成覆蓋於基板18上以露出軌跡線20。軌跡線20具有選擇性凸塊墊片以配接內連線12之直導體。對位開口16在回焊期間限制軌跡線20之凸塊墊片上之導電凸塊材料並阻止該熔化凸塊材料滲透至該些軌跡線上，其會引起相鄰結構間之電性短路。對位開口16被製造的較該軌跡線或凸塊墊片大。對位開口16形狀典型地為環狀且儘可能地製造的小些以減少軌跡線20之間距並增加路徑密度。
在典型設計規則中，軌跡線20之最小外洩間距受到對位開口16必須至少和內連線12之基座部直徑(D)加上一焊料遮罩對位容限(SRT)一樣大所限。此外，由於該焊料遮罩應用製程限制，故在相鄰開口間需要一最小細線(L)之焊料遮罩材料。更特別地，該最小外洩間距定義為P=D+2*SRT+L。在一實施例中，D為100微米(μm)，SRT為10微米，且L為60微米，因此，該最小外洩間距為100+2*10+60=180微米。
圖3a和圖3b顯示具有基板40上之軌跡線32和34與凸塊36和38間所排定之軌跡線30之另一傳統安排之俯視圖及剖面圖。凸塊36和38電性連接半導體晶粒42至基板40。焊料遮罩44覆蓋在凸塊墊片46和48上方。軌跡線30之最小外洩間距定義為P=D/2+SRT+L+W/2，其中，D為凸塊基座部直徑，SRT為焊料遮罩對位容線，W為軌跡線寬度，且L為對位開口及相鄰結構間之細線間隔。在一實施例中，D為100微米，SRT為10微米，W為30微米，且L為60微米。軌跡線30-34之最小外洩間距為100/2+10+60+30/2=135微米。在高路徑密度要求增加時，一較小外洩間距是需要的。
現存有為了提供較高路徑密度而極小化軌跡線之外洩間距之需求。因此，在一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一具有一晶粒凸塊墊片之半導體晶粒、提供一具有一內含基板凸塊墊片之軌跡線之基板、沉積導電凸塊材料在該基板凸塊墊片或晶粒凸塊墊片上、將該半導體晶粒安裝在該基板上而使得該導電凸塊材料沉積於該晶粒凸塊墊片和基板凸塊墊片之間及在無一焊料遮罩環繞著該晶粒凸塊墊片或基板凸塊墊片下回焊該導電凸塊材料以形成一內連線。該導電凸塊材料於回焊期間自我封閉在該晶粒凸塊墊片或基板凸塊墊片之佔用空間內。
在另一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為提供一具有一第一凸塊墊片之第一半導體結構、提供一具有一第二凸塊墊片之第二半導體結構、沉積導電凸塊材料於該第一及第二凸塊墊片之間及在無一焊料遮罩環繞著該第一凸塊墊片及第二凸塊墊片下回焊該導電凸塊材料以形成一內連線。該導電凸塊材料於回焊期間自我封閉在該第一及第二凸塊墊片內。
在另一實施例中，本發明為一種半導體元件之製造方法，包括之步驟為將導電凸塊材料沉積於一第一凸塊墊片上、及在無一焊料遮罩下回焊該導電凸塊材料。該導電凸塊材料於回焊期間自我封閉在該第一凸塊墊片內。
在另一實施例中，本發明為一種半導體元件，包括一具有一第一凸塊墊片之半導體晶粒及具有一第二凸塊墊片之基板。一內連線在無一焊料遮罩下經由回焊導電凸塊材料而形成於該第一及第二凸塊墊片之間。該導電凸塊材料自我封閉於該第一及第二凸塊墊片內。
本發明參考圖形描述於下列說明之一或更多實施例中，其中類似編號代表相同或類似構件。雖然本發明以最佳模式來描述以達成本發明目的，然而那些熟知此項技術之人士應理解到本發明要涵蓋下列揭示及圖式所支持附上之申請專利範圍及它們等效例所定義之本發明精神及範圍所包含之替代例、修改例和等效例。
半導體元件大體上為使用二複合製程：前端製程和後端製程來製造之。前端製程涉及在一半導體晶圓表面上形成複數個晶粒。在該晶圓上之每一個晶粒內含主動及被動電性構件，其為電性連接以形成功能性電性電路。例如電晶體及二極體之主動電性構件具有控制電流流動之能力。例如電容器、電感器、電阻器和變壓器之被動電性構件產生用以執行電性電路功能所需之電壓和電流間的關係。
被動及主動構件為經由包含摻雜、沉積、微影成像、蝕刻及平坦化之一系列製程而形成於該半導體晶圓表面上。摻雜技術經由例如離子植入或熱擴散類之技術將雜質引入該半導體材料中。該摻雜製程改變主動元件內部半導體材料之導電性，以轉換該半導體材料成為一絕緣體、導體，或動態地改變該半導體材料導電性以回應一電場或基極電流。電晶體內含依需求安排之各種摻雜類型與程度之區域以使該電晶體可依據該電場或基極電流來增進或限制電流流動。
主動及被動構件為由具有不同電特性之材料層所形成。該些材料層可由欲沉積之材料類型所部分決定之各類沉積技術來形成之。例如，薄膜沉積技術可包含化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍及無電鍍各製程。每一層大體上被圖案化以形成主動構件、被動構件或構件間之電性連接部分。
該些材料層可使用微影成像技術來圖案化之，其包含將例如光阻劑之感光性材料沉積於欲圖案化之材料層上。使用光將一圖案自一光罩轉印至該光阻劑。該光阻劑圖案中遇到光的部分使用一溶劑來移除之，以露出下層中欲圖案化的部分。該光阻劑其餘部分被移除，留下一圖案化層。替代性地，一些材料類型經由直接沉積材料於使用例如無電鍍及電鍍類技術之先前沉積/蝕刻製程所形成之區域或孔隙中而進行圖案化。
將一薄膜材料沉積於一現成圖案上可擴大該下層圖案並產生一不均勻平坦表面。一均勻平坦表面被需要以產生較小且更密集封裝之主動及被動構件。平坦化技術可被使用以移除該晶圓表面之材料並產生一均勻平坦表面。平坦化技術涉及以一拋光墊片來拋光該晶圓表面。一研磨材料及腐蝕性化學藥品於拋光期間被添加至該晶圓表面。結合研磨之機械性動作及化學藥品之腐蝕性動作可移除任何不規則拓樸，產生一均勻平坦表面。
後端製程指切割或單粒化該已完成晶圓成為該個別晶粒並接著構裝該晶粒以提供結構支撐及環境隔離。為了單粒化該晶粒，將該晶圓沿著所謂割鋸道或劃線之晶圓無功能區域做記號並切開。使用一雷射切割工具或鋸片切割該晶圓成晶粒。單粒化後，個別晶粒被安裝至包含接腳或接觸墊片以與其它系統構件互相連接之構裝基板上。該半導體晶粒上所形成之接觸墊片接著被連接至該構裝內之接觸墊片。該電性連接可搭配錫球凸塊、短柱凸塊、導電膏或接線來進行之。一封膠劑或其它封膠材料被沉積於該構裝上以提供物理性支撐及電性隔離。該已完成構裝接著被插入一電性系統中，且該半導體元件功能對於其它系統構件是有用的。
圖4說明具有在表面上安裝有複數個半導體構裝之晶片載體基板或印刷電路板52之電子元件50。電子元件50可具有某半導體構裝類型或多種半導體構裝類型，視應用而定。基於說明目的，不同半導體構裝類型示於圖4中。
電子元件50可為使用該些半導體構裝來執行一或更多電性功能之獨立系統。替代性地，電子元件50可為一較大型系統之子構件。例如，電子元件50可為能夠插入一電腦內之繪圖卡、網路界面卡或其它訊號處理卡。該半導體構裝可包含微處理器、記憶體、特殊用途積體電路(ASIC)、邏輯電路、類比電路、射頻電路、離散元件或其它半導體晶粒或電性構件。
在圖4中，為了安裝在該印刷電路板上之半導體構裝之結構支撐及電性內連線，印刷電路板52提供一總基板。傳導訊號軌跡線54使用蒸鍍製程、電鍍製程、無電鍍製程、網印製程或其它合適金屬沉積製程來形成於印刷電路板52之某一表面上或多層內。訊號軌跡線54提供該些半導體構裝、安裝構件及其它外部系統構件中每一個間之電性通訊。軌跡線54也提供至該些半導體構裝中每一個之電力及接地連接。
在一些實施例中，一半導體元件具有二構裝級。第一級構裝用以機械性和電性地黏結該半導體晶粒至一中介載體之技術。第二級構裝涉及機械性和電性地黏結該中介載體至該印刷電路板。在其它實施例中，一半導體元件可以只具有該第一級構裝，其中，該晶粒經由機械性和電性方式直接安裝至該印刷電路板。
基於說明目的，包含打線接合構裝56及覆晶構裝58之一些第一級構裝類型被示於印刷電路板52上。此外，包含錫球陣列(BGA)構裝60、凸塊晶片載體(BCC)62、雙列式構裝(DIP)、平面陣列(LGA)構裝66、多晶片模組(MCM)構裝68、四邊扁平無引腳構裝(QFN)70及四邊扁平構裝72之一些第二級構裝類型顯示安裝於印刷電路板52上。依據該些系統需求，搭配第一及第二級構裝型式之任意結合以及其它電子構件所建構之半導體構裝之任意結合可被連接至印刷電路板52。在一些實施例中，電子元件50包含一單黏結半導體構裝，而其它實施例需要多個連接構裝。經由結合單一基板上之一或更多半導體構裝，製造商可整合預製構件至電子元件及系統中。因為該些半導體構裝包含複雜功能，故可使用較便宜構件及一現代化製程來製造電子元件。所產元件較不可能失敗，且對於消費者而言製造成本較低而使所產元件較便宜。
圖5a-5d顯示示範性半導體構裝。圖5a說明安裝在印刷電路板52上之雙列式構裝64之進一步細部。半導體晶粒74包含一內含類比或數位電路之作用區域，該些電路被配置為形成於該晶粒內並根據該晶粒之電性設計進行電性互連之主動元件、被動元件、導電層和介電層。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器和形成於該半導體晶粒74之作用區域內之其它電路構件。接觸墊片76為例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)中之一或更多導電材料層，且被電性連接至形成於半導體晶粒74內之電路構件。在組合雙列式構裝64期間，半導體晶粒74為使用一金矽合金層或例如熱環氧樹脂類之黏接材料來安裝至一中介載體78。該構裝主體包含例如聚合物或陶瓷類之絕緣構裝材料。導線80及接線82提供半導體晶粒74及印刷電路板52間之電性內連線。封膠劑84被沉積於該構裝上以阻止濕氣和微粒進入該構裝並污染晶粒74或接線82而提供環境保護。
圖5b說明安裝於印刷電路板52上之凸塊晶片載體62之進一步細部。半導體晶粒88為使用一底部填膠或環氧樹脂黏接材料92來安裝於載體90上。接線94提供接觸墊片96及98間之第一級封裝內連線。封膠化合物或封膠劑100被沉積於半導體晶粒88及接線94上以提供該元件物理性支撐和電性隔離。接觸墊片102為使用例如電鍍或無電鍍之合適金屬沉積製程來形成於印刷電路板52之表面上而阻止氧化作用。接觸墊片102被電性連接至印刷電路板52之傳導訊號軌跡線54。凸塊104形成於凸塊晶片載體62之接觸墊片98及印刷電路板52之接觸墊片102之間。
覆晶半導體構裝及晶圓級構裝(WLP)為共用搭配要求高速、高密度和較多接腳數之積體電路(IC)來使用之。在圖5c中，半導體晶粒58為面朝下安裝至具有一覆晶式第一級構裝之中介載體106。半導體晶粒58之作用區域108包含根據該晶粒電性設計所形成做為主動元件、被動元件、導電層和介電層而配置之類比或數位電路。例如，該電路可包含一或更多電晶體、二極體、電感器、電容器、電阻器及作用區域108內之其它電路構件。半導體晶粒58為透過內連線110以電性及機械性地連接至載體106。
錫球陣列構裝60為使用內連線112來電性及機械性地連接至具有一錫球陣列式第二級構裝之印刷電路板52。半導體晶粒58為透過內連線110、訊號線114和內連線112來電性連接至印刷電路板52之傳導訊號軌跡線54。一封膠化合物或封膠劑116被沉積於半導體晶粒58及載體106上以提供該元件物理性支撐和電性隔離。該覆晶半導體元件提供自半導體晶粒58上之主動元件至印刷電路板52上之傳導軌跡線一短的導電路徑，用以減少訊號傳送距離、降低電容並改進整體電路執行效率。
在另一實施例中，如圖5d所示，半導體晶粒58之作用區域108為面朝下地直接安裝至印刷電路板115，也就是說沒使用一中介載體。凸塊墊片111為使用一蒸鍍製程、電鍍製程、無電鍍製程、網印製程或其它合適金屬沉積製程來形成於作用區域108上。凸塊墊片111經由作用區域108中之傳導軌跡線來連接至該些主動及被動電路。凸塊墊片116可為鋁、錫、鎳、金、銀或銅。一導電凸塊材料為使用一蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於凸塊墊片111上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑材料。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至晶粒凸塊墊片160。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成圓球或凸塊117。在一些應用中，凸塊117被回焊一第一時間以改進對凸塊墊片111之電性接觸。該覆晶半導體元件提供自半導體晶粒58上之主動元件至印刷電路板115上之傳導軌道118之一短導電路徑，用以減少訊號傳送、降低電容並取得整體較佳電路執行效率。
圖6a和圖6b說明具有晶粒凸塊墊片122之覆晶型半導體晶粒120中其中一部分之俯視圖和剖面圖。軌跡線124具有形成於基板或印刷電路板130上之整合凸塊墊片126之直立導體。圖7a和圖7b顯示沿著軌跡線124之基板凸塊墊片126之進一步細部。該基板凸塊墊墊片126可如圖7a所示地成為圓形或如圖7b所示地成為矩形。該些基板凸塊墊片126各邊可與軌跡線124共平面。
一導電凸塊材料為使用一蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於晶粒凸塊墊片122或基板凸塊墊片126上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑溶液。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至晶粒凸塊墊片122及基板凸塊墊片126。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成內連線132。在一些應用中，內連線132被回焊一第二時間以改進晶粒凸塊墊片122及基板凸塊墊片126間之電性接觸。環繞該窄基板凸塊墊片126之凸塊材料維持回焊期間之晶粒定位。雖然所示內連線132為連接至軌跡線124成為一引腳上凸塊(BOL)，但是該內連線也可被形成於基板130上具有與晶粒凸塊墊片122等階層或更大之區域之凸塊墊片上。一選擇性底部填膠材料138被沉積於半導體晶粒120及基板130之間。
在高路徑密度應用中，極小化軌跡線124之外洩間距為可期待的。軌跡線124間之外洩間距可經由省去產生回焊污染之焊料遮罩，亦即回焊該凸塊材料而不用一焊料遮罩而被降低。焊料遮罩140可被形成於部分基板130上。然而，焊料遮罩140未被形成於產生回焊污染之軌跡線124之基板凸塊墊片126上。也就是，設計來與該凸塊材料搭配之部分軌跡線124為沒有任何焊料遮罩140之對位開口。既然沒有對位開口環繞晶粒凸塊墊片122或基板凸塊墊片126而形成，軌跡線124可以一較細間距來形成之，亦即軌跡線124可較緊密地沉積在一起或較靠近附近結構處進行沉積。沒有焊料遮罩140，給予之軌跡線124間之間距為P=D+PLT+W/2，其中，D為內連線132之基座部直徑，PLT為晶粒定位容限，且W為該軌跡線124之寬度。在一實施例中，給予100微米之凸塊基座部直徑及30微米之軌跡線寬度，則軌跡線124之最小外洩間距為125微米。該無焊料遮罩形成省去習知技術所見之對相鄰開口、焊料遮罩對位容限及最小可溶解對位開口間之焊料遮罩材料之細線間隔之需求。
當不用一焊料遮罩而回焊該凸塊材料以冶金及電性地連接晶粒凸塊墊片122至基板凸塊墊片126時，濕潤及表面張力使該凸塊材料維持自我封閉並保留於晶粒凸塊墊片122、基板凸塊墊片126及實際上在該些凸塊墊片佔用空間內緊鄰著軌跡線124的部分基板130之間的間隔內。
為了達到想要的自我封閉特性，該凸塊材料可在定位於晶粒凸塊墊片122或基板凸塊墊片126上之前先被浸入一助焊劑溶液中以選擇性地使該凸塊材料接觸之區域較軌跡線124環繞區域更濕潤。由於該助焊劑溶液之可濕潤特性，該熔化凸塊材料實際上仍被封閉於該些凸塊墊片所定義之區域內。該凸塊材料不會溢出至較不濕潤的區域。一薄氧化層或其它絕緣層可被形成於不欲因凸塊材料而造成該區域較不濕潤之所在區域上。因此，不需焊料遮罩140環繞著晶粒凸塊墊片122或基板凸塊墊片126。
在另一實施例中，一複合內連線144形成於晶粒凸塊墊片122及基板凸塊墊片126間以得到想要之凸塊材料自我封閉。如圖8所示，複合內連線144包含由銅、金、錫、鎳或鉛所製造之不可熔化基座部146和由焊錫、錫或銦所製造之可熔化帽蓋部148。與不可熔化基座部材料有關之可熔化凸塊材料量被選擇以確保由於表面張力所產生之自我封閉。在回焊期間，該可熔化基座部材料環繞著該不可熔化基座部材料而自我封閉。環繞著該不可熔化基座部之可熔化凸塊材料同時於回焊期間維持著晶粒定位。大體上，複合內連線144之高度為相同或小於該凸塊之直徑。在一些例子中，複合內連線144之高度為大於該內連線之直徑。在一實施例中，給予100微米之凸塊基座部直徑，該不可熔化基座部146之高度約為45微米且該可熔化帽蓋部148之高度約為35微米。實際上在該些凸塊墊片所定義之區域內之熔化凸塊材料維持著封閉，此因用以形成包含不可熔化基座部146和可熔化帽蓋部148之複合凸塊144所沉積之凸塊材料量被選擇以使所產生之表面張力足以使該凸塊材料實際上保留在該些凸塊墊片之佔用空間內並阻止溢出至計劃外之相鄰或附近區域之故。因此，不需焊料遮罩140環繞著晶粒凸塊墊片122或基板凸塊墊片126以降低軌跡線間距並增加路徑密度。
圖9a和圖9b說明具有晶粒凸塊墊片152之覆晶型半導體晶粒150之另一實施例之俯視圖和剖面圖。軌跡線154為類似於圖7a和圖7b之具有形成於基板或印刷電路板160上之整合凸塊墊片156之直立導體。在本實施例中，凸塊墊片156被安排成多排或交錯排。因此，替代性軌跡線154包含用以安排路線至凸塊墊片156之肘狀部。
一導電凸塊材料使用一蒸鍍、電鍍、無電鍍、錫球滴落或網印製程來沉積於晶粒凸塊墊片152或基板凸塊墊片156上。該凸塊材料可為鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫及上述之結合，加上一選擇性助焊劑溶液。例如，該凸塊材料可為共晶錫/鉛、高鉛焊錫或無鉛焊錫。使用一合適黏接或黏結製程將該凸塊材料黏結至晶粒凸塊墊片152和基板凸塊墊片156。在一實施例中，該凸塊材料經由將該材料加熱超過它的熔點而進行回焊以形成內連線162。在一些應用中，內連線162被回焊一第二時間以改進晶粒凸塊墊片152和基板凸塊墊片156間之電性接觸。環繞該窄基板凸塊墊片156之凸塊材料維持回焊期間之晶粒定位。雖然所示內連線162為連接至軌跡線154成為一引腳上凸塊，但是該凸塊材料也可被形成於基板160上具有與晶粒凸塊墊片152等階層或更大之區域之凸塊墊片上。一選擇性底部填膠材料168被沉積於半導體晶粒150及基板160之間。
在高路徑密度應用中，極小化外洩間距為可期待的。為了降低軌跡線154間之間距，焊料遮罩被回焊而無焊料遮罩，經由省去產生焊料回焊污染之焊料遮罩來降低軌跡線154間之外洩間距，亦即回焊該凸塊材料而不用一焊料遮罩。焊料遮罩170可被形成於部分基板160上。然而，焊料遮罩170未被形成於產生焊料回焊污染之軌跡線154之基板凸塊墊片156上。也就是，設計來與該凸塊材料搭配之部分軌跡線154為沒有焊料遮罩170之對位開口。既然沒有對位開口環繞著晶粒凸塊墊片152或基板凸塊墊片156而形成，軌跡線154可以一較細間距來形成之，亦即軌跡線154可於較靠近附近結構處進行沉積。
沒有焊料遮罩170，給予之軌跡線154間之間距為P=D/2+PLT+W/2，其中，D為內連線162之基座部直徑，PLT為晶粒定位容限，且W為該軌跡線154之寬度。在一實施例中，給予100微米之凸塊直徑、10微米之晶粒定位容限及10微米之軌跡線寬度，則軌跡線154之最小外洩間距為75微米。該無焊料遮罩形成省去習知技術所見之對相鄰開口、焊料遮罩對位容限及最小可溶解對位開口間之焊料遮罩材料之細線間隔之需求。
當不用一焊料遮罩而回焊該凸塊材料以冶金及電性地連接半導體晶粒150之晶粒凸塊墊片152至軌跡線154之基板凸塊墊片156時，濕潤及表面張力使該凸塊維持自我封閉並保留於晶粒凸塊墊片152、基板凸塊墊片156及實際上在該些凸塊墊片佔用空間內緊鄰著軌跡線154的部分基板160之間的間隔內。
為了達到想要的自我封閉特性，該凸塊材料可在定位於晶粒凸塊墊片152或基板凸塊墊片156上之前先被浸入一助焊劑溶液中以選擇性地使該凸塊材料接觸之區域較軌跡線154環繞區域更濕潤。由於該助焊劑溶液之可濕潤特性，該熔化凸塊材料實際上仍被封閉於該些凸塊墊片所定義之區域內。該凸塊材料不會溢出至較不濕潤的區域。一薄氧化層或其它絕緣層可被形成於不欲因凸塊材料而造成該區域較不濕潤之所在區域上。因此，不需焊料遮罩170環繞著晶粒凸塊墊片152或基板凸塊墊片156。
在另一實施例中，一複合內連線形成於晶粒凸塊墊片152及基板凸塊墊片156間以得到想要之凸塊材料自我封閉。該複合內連線包含由銅、金、錫、鎳或鉛所製造之不可熔化基座部和由焊錫、錫或銦所製造之可熔化帽蓋部，類似於圖8。與不可熔化基座部材料有關之可熔化凸塊材料高度或容量被選擇以確保由於表面張力所產生之自我封閉。在回焊期間，該可熔化基座部材料環繞著該不可熔化基座部材料而自我封閉。環繞著該不可熔化基座部之可熔化凸塊材料同時維持著回焊期間之晶粒定位。大體上，該複合內連線之高度為相同或小於該凸塊直徑。在一些例子中，該複合內連線之高度為大於該內連線直徑。在一實施例中，給予100微米之凸塊基座部直徑，該不可熔化基座部之高度約為45微米且該可熔化帽蓋部之高度約為35微米。實際上在該些凸塊墊片所定義之區域內之熔化凸塊材料維持著封閉，此因用以形成包含不可熔化基座部和可熔化帽蓋部之複合凸塊所沉積之凸塊材料量被選擇以使所產生之表面張力足以使該凸塊材料實際上保留在該些凸塊墊片之佔用空間內並阻止溢出至計劃外之相鄰或附近區域之故。因此，不需焊料遮罩170環繞著晶粒凸塊墊片152或基板凸塊墊片156以降低軌跡線間距並增加路徑密度。
儘管本發明一或更多實施例已被詳加說明，熟知此項技術之人士會理解到對那些實施例之修正和改寫可被進行而不偏離下列申請專利範圍所提之本發明範圍。
10．．．覆晶型半導體元件
12．．．內連線
14．．．凸塊墊片
15．．．焊料遮罩
16．．．環狀焊料遮罩或對位開口
18．．．基板
20．．．軌跡線
30．．．軌跡線
32．．．軌跡線
34．．．軌跡線
36．．．凸塊
38．．．凸塊
40．．．基板
42．．．半導體晶粒
44．．．焊料遮罩
46．．．凸塊墊片
48．．．凸塊墊片
50．．．電子元件
52．．．印刷電路板
54．．．軌跡線
56．．．打線接合構裝
58．．．覆晶構裝
60．．．錫球陣列構裝
62．．．凸塊晶片載體
64．．．雙列式構裝
66．．．平面陣列構裝
68．．．多晶片模組構裝
70．．．四邊扁平無引腳構裝
72．．．四邊扁平構裝
74．．．半導體晶粒
76．．．接觸墊片
78．．．中介載體
80．．．導線
82．．．接線
84．．．封膠劑
88．．．半導體晶粒
90．．．載體
92．．．底部填膠或環氧樹脂黏接材料
94．．．接線
96．．．接觸墊片
98．．．接觸墊片
100．．．封膠化合物或封膠劑
102．．．接觸墊片
104．．．凸塊
106．．．載體
108．．．作用區域
110．．．內連線
111．．．凸塊墊片
112．．．內連線
114．．．訊號線
115．．．印刷電路板
116．．．封膠化合物或封膠劑
117．．．圓球或凸塊
118．．．導電軌道
120．．．覆晶型半導體晶粒
122．．．凸塊墊片
124．．．軌跡線
126．．．凸塊墊片
130．．．基板
132．．．內連線
138．．．底部填膠材料
140．．．焊料遮罩
144．．．複合內連線
146．．．不可熔化基座部
148‧‧‧可熔化帽蓋部
150‧‧‧覆晶型半導體晶粒
152‧‧‧晶粒凸塊墊片
154‧‧‧軌跡線
156‧‧‧凸塊墊片
160‧‧‧印刷電路板
162‧‧‧內連線
168‧‧‧底部填膠材料
170‧‧‧焊料遮罩
圖1說明形成於一半導體晶粒及一基板上之軌跡線間之傳統內連線剖面圖。
圖2說明透過一焊料遮罩開口將傳統內連線形成於該軌跡線上之俯視圖。
圖3a-3b說明介於使用一焊料遮罩回焊之內連線間之軌跡線之傳統安排。
圖4說明在表面上安裝有各類型構裝之印刷電路板。
圖5a-5d說明安裝至該印刷電路板之代表性半導體構裝之進一步細部。
圖6a-6b為具有在無一焊料遮罩下回焊於軌跡線上之內連線之一半導體元件。
圖7a-7b顯示沿著該軌跡線之凸塊墊片之進一步細部。
圖8顯示具有不可熔化基座部及可熔化帽蓋部之一複合內連線。
圖9a-9b為具有在無一焊料遮罩下回焊於軌跡線上之內連線之半導體元件之替代性實施例。
120．．．覆晶型半導體晶粒
122．．．凸塊墊片
126．．．凸塊墊片
130．．．基板
132．．．內連線
138．．．底部填膠材料

Claims (15)

  1. 一種製造半導體之方法，包括：提供包含一第一凸塊墊片之一第一半導體結構；提供包含一第二凸塊墊片之一第二半導體結構；沉積導電凸塊材料於該第一及第二凸塊墊片之間；及在無一焊料遮罩環繞著該第一凸塊墊片及第二凸塊墊片下回焊該導電凸塊材料以形成一內連線，其中，該導電凸塊材料於回焊期間自我封閉在該第一凸塊墊片或第二凸塊墊片上。
  2. 如申請專利範圍第1項之方法，進一步包含在環繞該第一凸塊墊片或第二凸塊墊片之區域上形成一絕緣層以使該區域較該第一及第二凸塊墊片不濕潤。
  3. 如申請專利範圍第1項之方法，其中，沉積於該第一及第二凸塊墊片間之導電凸塊材料量被選擇以使一表面張力可於回焊期間實際地維持該導電凸塊材料自我封閉於該第一及第二凸塊墊片內。
  4. 如申請專利範圍第1項之方法，其中，該內連線高度等於或小於該內連線直徑。
  5. 一種半導體元件，包括：一包含一第一凸塊墊片之半導體晶粒；一包含一第二凸塊墊片之基板；及一內連線，在無一焊料遮罩下經由回焊導電凸塊材料而形成於該第一及第二凸塊墊片之間，其中，該導電凸塊材料自我封閉於該第一凸塊墊片或第二凸塊墊片的佔用空 間內。
  6. 如申請專利範圍第5項之半導體元件，其中，該導電凸塊材料可在回焊前先浸入一助焊劑溶液中以增加可濕潤性。
  7. 如申請專利範圍第5項之半導體元件，進一步包含一絕緣層，形成於環繞該第一凸塊墊片或第二凸塊墊片之區域上以使該區域較該第一及第二凸塊墊片不濕潤。
  8. 如申請專利範圍第6項之半導體元件，其中，該內連線包含不可熔化部分及可熔化部分。
  9. 如申請專利範圍第7項之半導體元件，其中，沉積於該第一及第二凸塊墊片間之導電凸塊材料量被選擇以使一表面張力可於回焊期間實際地維持該導電凸塊材料自我封閉於該第一及第二凸塊墊片內。
  10. 一種製造半導體元件之方法，包含：提供包含一晶粒凸塊墊片之一半導體晶粒；提供包含一基板凸塊墊片之一基板；沉積一凸塊材料在該基板凸塊墊片或晶粒凸塊墊片上；將該半導體晶粒沉積於該基板上；及以自我封閉在該晶粒凸塊墊片或基板凸塊墊片上的該凸塊材料將該凸塊材料接合至該晶粒凸塊墊片和基板凸塊墊片。
  11. 如申請專利範圍第10項之方法，進一步包含將該凸塊材料浸入一助焊劑溶液中。
  12. 如申請專利範圍第10項之方法，進一步包含形成一絕緣層於環繞該晶粒凸塊墊片或基板凸塊墊片之區域上。
  13. 如申請專利範圍第10項之方法，其中，該凸塊材料包含不可熔化部分及可熔化部分。
  14. 如申請專利範圍第10項之方法，進一步包含形成一導電層於該基板或半導體晶粒上，其中給予之該導電層的外洩間距為D+PLT+W/2，其中，D為該凸塊材料之基座部直徑，PLT為晶粒定位容限，且W為該導電層之寬度。
  15. 如申請專利範圍第10項之方法，進一步包含進一步包含形成一導電層於該基板或半導體晶粒上，其中給予之該導電層的外洩間距為D/2+PLT+W/2，其中，D為該凸塊材料之基座部直徑，PLT為晶粒定位容限，且W為該導電層之寬度。
TW099114339A 2009-05-22 2010-05-05 半導體元件以及在無焊料遮罩的回焊期間的導電凸塊材料的自我封閉之方法 TWI508200B (zh)

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