TW202201740A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202201740A
TW202201740A TW110123783A TW110123783A TW202201740A TW 202201740 A TW202201740 A TW 202201740A TW 110123783 A TW110123783 A TW 110123783A TW 110123783 A TW110123783 A TW 110123783A TW 202201740 A TW202201740 A TW 202201740A
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Taiwan
Prior art keywords
die
memory
cache
processor
storage module
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TW110123783A
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English (en)
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吳昭誼
林佑明
世海 楊
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台灣積體電路製造股份有限公司
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Publication of TW202201740A publication Critical patent/TW202201740A/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
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    • G11C—STATIC STORES
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Abstract

一種半導體封裝包含處理器晶粒、儲存模組以及封裝基板。儲存模組包含彼此堆疊的快取記憶體單元陣列及記憶體單元陣列且電性連接到處理器晶粒，其中快取記憶體單元陣列配置成保留儲存在記憶體單元陣列中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒及儲存模組。

Description

半導體封裝
本揭露是有關於一種半導體封裝。
半導體行業已經由於多種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度的持續改進而經歷快速增長。主要來說，最小特徵大小的反復減小已經帶來集成密度的改進，這允許將更多元件集成到給定區域中。隨著對於縮小的電子裝置的需求增長，對於半導體晶粒的更小且更創新的封裝技術的需求已經出現。
本揭露提供一種半導體封裝，其可提高系統的效率。
根據本揭露的一些實施例，一種半導體封裝包含處理器晶粒、儲存模組以及封裝基板。儲存模組包含彼此堆疊的快取記憶體單元陣列及記憶體單元陣列且電性連接到處理器晶粒，其中快取記憶體單元陣列配置成保留儲存在記憶體單元陣列中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒及儲存模組。
根據本揭露的一些實施例，一種半導體封裝包含處理器晶粒、快取記憶體晶粒、記憶體晶粒以及封裝基板。快取記憶體晶粒包含MRAM快取記憶體單元陣列且電性連接到處理器晶粒。記憶體晶粒堆疊在快取記憶體晶粒上方且包含記憶體單元陣列，其中記憶體晶粒電性連接到快取記憶體晶粒及處理器晶粒，且快取記憶體晶粒配置成保留儲存在記憶體晶粒中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒、快取記憶體晶粒以及記憶體晶粒。
根據本揭露的一些實施例，一種半導體封裝包含處理器晶粒、記憶體晶粒以及封裝基板。記憶體晶粒電性連接到處理器晶粒且包含在基板上彼此堆疊的快取記憶體單元陣列及垂直堆疊式記憶體單元陣列，其中快取記憶體單元陣列配置成保留儲存在垂直堆疊式記憶體單元陣列中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒及記憶體晶粒。
以下揭露內容提供用於實施所提供主題的不同特徵的許多不同實施例或實例。下文描述元件及佈置的特定實例來簡化本揭露。當然，這些元件及佈置僅為實例且並不意圖為限制性的。舉例來說，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且還可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。這種重複是出於簡化及清楚的目的，且本身並不規定所論述的各種實施例及/或配置之間的關係。
此外，為易於描述，可使用例如「在…下方」、「在…之下」、「下部」、「在…之上」、「上部」以及類似術語的空間相對術語，以描述如圖中所示出的一個元件或特徵相對於另一元件或特徵的關係。除圖中所描繪的定向外，空間相關術語意圖涵蓋裝置在使用或操作中的不同定向。設備可以其它方式定向（旋轉90度或處於其它定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
此外，為易於描述，可在本文中使用例如「第一」、「第二」、「第三」、「第四」以及類似術語的術語，以描述如圖中所示出的類似或不同元件或特徵，且可取決於存在次序或描述的上下文而互換地使用所述術語。
圖1示出根據本揭露的一些示例性實施例的半導體封裝的橫截面圖。本文中描述的是實施2.5D及/或3D記憶體堆疊晶粒系統的半導體封裝及製造方法。參考圖1，例如，根據一個實施例所揭露，半導體封裝100包含：處理器晶粒110、電性連接到所述處理器晶粒110且包含一或多個記憶體層的儲存模組120；以及在其上安置處理器晶粒110及儲存模組120的封裝基板130。在一些實施例中，處理器晶粒110可以是其中包含邏輯電路的邏輯裝置晶粒。在一些實施例中，處理器晶粒110可包含以具有行及列的陣列設置的多個個別及單獨的處理單元。在其它形式中，處理單元可放置在除處理單元的行及列以外的幾何配置陣列中。處理單元中的每一個是任何類型的各種資料處理器。舉例來說，處理晶粒可包含中央處理單元（central processing unit；CPU）、數位訊號處理器、特定圖形處理器（graphics-specific processor）、微控制器單元（microcontroller unit；MCU）、通訊處理器或任何其它類型的處理單元。此外，處理單元可以是相同類型的處理單元或可在處理器晶粒110中的處理單元的類型之間不同。當實現功能上不同類型的處理單元時，由每一處理單元所佔用的電路區域可不同。
在一些實施例中，處理器晶粒110可包含處理單元及在處理單元週邊的外部連接區域。相應地，例如焊料凸塊的多個導電凸塊150放置在外部連接區域處以提供處理器晶粒110的進一步電性連接。在這一實施例中，外部連接區域是處理器晶粒110的從外部與處理器晶粒110進行電性連接的區域。在外部連接區域內的導電凸塊150之下是接觸墊及導電佈線（圖1不可見），所述導電佈線將導電凸塊150連接到處理器晶粒110內的預定電路。導電凸塊150傳達功率、資料、控制訊號以及位址訊號且提供獲得對處理器晶粒110的外部存取的方法。
根據本揭露的一些實施例，圖1示出半導體封裝100，其具有在下部層的處理器晶粒110，例如片上系統（system on chip；SOC），也稱為「邏輯晶粒」、功能性矽晶粒或功能性半導體裝置，且接著具有在上部層的儲存模組120。進一步描繪封裝基板130，其經由例如球柵陣列（ball grid array；BGA）的多個導電凸塊150與處理器晶粒110及儲存模組120接合，如所繪示。儲存模組120的電互連經由例如矽通孔（through silicon via；TSV）、層間通孔（through interlayer via；TIV）或類似物的通孔113且隨後經由導電凸塊150電性接合到封裝基板130且電性接合到封裝基板130。此外，描繪了在基板與另一板（例如主機板、印刷電路板（printed circuit board；PCB）、主機板等）之間提供電性連接的焊料球160。本文中示出的半導體封裝100提供至少一個三維（three dimensional；3D）堆疊儲存模組120（例如，快取記憶體晶粒122及記憶體晶粒124），其緊密地集成到例如SOC晶粒110的微處理器中。
在一些實施例中，處理器晶粒110可包含記憶體快取記憶體（memory cache），例如用於處理器晶粒110的靜態隨機存取記憶體（static random-access memory；SRAM）。通常，SRAM是靜態隨機存取記憶體，且取決於介面的內部配置及差異而具有各種類型，例如非同步靜態隨機存取記憶體及同步靜態隨機存取記憶體。任何靜態隨機存取記憶體可用於處理器晶粒110的記憶體快取記憶體。可根據特定應用使用其它記憶體晶粒配置。
圖13示出根據本揭露的一些示例性實施例的半導體封裝的框圖。參考圖1及圖13，在一些實施例中，儲存模組120電性連接到處理器晶粒110且包含彼此堆疊的快取記憶體單元（例如，圖13中所繪示的快取記憶體單元1225）的陣列及記憶體單元（例如，圖13中所繪示的記憶體單元1245）的陣列。快取記憶體單元1225的陣列配置成保留儲存在記憶體單元1245的陣列中且由處理器晶粒110頻繁地使用的資料的副本。在本揭露實施例中，儲存模組120包含具有快取記憶體單元1225的陣列的快取記憶體晶粒122，以及堆疊在快取記憶體晶粒122上方且具有記憶體單元1245的陣列的記憶體晶粒124。
在一些實施例中，快取記憶體單元1225中的每一個是半導體快取記憶體（即，記憶體）且可以是任何類型的快取記憶體。舉例來說，處理器晶粒110的快取記憶體單元中的每一個可以是靜態隨機存取記憶體（SRAM）、快閃記憶體、磁阻式隨機存取記憶體（magnetoresistive random access memory；MRAM）、動態隨機存取記憶體（dynamic random access memory；DRAM）或任何其它類型的記憶體。在本揭露實施例中，舉例來說，處理器晶粒110的處理單元的類型可以是（包含）SRAM且快取記憶體晶粒122的快取記憶體單元的類型可以是（包含）MRAM。換句話說，快取記憶體晶粒122包含MRAM快取記憶體單元陣列。在一些實施例中，記憶體晶粒124的記憶體單元陣列的類型可包含非易失性記憶體（non-volatile memory；NVM）、垂直與非型（Vertical NAND）快閃記憶體、或非型（NOR）快閃記憶體、動態隨機存取記憶體（DRAM）、快閃記憶體、相變記憶體（phase change memory；PCM）、電阻性隨機存取記憶體（resistive random access memory；RRAM），其可為比快取記憶體晶粒122慢的資料儲存。在一些實施例中，記憶體晶粒124可以是2D記憶體裝置或3D記憶體裝置。
在一些佈置中，3D記憶體裝置可包含多個脊狀堆疊（ridge-shaped stacks），其是以由絕緣材料間隔開的多個條帶式的半導體材料的形式來呈現。舉例來說，半導體材料的條帶是NAND串中的儲存胞元的水平溝道。半導體材料的條帶在脊形堆疊的側面上具有側表面。可耦合到行解碼器的多個字線在多個脊形堆疊上方正交地延伸。記憶體元件位於堆疊的表面與字線之間。記憶體元件是可程式設計且非易失性的（如可程式設計電阻結構或電荷捕獲結構），或是可程式設計且易失性的。保形字線、記憶體元件以及半導體條帶的堆疊組合形成記憶體單元（胞元）的堆疊。
在一些實施例中，處理器晶粒110的每一快取記憶體單元可連接到快取記憶體晶粒122的快取記憶體單元中特定指示的一個。應理解，可在快取記憶體晶粒122的快取記憶體單元中的每一個之間提供一些物理分離及互連。快取記憶體晶粒122的快取記憶體單元1225的陣列配置成用以儲存資料使得可更快地服務此資料的未來請求。儲存在快取記憶體單元中的資料可為較早計算的結果或儲存在別處（例如，記憶體晶粒124的記憶體單元陣列）的資料的副本。快取記憶體命中（cache hit）在可在快取記憶體晶粒122中找到所請求資料時發生，而快取記憶體未命中（cache miss）在未在快取記憶體晶粒122中找到所請求資料時發生。快取記憶體命中是通過從快取記憶體單元讀取資料來達成，這比重新計算結果或從更慢的資料儲存（例如，記憶體晶粒124）讀取更快。因此，可由快取記憶體服務的請求越多，系統執行得越快。在一些實施例中，快取記憶體晶粒122（例如，MRAM）的快取記憶體密度（容量）可大於處理器晶粒110（例如，SRAM）的快取記憶體密度（容量），因此快取記憶體晶粒122可一次處理比處理器晶粒110更多的資料，從而提高系統的效率。
在圖1中所繪示的實施例中，儲存模組120安置在處理器晶粒110上，且處理器晶粒110安置在封裝基板130上。在一些實施例中，處理器晶粒110包含延伸穿過處理器晶粒110且將儲存模組120及封裝基板130電性連接的多個通孔113。製造這類半導體封裝100的製造方法中的一種可包含以下步驟。
圖2到圖7示出在根據本揭露的一些示例性實施例的半導體封裝的製造中的中間階段的橫截面圖。參考圖2，在一些實施例中，首先設置半導體晶圓112'。在後續切割製程之後，半導體晶圓112'用於形成圖1的處理器晶粒110。半導體晶圓112'包含主動表面S1及在其內部形成的多個（矽）通孔113。另外，半導體晶圓112'的主動表面S1包含第一佈線層114。第一佈線層114包含第一互連件（例如，配線工程互連件）1141，且第一互連件1141連接到通孔113中的每一個的一端。
現在參考圖2及圖3，對半導體晶圓112'的背表面（與主動表面S1相反）進行例如背面研磨處理的膜薄化處理以暴露通孔113中的每一個的另一端。通過此處進行的膜薄化處理，半導體晶圓112'的厚度減小到接近於最終半導體晶圓112的目標厚度的值。因此，研磨量是通過從晶圓的初始厚度減去晶圓的目標厚度所獲得的差值。
隨後，參考圖4，第二佈線層116形成於半導體晶圓112的背表面S2上。第二佈線層116中包含多個第二互連件1161，其連接到通孔113的另一端。在一些實施例中，第二佈線層116可以是單個或多個金屬層及介電層的堆疊。隨後，多個凸塊墊1162可在形成最上部介電層上且電性連接到第二互連件1161。在鍍覆製程中，為了增加凸塊墊1162與後續接合的導電凸塊140之間的可焊性，可通過鍍覆（plating）形成銅層及鎳金堆疊層。金層可用作鍍覆結構的表面層，其具有良好的潤濕性，因此增加後續焊接製程的良率。
參考圖5，在一些實施例中，半導體晶圓112隨後鋸切成多個個別處理器晶粒110。隨後，參考圖6，在鋸切半導體晶圓112後，個別處理器晶粒110中的一個以覆晶的方式接合到封裝基板130。處理器晶粒110的通孔113經由導電凸塊150電性連接到封裝基板130。此外，在本揭露實施例中，底部填充物155可填充在處理器晶粒110與封裝基板130之間以圍封導電凸塊150。底部填充物155可在處理器晶粒110接合到封裝基板130之前預先形成在封裝基板130上，或在處理器晶粒110接合到封裝基板130之後填充在處理器晶粒110與封裝基板130之間。
隨後，如圖7中所繪示，包含快取記憶體晶粒122及記憶體晶粒124的儲存模組120以覆晶的方式接合到處理器晶粒110。在一些實施例中，儲存模組120經由導電凸塊140以覆晶的方式接合到處理器晶粒110。儲存模組120經由對應的導電凸塊140連接到凸塊墊1162。此外，在本揭露實施例中，底部填充物145選擇地施加於儲存模組120與第二佈線層116之間，且底部填充物145圍封導電凸塊140。填充底部填充物145的步驟可在儲存模組120以覆晶接合到處理器晶粒110之前或之後執行。也就是說，底部填充物145可在儲存模組120接合到處理器晶粒110之前形成於第二佈線層116上，或可在儲存模組120接合到處理器晶粒110之後填充在儲存模組120與第二佈線層116之間。此時，半導體封裝100的製造製程可能大體上完成。
應注意，圖4中所繪示的所得結構是處理器晶粒110的半成品，其可在鋸切製程後以晶圓或個別晶粒的形式運輸。因此，在替代實施例中，在鋸切製程之前，包含快取記憶體晶粒122及記憶體晶粒124的多個儲存模組120可經由導電凸塊140以覆晶的方式接合到圖4中所繪示的半導體晶圓112。類似地，底部填充物145任選地施加於儲存模組120與第二佈線層116之間，其中底部填充物145圍封導電凸塊140。在儲存模組120以覆晶的方式接合到半導體晶圓112之後，將半導體晶圓112鋸切成多個個別處理器晶粒110。隨後，處理器晶粒110中的一個以覆晶的方式接合到封裝基板130。處理器晶粒110的通孔113經由導電凸塊150電性連接到封裝基板130。此外，底部填充物155還可填充在處理器晶粒110與封裝基板130之間以圍封導電凸塊150。本揭露不限制方法的順序。
圖8到圖10示出在根據本揭露的一些示例性實施例的半導體封裝的製造中的中間階段的橫截面圖。在一些實施例中，可通過將記憶體晶粒124及快取記憶體晶粒122堆疊在彼此的頂部上來形成儲存模組120。以下描述示出製造儲存模組120的可能的製程中的一個。
圖8示出快取記憶體晶粒122的半成品，其可能仍然呈晶圓形式。如圖8中所繪示，形成至少一個基板通孔1224'。基板通孔1224'可首先埋入快取記憶體晶粒122的基板1221'中且連接到快取記憶體晶粒122的內埋佈線（例如，快取記憶體晶粒122的基板工程（front end of line；FEOL）1222的內埋佈線），所述內埋佈線電性連接到快取記憶體單元1225的陣列。視需要在通孔1224上形成內埋佈線。多層中間層內埋佈線（例如，配線工程（back end of line；BEOL）1223）埋入中間層中。至少一個電極墊1228（例如，鋁墊）在配線工程1223上方形成，且其上除了接墊開口的部分由最終鈍化膜1229覆蓋。至少一個導電凸塊140（例如銅凸塊電極）形成於電極墊1228上。在一些實施例中，焊料阻擋金屬膜（例如，鎳膜）可通過電鍍或類似方法形成於導電凸塊140上，且例如無鉛焊料的焊料層（例如，錫銀類焊料）可通過電鍍或類似方法形成於焊料阻擋金屬膜上。
隨後，參考圖8及圖9，對基板1221'的背表面進行例如背面研磨處理的膜薄化處理以暴露基板通孔1224的另一端。通過此處進行的膜薄化處理，基板1221的厚度減小到接近於快取記憶體晶粒122的最終基板1221的目標厚度的值。相應地，基板通孔1224垂直地延伸穿過快取記憶體晶粒122的基板1221且電性連接到快取記憶體單元1225的陣列。隨後，背側接合墊1227可形成在基板1221的背表面上方且電性連接到基板通孔1224。接合墊1227的形成可包含以下步驟，但不限於此。
在一些實施例中，可通過使用例如乾式蝕刻（使用鹵素氣體作為氣體系統）來輕微蝕刻基板1221的背側上的矽基板1221來使基板通孔1224從基板1221的背表面突出少許。這種蝕刻是所謂的回蝕。隨後，將作為背側絕緣膜1226的樹脂膜（例如，聚醯亞胺）應用到基板1221的幾乎整個背表面，接著通過CMP或回蝕來使其平面化且再次暴露基板通孔1224的下端部分。隨後，例如鈦膜、銅膜、鎳膜以及類似膜的金屬膜通過例如濺鍍形成於基板1221的幾乎整個背表面上。隨後，通過例如濕式蝕刻來圖案化所得金屬膜，以形成接合墊1227。
隨後，參考圖10，圖9中所繪示的所得結構附接到切割帶上，所述切割帶附接到切割框架上。在這種狀態下，呈晶圓形式的所得結構通過例如切割劃分成多個個別的快取記憶體晶粒122。隨後，記憶體晶粒124通過例如焊料接合經由多個導電凸塊126接合到快取記憶體晶粒122中的一個的背表面。在一些實施例中，快取記憶體晶粒122中的一個的背表面上的接合墊1227可通過例如焊料接合來接合到記憶體晶粒124的接合墊1244上的導電凸塊126。通過這種接合，多個基板通孔1224電性連接到例如設置在記憶體晶粒124上的導電凸塊126。在一些實施例中，導電凸塊126可包含微凸塊。記憶體晶粒124可以與快取記憶體晶粒122類似的方式形成，且包含基板1241、形成於基板1241上方的基板工程1242以及形成於基板工程1242上方的佈線工程1243。
圖11示出根據本揭露的一些示例性實施例的半導體封裝的儲存模組的橫截面圖。應注意，圖11中所繪示的儲存模組120'含有與圖8到圖10較早所揭露的儲存模組120相同或類似的許多特徵。出於清楚及簡單的目的，可省略相同或類似特徵的細節描述，並且相同或類似附圖標號指代相同或類似組件。如下描述圖11中所繪示的儲存模組120'與圖8到圖10較早所揭露的儲存模組120之間的主要差異。
參考圖11，在一些實施例中，記憶體晶粒124的至少一個接合墊1244直接接合到快取記憶體晶粒122的至少一個接合墊1227。換句話說，記憶體晶粒124可通過混合接合（hybrid bonding）技術接合到快取記憶體晶粒122。通常，混合接合包含記憶體晶粒124及快取記憶體晶粒122中的金屬特徵的直接金屬對金屬接合以及記憶體晶粒124中的絕緣材料與快取記憶體晶粒122中的絕緣材料的熔融接合。
直接接合可發生在記憶體晶粒124的接合墊1244與快取記憶體晶粒122的接合墊1227之間接合墊1244與接合墊1227的接合代表接墊對接墊混合接合。在替代實施例中，記憶體晶粒124與快取記憶體晶粒122之間的接合還可以是通孔對通孔混合接合、通孔對接墊混合接合、接墊對通孔混合接合或類似接合。記憶體晶粒124及快取記憶體晶粒122的接合墊是由例如銅、金、錫以及類似物或其合金的導電材料製成。記憶體晶粒124中的通孔或接合墊中的每一個的導電材料可與快取記憶體晶粒122中的導電材料相同或不同。
另外，快取記憶體晶粒122及記憶體晶粒124還分別包含絕緣材料1227a及絕緣材料1224a。絕緣材料1227a及絕緣材料1224a可以是氧化物、氮氧化物、介電質、聚合物等等。在一些實施例中，絕緣材料1227a可以與絕緣材料1224a是相同材料，而在其它實施例中，絕緣材料1227a可不同於絕緣材料1224a。
在一些實施例中，在混合接合製程中，快取記憶體晶粒122的接合墊與記憶體晶粒124的接合墊對準且接觸記憶體晶粒124的接合墊。快取記憶體晶粒122的絕緣材料1227也接觸記憶體晶粒124的絕緣材料1224。隨後，可執行退火以直接接合導電材料且將絕緣材料熔融接合在一起。退火導致金屬在快取記憶體晶粒122的接墊及記憶體晶粒124的接墊中相互擴散以導致直接金屬對金屬接合。根據各種實施例，絕緣材料1227與絕緣材料1244之間的所得接合是絕緣體對絕緣體接合，其可以是無機對聚合物接合、聚合物對聚合物接合或無機對無機接合。
在一些實施例中，混合接合可使得接點能夠具有精細間距。因此，混合接合可允許例如快取記憶體晶粒122及記憶體晶粒124的晶粒具有高密度連接。此外，混合接合製程允許兩個結構之間的接合不包含焊接材料，且因此可能增大封裝結構的可靠性及良率。又另外，因為在晶粒之間不使用接點，所以混合接合製程產生更薄的晶粒堆疊。
圖12示出根據本揭露的一些示例性實施例的半導體封裝的儲存模組的橫截面圖。應注意，圖12中所繪示的儲存模組120''含有與圖8到圖10較早所揭露的儲存模組120相同或類似的許多特徵。出於清楚及簡單的目的，可省略相同或類似特徵的細節描述，並且相同或類似附圖標號指代相同或類似組件。如下描述圖12中所繪示的儲存模組120''與圖8到圖10較早所揭露的儲存模組120之間的主要差異。
現在參考圖12，在本揭露實施例中，快取記憶體晶粒122及記憶體晶粒124可集成到一個記憶體晶粒120''中。換句話說，實際上，儲存模組120''是包含在基板121''上彼此堆疊的快取記憶體單元1225的陣列及記憶體單元1245的陣列的記憶體晶粒120''。在一些實施例中，快取記憶體單元1225的陣列安置於基板工程結構123''上方的第一佈線工程結構122''中，且配置成保留儲存在記憶體單元1245的陣列中且由處理器晶粒110頻繁地使用的資料的副本。在這一實施例中，記憶體單元1245的陣列安置於第二佈線工程結構124''中，且記憶體單元1245的陣列包含垂直堆疊式記憶體單元陣列，即，3D記憶體單元陣列。也就是說，記憶體晶粒120''的類型是3D記憶體。3D記憶體包含3D非易失性記憶體（NVM）、3D NAND快閃記憶體或垂直NAND（Vertical NAND；V-NAND）快閃記憶體、3D NOR快閃記憶體等。
在一些實施例中，記憶體單元1245的陣列包含垂直堆疊式儲存胞元，其分別包含使用氧化物半導體層作為溝道的薄膜電晶體。換句話說，記憶體單元1245包含氧化物半導體垂直溝道。在一個實施例中，氧化物半導體垂直溝道是金屬氧化物半導體。氧化物半導體可具有晶體結構。對於垂直NAND（V-NAND）或3D NAND記憶體，儲存胞元垂直堆疊，且採用電荷捕獲快閃記憶體架構。垂直層允許較大面積的位元密度而不需要更小個別胞元。使用這類配置，記憶體單元1245的陣列能夠彼此堆疊。因此，對於快取記憶體晶粒122及記憶體晶粒124集成到一個記憶體晶粒中的實施例，記憶體單元1245的類型應該為3D記憶體。
另外，在一些實施例中，快取記憶體單元1225的陣列可採用MOSFET溝道，其可包含基板工程結構（例如，基板工程結構123''）。相應地，在這一實施例中，記憶體單元1245形成於這類快取記憶體單元1225上方（在形成快取記憶體單元1225之後形成）。換句話說，這類快取記憶體單元1225位於基板121''（及基板工程結構123''）與記憶體單元1245的陣列之間。在不使用MOSFET溝道（例如，而是使用OTS選擇器）的快取記憶體單元1225的替代實施例中，3D記憶體單元1245的陣列可在形成快取記憶體單元1225的陣列之前或之後形成。也就是說，記憶體單元1245還可安置在基板121''（及基板工程結構123''）與快取記憶體單元1225的陣列之間。在一些實施例中，快取記憶體單元1225的類型是MRAM，但本揭露不限於此。在另一實施例中，快取記憶體單元1225的類型還可包含SRAM、（3D）NAND、（3D）NVM、（3D）NOR、DRAM、PCM、RRAM或類似類型。
參考圖13，利用這類配置，處理器晶粒110耦合到包含快取記憶體單元1225的陣列及記憶體單元1245的陣列的儲存模組120、儲存模組120'、儲存模組120''。相應地，當在快取記憶體單元1225中找到所請求資料時，處理器晶粒110從快取記憶體單元1225讀取資料，這比重新計算結果或從更慢的資料儲存（例如，記憶體晶粒124）讀取更快。當未在快取記憶體單元1225中找到所請求資料時，處理器晶粒110可從記憶體單元1245請求資料。處理器晶粒110還可以配置成將資料寫入到快取記憶體單元1225及記憶體單元1245中，且記憶體單元1245可以配置成用以更新快取記憶體單元1225中的資料。因此，通過儲存模組120、儲存模組120'、儲存模組120''與快取記憶體晶粒122（或快取記憶體單元1225的陣列）一起配置，更多的請求可由快取記憶體單元1225來服務，從而改進系統性能。另外，快取記憶體晶粒122（例如，MRAM）的快取記憶體密度（容量）大於處理器晶粒110（例如，SRAM）的快取記憶體密度（容量），因此快取記憶體晶粒122可一次處理比處理器晶粒110更多的資料，從而提高系統的效率。
圖14示出根據本揭露的一些示例性實施例的半導體封裝的橫截面圖。應注意，圖14中所繪示的半導體封裝100a含有與圖1到圖7較早所揭露的半導體封裝100相同或類似的許多特徵。出於清楚及簡單的目的，可省略相同或類似特徵的細節描述，並且相同或類似附圖標號指代相同或類似組件。如下描述半導體封裝100a與圖1到圖7較早所揭露的半導體封裝100之間的主要差異。
現在參考圖14，在一些實施例中，半導體封裝100a更包含安置在封裝基板130上的中介層（interposer）170，且處理器晶粒110及儲存模組120、儲存模組120'或儲存模組120''並排地安置在中介層170上。在本揭露實施例中，儲存模組可為以上示出的任何實施例，其意指儲存模組的快取記憶體晶粒122及記憶體晶粒124可利用微凸塊來接合、通過混合接合（hybrid bonding）來接合或集成到一個記憶體晶粒中。在本揭露實施例中，處理器晶粒110及儲存模組120、儲存模組120'或儲存模組120''經由互連件（例如，導電凸塊140）互連到中介層。這一示例性實施例中的互連件140是例如密集的晶粒對晶粒覆晶微凸塊；然而，可使用其它類型的晶粒對晶粒精細間距互連件。
在一些實施例中，處理器晶粒110及儲存模組120、儲存模組120'或儲存模組120''經由晶粒對晶粒互連件140的一部分連接到中介層170的上表面，所述晶粒對晶粒互連件140可以是精細間距互連件或可以是常規的覆晶微凸塊。晶粒對晶粒互連件140中的一些可耦合到其它較大互連件，所述較大互連件在本文中被稱作「接點」（例如，導電凸塊150）以免與晶粒對晶粒互連件（「互連件」）140混淆。舉例來說，接點150可以使用例如矽通孔（“TSV”）的基板通孔耦合到互連件140。在這一實施例中，接點150是微型球；然而，可使用其它類型的晶片對晶片大型互連件。另外，接點150大體上大於互連件140。由於互連件140的互連密度比接點150的互連密度大，因此可如先前描述提高IC的頻寬。此外，在這一示例性實施例中，中介層170是矽中介層；然而，在其它實施例中，可使用其它類型的基板或晶粒平臺。
圖15到圖22示出在根據本揭露的一些示例性實施例的半導體封裝的製造中的中間階段的橫截面圖。示例性實施例描繪用於形成半導體封裝100b的另一製造方法。應注意，圖15到圖22中所繪示的半導體封裝100b及其製造方法含有與圖1到圖7較早所揭露的半導體封裝100及其製造方法相同或類似的許多特徵。出於清楚及簡單的目的，可省略相同或類似特徵的細節描述，並且相同或類似附圖標號指代相同或類似組件。示例性實施例的製造製程可包含以下步驟。
參考圖15，如圖15中所繪示的至少一個處理器晶粒110b'設置在載體C1上。在一些實施例中，黏合層A1可安置在載體C1上。在一些實施例中，載體C1可以是玻璃載體、陶瓷載體或類似物。黏合層A1可以是光熱轉換釋放塗層（light to heat conversion release coating；LTHC）或類似物。在一些實施例中，絕緣層106可任選地安置在載體C1上。另外，多個通孔（導電柱）113設置於載體C1上，且通孔113可包圍其中安置有處理器晶粒110b'的裝置區域。通孔113可在安置處理器晶粒110b'之前或之後設置於載體C1上。本揭露並不限於此。在一些實施例中，處理器晶粒110b'可以是其中包含邏輯電路的邏輯裝置晶粒。舉例來說，處理晶粒可包含中央處理單元（CPU）、數位訊號處理器、特定圖形處理器、微控制器單元（MCU）、通訊處理器或任何其它類型的處理單元。此外，處理單元可以是相同類型的處理單元或可在處理器晶粒110b'中的處理單元的類型之間不同。雖然示出一個處理器晶粒110b'，但是更多晶粒可放置在載體C1上方且彼此齊平。
在一些實施例中，載體C1可包含例如以陣列方式佈置的多個晶粒區域A1。相應地，通孔113可如圖15中所示出形成為包圍晶粒區域A1中的每一個，且多個處理器晶粒110b'可分別安置在晶粒區域A1上，因此通孔113可包圍處理器晶粒110b'中的每一個。使用這種佈置，可同時形成多個半導體封裝。出於簡潔及清楚起見，圖15到圖22中示出半導體封裝中的一個的製造流程。舉例來說，圖15中示出由一些通孔113包圍的處理器晶粒110b'中的一個。
在一些實施例中，通孔113可預先形成，且隨後放置在載體C1上。在替代實施例中，通孔113可通過例如鍍覆製程形成。通孔113的鍍覆可在放置處理器晶粒110b'之前執行，且可包含在載體C1上方形成晶種層（未繪示）、形成並圖案化光阻層（未繪示）以及鍍覆晶種層的經由光阻層暴露的部分上的通孔113。可隨後去除光阻層及晶種層的由光阻層覆蓋的部分。通孔113的材料可包含銅、鋁或類似物。相應地，通孔113的底端與處理器晶粒110b'的背表面大體上齊平。
在一些示例性實施例中，多個導電通孔1101（例如，銅通孔）可形成於處理器晶粒110b'的基板1103上方的處理器晶粒110b'的主動表面（例如，頂表面）上。在一些實施例中，介電層1102'可形成於處理器晶粒110b'的主動表面（例如，頂表面）上，且可覆蓋導電通孔1101的頂表面。在其它實施例中，介電層1102'的頂表面可與導電通孔1101的頂表面大體上齊平。替代地，可省略介電層1102'。在一些實施例中，通孔113的頂端可與導電通孔1101的頂表面大體上齊平。在其它實施例中，通孔113的頂端可大體上高於或低於導電通孔1101的頂表面。
隨後，載體C1上的處理器晶粒110b'及通孔113由包封材料115至少側向地包封。換句話說，包封材料115設置在載體C1上方以至少側向地包封通孔113及處理器晶粒110b'。在一些實施例中，包封材料115填充處理器晶粒110b'與通孔113之間的間隙。包封材料115可包含模製化合物、環氧樹脂或樹脂等。
在一些實施例中，包封材料115首先覆蓋通孔113的頂端及介電層1102'的頂表面。隨後，執行薄化製程（可以是研磨製程）以薄化包封材料115（以及介電層1102'），直到顯露通孔113的頂端以及導電通孔1101的頂表面為止。所得結構繪示於圖16中。由於薄化製程，通孔113的頂端與導電通孔1101的頂表面大體上齊平，且與包封材料115的頂表面以及介電層1102的頂表面大體上齊平，如圖16中所繪示。在整個描述中，包含如圖16中所繪示的處理器晶粒110、通孔113以及包封材料115的所得結構被稱作包封處理器晶粒101，其在製程中可具有晶圓形式。相應地，在包封處理器晶粒101中，處理器晶粒110安置於晶粒區域處，通孔113延伸穿過晶粒區域A1外部的包封處理器晶粒101，且包封材料115側向地包封處理器晶粒110及通孔113。換句話說，包封材料115包封其中的處理器晶粒110，且通孔113延伸穿過包封材料115。
接著，參考圖17，重佈線電路結構114形成於處理器晶粒110b及包封材料115上方。重佈線電路結構114電性連接到處理器晶粒110b及通孔113。在一些實施例中，重佈線電路結構114形成於包封處理器晶粒101上方以連接到處理器晶粒110b的導電通孔以及通孔113。重佈線電路結構114可通過例如以下形成：沉積導電層，圖案化導電層以形成重佈線電路1141，部分地覆蓋重佈線電路1141，以及填充重佈線電路1141與介電層1142之間的間隙等。重佈線電路1141的材料可包含金屬或金屬合金，其包含鋁、銅、鎢及/或其合金。介電層1142可由例如氧化物、氮化物、碳化物、碳氮化物、其組合的介電材料及/或其多層來形成。重佈線電路1141形成於介電層1142中且電性連接到處理器晶粒110b及通孔113。
參考圖18，接點（導電凸塊）150中的至少一個安置在根據一些示例性實施例的重佈線電路結構114上。在一些實施例中，至少一個集成被動裝置（integrated passive device；IPD）152也可安置在重佈線電路結構114上。接點150的形成可包含將焊料球放置在UBM層上（或重佈線電路結構114上），且隨後回焊焊料球。在替代實施例中，接點150的形成可包含執行鍍覆製程以在重佈線電路結構114上形成焊料區域，且隨後回焊焊料區域。接點150還可包含導電柱，或具有焊料蓋的導電柱，其也可通過鍍覆形成。IPD 152可使用例如薄膜及微影製程的標準晶圓製造技術來製造，且可經由例如覆晶接合或引線接合等來安裝在重佈線電路結構114上。
隨後，參考圖19，可去除載體C1。在一些實施例中，通過使黏合層A1失去或降低黏合力來從包封處理器晶粒101及絕緣層106（如果存在）拆離載體C1。隨後，黏合層A1與載體C1一起被去除。舉例來說，黏合層A1可暴露於UV光，使得黏合層A1失去或降低黏合力，且因此可從包封處理器晶粒101去除載體C1及黏合層A1。
在省略絕緣層106的實施例中，在去除載體C1之後，通孔113的底端顯露。在示出的結構中，通孔113的底端與處理器晶粒110b的底表面以及包封材料115的底表面齊平。可執行研磨製程以輕微地研磨處理器晶粒110b的背表面及通孔113的底端。替代地，可跳過研磨製程。
參考圖20，在具有絕緣層106的實施例中，可隨後對絕緣層106執行圖案化製程以形成多個開口1061。開口1061分別位於通孔113上以顯露通孔113的底端。在一些實施例中，開口1061可通過微影製程、雷射鑽孔製程等形成。
參考圖21，多個導電凸塊140可形成在包封處理器晶粒101上以電性連接到通孔113。在一些實施例中，導電凸塊140安置在絕緣層106的開口1061中以連接到通孔113。在一些實施例中，導電凸塊140可包含微凸塊或類似物。在整個描述中，包含如圖21中所繪示的處理器晶粒110b、通孔113、包封材料115以及重佈線電路結構114的所得結構被稱作處理器封裝件105，其在製程中可具有晶圓形式。相應地，在處理器封裝件105中，處理器晶粒110b由延伸穿過包封材料115的通孔113包圍，且包封材料115包封處理器晶粒110b及通孔113。重佈線電路結構114安置於處理器晶粒110b及包封材料115上方。
隨後，參考圖22，儲存模組120、儲存模組120'或儲存模組120''安置在處理器封裝件105上且經由處理器封裝件105的導電凸塊140電性連接到通孔113。儲存模組120、儲存模組120'或儲存模組120''以儲存模組120、儲存模組120'或儲存模組120''通過導電凸塊140的方式安裝在處理器封裝件105上。在一些實施例中，儲存模組120、儲存模組120'或儲存模組120''可以是封裝件、裝置晶粒及/或類似物。處理器封裝件105與儲存模組120、儲存模組120'或儲存模組120''一起可隨後鋸切成多個個別的封裝件，且隨後封裝件中的一個安裝到封裝基板130上以形成半導體封裝100b。在其它實施例中，處理器封裝件105首先可鋸切成多個個別的封裝件，儲存模組120、儲存模組120'或儲存模組120''隨後安裝在封裝件中的一個上，且所得結構隨後安裝在封裝基板130上以形成半導體封裝100b。本揭露不限制方法的順序。相應地，半導體封裝100b包含處理器封裝件105以及包含記憶體陣列及快取記憶體陣列的垂直分散式儲存模組120、儲存模組120'或儲存模組120''。儲存模組120、儲存模組120'或儲存模組120''可經由處理器封裝件105的通孔113電性連接到封裝基板130。
基於以上論述，可看出本揭露提供各種優勢。然而，應理解，並非所有優勢都必須在本文中論述，且其它實施例可提供不同優勢，並且對於所有實施例並不要求特定優勢。
還可包含其它特徵及製程。舉例來說，可包含測試結構以輔助對3D封裝或3DIC裝置的校驗測試。測試結構可包含例如形成於重佈線層中或基板上的測試墊，所述基板允許對3D封裝或3DIC的測試、對探針及/或探針卡的使用以及類似操作。可對中間結構以及最終結構執行校驗測試。另外，本文中所揭露的結構及方法可與並有已知良好晶粒的中間校驗的測試方法結合使用以增加良率並降低成本。
根據本揭露的一些實施例，一種半導體封裝包含處理器晶粒、儲存模組以及封裝基板。儲存模組包含彼此堆疊的快取記憶體單元陣列及記憶體單元陣列且電性連接到處理器晶粒，其中快取記憶體單元陣列配置成保留儲存在記憶體單元陣列中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒及儲存模組。
根據本揭露的一些實施例，所述快取記憶體單元陣列的類型包括磁阻式隨機存取記憶體。
根據本揭露的一些實施例，所述記憶體單元陣列的類型包括非易失性記憶體、垂直與非型快閃記憶體、或非型快閃記憶體、動態隨機存取記憶體、快閃記憶體、相變記憶體、電阻性隨機存取記憶體。
根據本揭露的一些實施例，所述的半導體封裝更包括安置在所述封裝基板上的中介層，且所述處理器晶粒及所述儲存模組並排地安置在所述中介層的一側上。
根據本揭露的一些實施例，所述儲存模組安置在所述處理器晶粒上，且所述處理器晶粒安置在所述封裝基板上。
根據本揭露的一些實施例，所述儲存模組包括具有所述快取記憶體單元陣列的快取記憶體晶粒及堆疊在所述快取記憶體晶粒上方且具有所述記憶體單元陣列的記憶體晶粒。
根據本揭露的一些實施例，所述記憶體晶粒經由多個導電凸塊接合到所述快取記憶體晶粒。
根據本揭露的一些實施例，所述記憶體晶粒及所述快取記憶體晶粒通過多個微凸塊接合。
根據本揭露的一些實施例，所述儲存模組是記憶體晶粒，且所述記憶體單元陣列包括垂直堆疊式記憶體單元陣列。
根據本揭露的一些實施例，所述處理器晶粒包括延伸穿過所述處理器晶粒且將所述儲存模組及所述封裝基板電性連接的多個通孔。
根據本揭露的一些實施例，所述的半導體封裝更包括至少側向地包封所述處理器晶粒的包封材料，且包括延伸穿過所述包封材料且將所述儲存模組及所述封裝基板電性連接的多個通孔。
根據本揭露的一些實施例，一種半導體封裝包含處理器晶粒、快取記憶體晶粒、記憶體晶粒以及封裝基板。快取記憶體晶粒包含MRAM快取記憶體單元陣列且電性連接到處理器晶粒。記憶體晶粒堆疊在快取記憶體晶粒上方且包含記憶體單元陣列，其中記憶體晶粒電性連接到快取記憶體晶粒及處理器晶粒，且快取記憶體晶粒配置成保留儲存在記憶體晶粒中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒、快取記憶體晶粒以及記憶體晶粒。
根據本揭露的一些實施例，所述的半導體封裝更包括安置在所述封裝基板上的中介層，且所述處理器晶粒與所述快取記憶體晶粒及所述記憶體晶粒的堆疊並排地安置在所述中介層上。
根據本揭露的一些實施例，所述快取記憶體晶粒及所述記憶體晶粒的堆疊安置在所述處理器晶粒上，且所述處理器晶粒安置在所述封裝基板上。
根據本揭露的一些實施例，所述快取記憶體晶粒更包括垂直地延伸穿過所述快取記憶體晶粒的基板且將所述快取記憶體晶粒及所述記憶體晶粒電性連接的基板通孔。
根據本揭露的一些實施例，一種半導體封裝包含處理器晶粒、記憶體晶粒以及封裝基板。記憶體晶粒電性連接到處理器晶粒且包含在基板上彼此堆疊的快取記憶體單元陣列及垂直堆疊式記憶體單元陣列，其中快取記憶體單元陣列配置成保留儲存在垂直堆疊式記憶體單元陣列中且由處理器晶粒頻繁地使用的資料的副本。封裝基板上安置有處理器晶粒及記憶體晶粒。
根據本揭露的一些實施例，所述快取記憶體單元陣列安置在所述基板與所述垂直堆疊式記憶體單元陣列之間。
根據本揭露的一些實施例，所述的半導體封裝更包括安置在所述封裝基板上的中介層，且所述處理器晶粒及所述記憶體晶粒並排地安置在所述中介層上。
根據本揭露的一些實施例，所述記憶體晶粒安置在所述處理器晶粒上，且所述處理器晶粒安置在所述封裝基板上。
根據本揭露的一些實施例，所述快取記憶體單元陣列的類型包括磁阻式隨機存取記憶體（MRAM）。
100、100a、100b:半導體封裝 101:包封處理器晶粒 105:處理器封裝件 106:絕緣層 110、110b、110b':處理器晶粒 112、112':半導體晶圓 113:通孔 114:第一佈線層 115:包封材料 116:第二佈線層 120、120'、120'':儲存模組 121''、1103、1221、1221'、1241:基板 122:快取記憶體晶粒 122'':第一配線工程結構 123'':基板工程結構 124:記憶體晶粒 124'':第二配線工程結構 126、140、150:導電凸塊 130:封裝基板 140:導電凸塊 145、155:底部填充物 150:導電凸塊 152:集成被動裝置 160:焊料球 170:中介層 1061:開口 1101:導電通孔 1102、1102'、1142:介電層 1141:第一互連件 1161:第二互連件 1162:凸塊墊 1222、1242:基板工程 1223、1243:配線工程 1224、1224':基板通孔 1224a、1227a:絕緣材料 1225:快取記憶體單元 1226:背側絕緣膜 1227、1244:接合墊 1228:電極墊 1229:鈍化膜 1245:記憶體單元 A1:黏合層 C1:載體 S1:主動表面 S2:背表面
當結合附圖閱讀時從以下詳細描述最好地理解本揭露的各方面。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為了論述清楚起見，可任意增大或減小各種特徵的尺寸。 圖1示出根據本揭露的一些示例性實施例的半導體封裝的橫截面圖。 圖2到圖7示出在根據本揭露的一些示例性實施例的半導體封裝的製造中的中間階段的橫截面圖。 圖8到圖10示出在根據本揭露的一些示例性實施例的半導體封裝的製造中的中間階段的橫截面圖。 圖11示出根據本揭露的一些示例性實施例的半導體封裝的儲存模組的橫截面圖。 圖12示出根據本揭露的一些示例性實施例的半導體封裝的儲存模組的橫截面圖。 圖13示出根據本揭露的一些示例性實施例的半導體封裝的框圖。 圖14示出根據本揭露的一些示例性實施例的半導體封裝的橫截面圖。 圖15到圖22示出在根據本揭露的一些示例性實施例的半導體封裝的製造中的中間階段的橫截面圖。
100:半導體封裝
110:處理器晶粒
113:通孔
120:儲存模組
122:快取記憶體晶粒
124:記憶體晶粒
130:封裝基板
140:導電凸塊
150:導電凸塊
160:焊料球

Claims (1)

  1. 一種半導體封裝，包括： 處理器晶粒； 儲存模組，包括彼此堆疊的快取記憶體單元陣列及記憶體單元陣列且電性連接到所述處理器晶粒，其中所述快取記憶體單元陣列配置成保留儲存在所述記憶體單元陣列中且由所述處理器晶粒頻繁地使用的資料的副本；以及 封裝基板，在其上安置所述處理器晶粒及所述儲存模組。
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