CN113437058A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN113437058A
CN113437058A CN202110706979.4A CN202110706979A CN113437058A CN 113437058 A CN113437058 A CN 113437058A CN 202110706979 A CN202110706979 A CN 202110706979A CN 113437058 A CN113437058 A CN 113437058A
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China
Prior art keywords
die
memory
cache
processor
memory module
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Pending
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CN202110706979.4A
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English (en)
Inventor
吴昭谊
林佑明
杨世海
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113437058A publication Critical patent/CN113437058A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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Abstract

一种半导体封装件包含处理器管芯、存储模块以及封装衬底。存储模块包含彼此堆叠的高速缓存单元阵列和存储单元阵列且电连接到处理器管芯，其中高速缓存单元阵列配置成保留存储在存储单元阵列中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯和存储模块。

Description

半导体封装件
技术领域
本公开涉及一种半导体封装件。
背景技术
半导体行业已经由于多种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进而经历快速增长。主要来说，最小特征大小的反复减小已经带来集成密度的改进，这允许将更多组件集成到给定区域中。随着对于缩小的电子装置的需求增长，对于半导体管芯的更小且更创新的封装技术的需求已经出现。
发明内容
本公开是针对一种半导体封装件，其可提高系统的效率。
根据本公开的一些实施例，一种半导体封装件包含处理器管芯、存储模块以及封装衬底。存储模块包含彼此堆叠的高速缓存单元阵列和存储单元阵列且电连接到处理器管芯，其中高速缓存单元阵列配置成保留存储在存储单元阵列中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯和存储模块。
根据本公开的一些实施例，一种半导体封装件包含处理器管芯、高速缓存管芯、存储器管芯以及封装衬底。高速缓存管芯包含MRAM高速缓存单元阵列且电连接到处理器管芯。存储器管芯堆叠在高速缓存管芯上方且包含存储单元阵列，其中存储器管芯电连接到高速缓存管芯和处理器管芯，且高速缓存管芯配置成保留存储在存储器管芯中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯、高速缓存管芯以及存储器管芯。
根据本公开的一些实施例，一种半导体封装件包含处理器管芯、存储器管芯以及封装衬底。存储器管芯电连接到处理器管芯且包含在衬底上彼此堆叠的高速缓存单元阵列和竖直堆叠式存储单元阵列，其中高速缓存单元阵列配置成保留存储在竖直堆叠式存储单元阵列中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯和存储器管芯。
附图说明
当结合附图阅读时从以下详细描述最好地理解本公开的各方面。应注意，根据业界中的标准惯例，各种特征未按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各种特征的尺寸。
图1示出根据本公开的一些示例性实施例的半导体封装件的横截面图。
图2到图7示出在根据本公开的一些示例性实施例的半导体封装件的制造中的中间阶段的横截面图。
图8到图10示出在根据本公开的一些示例性实施例的半导体封装件的制造中的中间阶段的横截面图。
图11示出根据本公开的一些示例性实施例的半导体封装件的存储模块的横截面图。
图12示出根据本公开的一些示例性实施例的半导体封装件的存储模块的横截面图。
图13示出根据本公开的一些示例性实施例的半导体封装件的框图。
图14示出根据本公开的一些示例性实施例的半导体封装件的横截面图。
图15到图22示出在根据本公开的一些示例性实施例的半导体封装件的制造中的中间阶段的横截面图。
附图标号说明
100、100a、100b：半导体封装件；
101：包封处理器管芯；
105：处理器封装件；
106：绝缘层；
110、110b、110b'：处理器管芯；
112、112'：半导体晶片；
113：通孔；
114：第一布线层；
115：包封材料；
116：第二布线层；
120、120'、120”：存储模块；
121”、1103、1221、1221'、1241：衬底；
122：高速缓存管芯；
122”：第一布线工序结构；
123”：基板工序结构；
124：存储器管芯；
124”：第二布线工序结构；
126、140、150：导电凸块；
130：封装衬底；
145、155：底部填充物；
152：集成无源装置；
160：焊料球；
170：中介层；
1061：开口；
1101：导电通孔；
1102、1102'、1142：介电层；
1141：第一互连件；
1161：第二互连件；
1162：凸块墊；
1222、1242：基板工序；
1223、1243：布线工序；
1224、1224'：衬底通孔；
1224a、1227a：绝缘材料；
1225：高速缓存单元；
1226：背侧绝缘膜；
1227、1244：接合墊；
1228：电极墊；
1229：钝化膜；
1245：存储单元；
A1：粘合层；
C1：载体；
S1：有源表面；
S2：背表面。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例来简化本公开。当然，这些组件和布置仅为实例且并不意图为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或第二特征上的形成可包含第一特征与第二特征直接接触地形成的实施例，且还可包含额外特征可在第一特征与第二特征之间形成以使得第一特征与第二特征可不直接接触的实施例。另外，本公开可在各种实例中重复附图标号和/或字母。这种重复是出于简化和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
此外，为易于描述，可使用例如“在…下方”、“在…之下”、“下部”、“在…之上”、“上部”以及类似术语的空间相对术语，以描述如图中所示出的一个元件或特征相对于另一元件或特征的关系。除图中所描绘的定向外，空间相关术语意图涵盖装置在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词可同样相应地进行解释。
此外，为易于描述，可在本文中使用例如“第一”、“第二”、“第三”、“第四”以及类似术语的术语，以描述如图中所示出的类似或不同元件或特征，且可取决于存在次序或描述的上下文而互换地使用所述术语。
图1示出根据本公开的一些示例性实施例的半导体封装件的横截面图。本文中描述的是实施2.5D和/或3D存储器堆叠管芯系统的半导体封装件和制造方法。参考图1，例如，根据一个实施例所公开，半导体封装件100包含：处理器管芯110、电连接到所述处理器管芯110且包含一或多个存储器层的存储模块120；以及在其上安置处理器管芯110和存储模块120的封装衬底130。在一些实施例中，处理器管芯110可以是其中包含逻辑电路的逻辑装置管芯。在一些实施例中，处理器管芯110可包含以具有行和列的阵列设置的多个个别和单独的处理单元。在其它形式中，处理单元可放置在除处理单元的行和列以外的几何配置阵列中。处理单元中的每一个是任何类型的各种数据处理器。举例来说，处理管芯可包含中央处理单元(central processing unit；CPU)、数字信号处理器、特定图形处理器(graphics-specific processor)、微控制器单元(microcontroller unit；MCU)、通信处理器或任何其它类型的处理单元。此外，处理单元可以是相同类型的处理单元或可在处理器管芯110中的处理单元的类型之间不同。当实现功能上不同类型的处理单元时，由每一处理单元所占用的电路区域可不同。
在一些实施例中，处理器管芯110可包含处理单元和在处理单元外围的外部连接区域。相应地，例如焊料凸块的多个导电凸块150放置在外部连接区域处以提供处理器管芯110的进一步电连接。在这一实施例中，外部连接区域是处理器管芯110的从外部與处理器管芯110进行电连接的区域。在外部连接区域内的导电凸块150之下是接触墊和导电布线(图1不可见)，所述导电布线将导电凸块150连接到处理器管芯110内的预定电路。导电凸块150传达功率、数据、控制信号以及地址信号且提供获得对处理器管芯110的外部存取的方法。
根据本公开的一些实施例，图1示出半导体封装件100，其具有在下部层的处理器管芯110，例如片上系统(system on chip；SOC)，也称为“逻辑管芯”、功能性硅管芯或功能性半导体装置，且接着具有在上部层的存储模块120。进一步描绘封装衬底130，其经由例如球栅阵列(ball grid array；BGA)的多个导电凸块150与处理器管芯110和存储模块120接合，如所绘示。存储模块120的电互连经由例如硅通孔(through silicon via；TSV)、层间通孔(through interlayer via；TIV)或类似物的通孔113且随后经由导电凸块150电接合到封装衬底130且电接合到封装衬底130。此外，描绘了在衬底与另一板(例如主板、印刷电路板(printed circuit board；PCB)、母板等)之间提供电连接的焊料球160。本文中示出的半导体封装件100提供至少一个三维(three dimensional；3D)堆叠存储模块120(例如，高速缓存管芯122和存储器管芯124)，其紧密地集成到例如SOC管芯110的微处理器中。
在一些实施例中，处理器管芯110可包含存储器高速缓存(memory cache)，例如用于处理器管芯110的静态随机存取存储器(static random-access memory；SRAM)。通常，SRAM是静态随机存取存储器，且取决于接口的内部配置和差异而具有各种类型，例如异步静态随机存取存储器和同步静态随机存取存储器。任何静态随机存取存储器可用于处理器管芯110的存储器高速缓存。可根据特定应用使用其它存储器管芯配置。
图13示出根据本公开的一些示例性实施例的半导体封装件的框图。参考图1和图13，在一些实施例中，存储模块120电连接到处理器管芯110且包含彼此堆叠的高速缓存单元(例如，图13中所绘示的高速缓存单元1225)的阵列和存储单元(例如，图13中所绘示的存储单元1245)的阵列。高速缓存单元1225的阵列配置成保留存储在存储单元1245的阵列中且由处理器管芯110频繁地使用的数据的副本。在本公开实施例中，存储模块120包含具有高速缓存单元1225的阵列的高速缓存管芯122，以及堆叠在高速缓存管芯122上方且具有存储单元1245的阵列的存储器管芯124。
在一些实施例中，高速缓存单元1225中的每一个是半导体高速缓存(即，存储器)且可以是任何类型的高速缓存存储器。举例来说，处理器管芯110的高速缓存单元中的每一个可以是静态随机存取存储器(SRAM)、闪存存储器、磁阻式随机存取存储器(magnetoresistive random access memory；MRAM)、动态随机存取存储器(dynamicrandom access memory；DRAM)或任何其它类型的存储器。在本公开实施例中，举例来说，处理器管芯110的处理单元的类型可以是(包含)SRAM且高速缓存管芯122的高速缓存单元的类型可以是(包含)MRAM。换句话说，高速缓存管芯122包含MRAM高速缓存单元阵列。在一些实施例中，存储器管芯124的存储单元阵列的类型可包含非易失性存储器(non-volatilememory；NVM)、竖直与非型(NAND)闪存存储器、或非型(NOR)闪存存储器、动态随机存取存储器(DRAM)、闪存存储器、相变存储器(phase change memory；PCM)、电阻性随机存取存储器(resistive random access memory；RRAM)，其可为比高速缓存管芯122慢的数据存储。在一些实施例中，存储器管芯124可以是2D存储器装置或3D存储器装置。
在一些布置中，3D存储器装置可包含多个脊状堆叠(ridge-shaped stacks)，其是以由绝缘材料间隔开的多个条带式的半导体材料的形式来呈现。举例来说，半导体材料的条带是NAND串中的存储胞元的水平沟道。半导体材料的条带在脊形堆叠的侧面上具有侧表面。可耦合到行解码器的多个字线在多个脊形堆叠上方正交地延伸。存储器元件位于堆叠的表面与字线之间。存储器元件是可编程且非易失性的(如可编程电阻结构或电荷捕获结构)，或是可编程且易失性的。保形字线、存储器元件以及半导体条带的堆叠组合形成存储单元(胞元)的堆叠。
在一些实施例中，处理器管芯110的每一高速缓存单元可连接到高速缓存管芯122的高速缓存单元中特定指示的一个。应理解，可在高速缓存管芯122的高速缓存单元中的每一个之间提供一些物理分离和互连。高速缓存管芯122的高速缓存单元1225的阵列配置成用以存储数据使得可更快地服务这一数据的未来请求。存储在高速缓存单元中的数据可为较早计算的结果或存储在别处(例如，存储器管芯124的存储单元阵列)的数据的副本。高速缓存命中(cache hit)在可在高速缓存管芯122中找到所请求数据时发生，而高速缓存未命中(cache miss)在未在高速缓存管芯122中找到所请求数据时发生。高速缓存命中是通过从高速缓存单元读取数据来达成，这比重新计算结果或从更慢的数据存储(例如，存储器管芯124)读取更快。因此，可由高速缓存服务的请求越多，系统执行得越快。在一些实施例中，高速缓存管芯122(例如，MRAM)的高速缓存密度(容量)可大于处理器管芯110(例如，SRAM)的高速缓存密度(容量)，因此高速缓存管芯122可一次处理比处理器管芯110更多的数据，从而提高系统的效率。
在图1中所绘示的实施例中，存储模块120安置在处理器管芯110上，且处理器管芯110安置在封装衬底130上。在一些实施例中，处理器管芯110包含延伸穿过处理器管芯110且将存储模块120和封装衬底130电连接的多个通孔113。制造这类半导体封装件100的制造方法中的一种可包含以下步骤。
图2到图7示出在根据本公开的一些示例性实施例的半导体封装件的制造中的中间阶段的横截面图。参考图2，在一些实施例中，首先设置半导体晶片112'。在后续切割工艺之后，半导体晶片112'用于形成图1的处理器管芯110。半导体晶片112'包含有源表面S1和在其内部形成的多个(硅)通孔113。另外，半导体晶片112'的有源表面S1包含第一布线层114。第一布线层114包含第一互连件(例如，布线工序互连件)1141，且第一互连件1141连接到通孔113中的每一个的一端。
现在参考图2和图3，对半导体晶片112'的背表面(与有源表面S1相反)进行例如背面研磨处理的膜薄化处理以暴露通孔113中的每一个的另一端。通过此处进行的膜薄化处理，半导体晶片112'的厚度减小到接近于最终半导体晶片112的目标厚度的值。因此，研磨量是通过从晶片的初始厚度减去晶片的目标厚度所获得的差值。
随后，参考图4，第二布线层116形成于半导体晶片112的背表面S2上。第二布线层116中包含多个第二互连件1161，其连接到通孔113的另一端。在一些实施例中，第二布线层116可以是单个或多个金属层和介电层的堆叠。随后，多个凸块墊1162可在形成最上部介电层上且电连接到第二互连件1161。在镀覆工艺中，为了增加凸块墊1162与后续接合的导电凸块140之间的可焊性，可通过镀覆(plating)形成铜层和镍金堆叠层。金层可用作镀覆结构的表面层，其具有良好的润湿性，因此增加后续焊接工艺的良率。
参考图5，在一些实施例中，半导体晶片112随后锯切成多个个别处理器管芯110。随后，参考图6，在锯切半导体晶片112后，个别处理器管芯110中的一个以倒装芯片的方式接合到封装衬底130。处理器管芯110的通孔113经由导电凸块150电连接到封装衬底130。此外，在本公开实施例中，底部填充物155可填充在处理器管芯110与封装衬底130之间以围封导电凸块150。底部填充物155可在处理器管芯110接合到封装衬底130之前预先形成在封装衬底130上，或在处理器管芯110接合到封装衬底130之后填充在处理器管芯110与封装衬底130之间。
随后，如图7中所绘示，包含高速缓存管芯122和存储器管芯124的存储模块120以倒装芯片的方式接合到处理器管芯110。在一些实施例中，存储模块120经由导电凸块140以倒装芯片的方式接合到处理器管芯110。存储模块120经由对应的导电凸块140连接到凸块墊1162。此外，在本公开实施例中，底部填充物145选择地施加于存储模块120与第二布线层116之间，且底部填充物145围封导电凸块140。填充底部填充物145的步骤可在存储模块120以倒装芯片接合到处理器管芯110之前或之后执行。也就是说，底部填充物145可在存储模块120接合到处理器管芯110之前形成于第二布线层116上，或可在存储模块120接合到处理器管芯110之后填充在存储模块120与第二布线层116之间。此时，半导体封装件100的制造工艺可能大体上完成。
应注意，图4中所绘示的所得结构是处理器管芯110的半成品，其可在锯切工艺后以晶片或个别管芯的形式运输。因此，在替代实施例中，在锯切工艺之前，包含高速缓存管芯122和存储器管芯124的多个存储模块120可经由导电凸块140以倒装芯片的方式接合到图4中所绘示的半导体晶片112。类似地，底部填充物145任选地施加于存储模块120与第二布线层116之间，其中底部填充物145围封导电凸块140。在存储模块120以倒装芯片的方式接合到半导体晶片112之后，将半导体晶片112锯切成多个个别处理器管芯110。随后，处理器管芯110中的一个以倒装芯片的方式接合到封装衬底130。处理器管芯110的通孔113经由导电凸块150电连接到封装衬底130。此外，底部填充物155还可填充在处理器管芯110与封装衬底130之间以围封导电凸块150。本公开不限制方法的顺序。
图8到图10示出在根据本公开的一些示例性实施例的半导体封装件的制造中的中间阶段的横截面图。在一些实施例中，可通过将存储器管芯124和高速缓存管芯122堆叠在彼此的顶部上来形成存储模块120。以下描述示出制造存储模块120的可能的工艺中的一个。
图8示出高速缓存管芯122的半成品，其可能仍然呈晶片形式。如图8中所绘示，形成至少一个衬底通孔1224'。衬底通孔1224'可首先埋入高速缓存管芯122的衬底1221'中且连接到高速缓存管芯122的内埋布线(例如，高速缓存管芯122的基板工序1222的内埋布线)，所述内埋布线电连接到高速缓存单元1225的阵列。视需要在通孔1224上形成内埋布线。多层中间层内埋布线(例如，布线工序(back end of line；BEOL)1223)埋入中间层中。至少一个电极墊1228(例如，铝墊)在布线工序1223上方形成，且其上除了接垫开口的部分由最终钝化膜1229覆盖。至少一个导电凸块140(例如铜凸块电极)形成于电极墊1228上。在一些实施例中，焊料阻挡金属膜(例如，镍膜)可通过电镀或类似方法形成于导电凸块140上，且例如无铅焊料的焊料层(例如，锡银类焊料)可通过电镀或类似方法形成于焊料阻挡金属膜上。
随后，参考图8和图9，对衬底1221'的背表面进行例如背面研磨处理的膜薄化处理以暴露衬底通孔1224的另一端。通过此处进行的膜薄化处理，衬底1221的厚度减小到接近于高速缓存管芯122的最终衬底1221的目标厚度的值。相应地，衬底通孔1224竖直地延伸穿过高速缓存管芯122的衬底1221且电连接到高速缓存单元1225的阵列。随后，背侧接合墊1227可形成在衬底1221的背表面上方且电连接到衬底通孔1224。接合墊1227的形成可包含以下步骤，但不限于此。
在一些实施例中，可通过使用例如干式刻蚀(使用卤素气体作为气体系统)来轻微刻蚀衬底1221的背侧上的硅衬底1221来使衬底通孔1224从衬底1221的背表面突出少许。这种刻蚀是所谓的回蚀。随后，将作为背侧绝缘膜1226的树脂膜(例如，聚酰亚胺)应用到衬底1221的几乎整个背表面，接着通过CMP或回蚀来使其平面化且再次暴露衬底通孔1224的下端部分。随后，例如钛膜、铜膜、镍膜以及类似膜的金属膜通过例如溅镀形成于衬底1221的几乎整个背表面上。随后，通过例如湿式刻蚀来图案化所得金属膜，以形成接合墊1227。
随后，参考图10，图9中所绘示的所得结构附接到切割带上，所述切割带附接到切割框架上。在这种状态下，呈晶片形式的所得结构通过例如切割划分成多个个别高速缓存管芯122。随后，存储器管芯124通过例如焊料接合经由多个导电凸块126接合到高速缓存管芯122中的一个的背表面。在一些实施例中，高速缓存管芯122中的一个的背表面上的接合墊1227可通过例如焊料接合来接合到存储器管芯124的接合墊1244上的导电凸块126。通过这种接合，多个衬底通孔1224电连接到例如设置在存储器管芯124上的导电凸块126。在一些实施例中，导电凸块126可包含微凸块。存储器管芯124可以与高速缓存管芯122类似的方式形成，且包含衬底1241、形成于衬底1241上方的基板工序1242以及形成于基板工序1242上方的布线工序1243。
图11示出根据本公开的一些示例性实施例的半导体封装件的存储模块的横截面图。应注意，图11中所绘示的存储模块120'含有与图8到图10较早所公开的存储模块120相同或类似的许多特征。出于清楚和简单的目的，可省略相同或类似特征的细节描述，并且相同或类似附图标号指代相同或类似组件。如下描述图11中所绘示的存储模块120'与图8到图10较早所公开的存储模块120之间的主要差异。
参考图11，在一些实施例中，存储器管芯124的至少一个接合墊1244直接接合到高速缓存管芯122的至少一个接合墊1227。换句话说，存储器管芯124可通过混合接合技术接合到高速缓存管芯122。通常，混合接合包含存储器管芯124和高速缓存管芯122中的金属特征的直接金属对金属接合以及存储器管芯124中的绝缘材料与高速缓存管芯122中的绝缘材料的熔融接合。
直接接合可发生在存储器管芯124的接合墊1244与高速缓存管芯122的接合墊1227之间接合墊1244与接合墊1227的接合代表接墊对接墊混合接合。在替代实施例中，存储器管芯124与高速缓存管芯122之间的接合还可以是通孔对通孔混合接合、通孔对接垫混合接合、接垫对通孔混合接合或类似接合。存储器管芯124和高速缓存管芯122的接合垫是由例如铜、金、锡以及类似物或其合金的导电材料制成。存储器管芯124中的通孔或接合垫中的每一个的导电材料可与高速缓存管芯122中的导电材料相同或不同。
另外，高速缓存管芯122和存储器管芯124还分别包含绝缘材料1227a和绝缘材料1224a。绝缘材料1227a和绝缘材料1224a可以是氧化物、氮氧化物、介电质、聚合物等等。在一些实施例中，绝缘材料1227a可以与绝缘材料1224a是相同材料，而在其它实施例中，绝缘材料1227a可不同于绝缘材料1224a。
在一些实施例中，在混合接合工艺中，高速缓存管芯122的接合墊与存储器管芯124的接合墊对准且接触存储器管芯124的接合墊。高速缓存管芯122的绝缘材料1227也接触存储器管芯124的绝缘材料1224。随后，可执行退火以直接接合导电材料且将绝缘材料熔融接合在一起。退火导致金属在高速缓存管芯122的接墊和存储器管芯124的接墊中相互扩散以导致直接金属对金属接合。根据各种实施例，绝缘材料1227与绝缘材料1244之间的所得接合是绝缘体对绝缘体接合，其可以是无机对聚合物接合、聚合物对聚合物接合或无机对无机接合。
在一些实施例中，混合接合可使得接点能够具有精细间距。因此，混合接合可允许例如高速缓存管芯122和存储器管芯124的管芯具有高密度连接。此外，混合接合工艺允许两个结构之间的接合不包含焊接材料，且因此可能增大封装结构的可靠性和良率。又另外，因为在管芯之间不使用接点，所以混合接合工艺产生更薄的管芯堆叠。
图12示出根据本公开的一些示例性实施例的半导体封装件的存储模块的横截面图。应注意，图12中所绘示的存储模块120”含有与图8到图10较早所公开的存储模块120相同或类似的许多特征。出于清楚和简单的目的，可省略相同或类似特征的细节描述，并且相同或类似附图标号指代相同或类似组件。如下描述图12中所绘示的存储模块120”与图8到图10较早所公开的存储模块120之间的主要差异。
现在参考图12，在本公开实施例中，高速缓存管芯122和存储器管芯124可集成到一个存储器管芯120”中。换句话说，实际上，存储模块120”是包含在衬底121”上彼此堆叠的高速缓存单元1225的阵列和存储单元1245的阵列的存储器管芯120”。在一些实施例中，高速缓存单元1225的阵列安置于基板工序结构123”上方的第一布线工序结构122”中，且配置成保留存储在存储单元1245的阵列中且由处理器管芯110频繁地使用的数据的副本。在这一实施例中，存储单元1245的阵列安置于第二布线工序结构124”中，且存储单元1245的阵列包含竖直堆叠式存储单元阵列，即，3D存储单元阵列。也就是说，存储器管芯120”的类型是3D存储器。3D存储器包含3D非易失性存储器(NVM)、3D NAND闪存存储器或竖直NAND(Vertical NAND；V-NAND)闪存存储器、3D NOR闪存存储器等。
在一些实施例中，存储单元1245的阵列包含竖直堆叠式存储胞元，其分别包含使用氧化物半导体层作为沟道的薄膜晶体管。换句话说，存储单元1245包含氧化物半导体竖直沟道。在一个实施例中，氧化物半导体竖直沟道是金属氧化物半导体。氧化物半导体可具有晶体结构。对于竖直NAND(V-NAND)或3D NAND存储器，存储胞元竖直堆叠，且采用电荷捕获闪存架构。竖直层允许较大面积的位密度而不需要更小个别胞元。使用这类配置，存储单元1245的阵列能够彼此堆叠。因此，对于高速缓存管芯122和存储器管芯124集成到一个存储器管芯中的实施例，存储单元1245的类型应该为3D存储器。
另外，在一些实施例中，高速缓存单元1225的阵列可采用MOSFET沟道，其可包含基板工序结构(例如，基板工序结构123”)。相应地，在这一实施例中，存储单元1245形成于这类高速缓存单元1225上方(在形成高速缓存单元1225之后形成)。换句话说，这类高速缓存单元1225位于衬底121”(和基板工序结构123”)与存储单元1245的阵列之间。在不使用MOSFET沟道(例如，而是使用OTS选择器)的高速缓存单元1225的替代实施例中，3D存储单元1245的阵列可在形成高速缓存单元1225的阵列之前或之后形成。也就是说，存储单元1245还可安置在衬底121”(和基板工序结构123”)与高速缓存单元1225的阵列之间。在一些实施例中，高速缓存单元1225的类型是MRAM，但本公开不限于此。在另一实施例中，高速缓存单元1225的类型还可包含SRAM、(3D)NAND、(3D)NVM、(3D)NOR、DRAM、PCM、RRAM或类似类型。
参考图13，利用这类配置，处理器管芯110耦合到包含高速缓存单元1225的阵列和存储单元1245的阵列的存储模块120、存储模块120'、存储模块120”。相应地，当在高速缓存单元1225中找到所请求数据时，处理器管芯110从高速缓存单元1225读取数据，这比重新计算结果或从更慢的数据存储(例如，存储器管芯124)读取更快。当未在高速缓存单元1225中找到所请求数据时，处理器管芯110可从存储单元1245请求数据。处理器管芯110还可以配置成将数据写入到高速缓存单元1225和存储单元1245中，且存储单元1245可以配置成用以更新高速缓存单元1225中的数据。因此，通过存储模块120、存储模块120'、存储模块120”与高速缓存管芯122(或高速缓存单元1225的阵列)一起配置，更多的请求可由高速缓存单元1225来服务，从而改进系统性能。另外，高速缓存管芯122(例如，MRAM)的高速缓存密度(容量)大于处理器管芯110(例如，SRAM)的高速缓存密度(容量)，因此高速缓存管芯122可一次处理比处理器管芯110更多的数据，从而提高系统的效率。
图14示出根据本公开的一些示例性实施例的半导体封装件的横截面图。应注意，图14中所绘示的半导体封装件100a含有与图1到图7较早所公开的半导体封装件100相同或类似的许多特征。出于清楚和简单的目的，可省略相同或类似特征的细节描述，并且相同或类似附图标号指代相同或类似组件。如下描述半导体封装件100a与图1到图7较早所公开的半导体封装件100之间的主要差异。
现在参考图14，在一些实施例中，半导体封装件100a更包含安置在封装衬底130上的中介层(interposer)170，且处理器管芯110和存储模块120、存储模块120'或存储模块120”并排地安置在中介层170上。在本公开实施例中，存储模块可为以上示出的任何实施例，其意指存储模块的高速缓存管芯122和存储器管芯124可利用微凸块来接合、通过混合接合(hybrid bonding)来接合或集成到一个存储器管芯中。在本公开实施例中，处理器管芯110和存储模块120、存储模块120'或存储模块120”经由互连件(例如，导电凸块140)互连到中介层。这一示例性实施例中的互连件140是例如密集的管芯对管芯倒装芯片微凸块；然而，可使用其它类型的管芯对管芯精细间距互连件。
在一些实施例中，处理器管芯110和存储模块120、存储模块120'或存储模块120”经由管芯对管芯互连件140的一部分连接到中介层170的上表面，所述管芯对管芯互连件140可以是精细间距互连件或可以是常规的倒装芯片微凸块。管芯对管芯互连件140中的一些可耦合到其它较大互连件，所述较大互连件在本文中被称作“接点”(例如，导电凸块150)以免与管芯对管芯互连件(“互连件”)140混淆。举例来说，接点150可以使用例如硅通孔(“TSV”)的衬底通孔耦合到互连件140。在这一实施例中，接点150是微型球；然而，可使用其它类型的芯片对芯片大型互连件。另外，接点150大体上大于互连件140。由于互连件140的互连密度比接点150的互连密度大，因此可如先前描述提高IC的带宽。此外，在这一示例性实施例中，中介层170是硅中介层；然而，在其它实施例中，可使用其它类型的衬底或管芯平台。
图15到图22示出在根据本公开的一些示例性实施例的半导体封装件的制造中的中间阶段的横截面图。示例性实施例描绘用于形成半导体封装件100b的另一制造方法。应注意，图15到图22中所绘示的半导体封装件100b及其制造方法含有与图1到图7较早所公开的半导体封装件100及其制造方法相同或类似的许多特征。出于清楚和简单的目的，可省略相同或类似特征的细节描述，并且相同或类似附图标号指代相同或类似组件。示例性实施例的制造工艺可包含以下步骤。
参考图15，如图15中所绘示的至少一个处理器管芯110b'设置在载体C1上。在一些实施例中，粘合层A1可安置在载体C1上。在一些实施例中，载体C1可以是玻璃载体、陶瓷载体或类似物。粘合层A1可以是光热转换释放涂层(light to heat conversion releasecoating；LTHC)或类似物。在一些实施例中，绝缘层106可任选地安置在载体C1上。另外，多个通孔(导电柱)113设置于载体C1上，且通孔113可包围其中安置有处理器管芯110b'的装置区域。通孔113可在安置处理器管芯110b'之前或之后设置于载体C1上。本公开并不限于此。在一些实施例中，处理器管芯110b'可以是其中包含逻辑电路的逻辑装置管芯。举例来说，处理管芯可包含中央处理单元(CPU)、数字信号处理器、特定图形处理器、微控制器单元(MCU)、通信处理器或任何其它类型的处理单元。此外，处理单元可以是相同类型的处理单元或可在处理器管芯110b'中的处理单元的类型之间不同。虽然示出一个处理器管芯110b'，但是更多管芯可放置在载体C1上方且彼此齐平。
在一些实施例中，载体C1可包含例如以阵列方式布置的多个管芯区域A1。相应地，通孔113可如图15中所示出形成为包围管芯区域A1中的每一个，且多个处理器管芯110b'可分别安置在管芯区域A1上，因此通孔113可包围处理器管芯110b'中的每一个。使用这种布置，可同时形成多个半导体封装件。出于简洁和清楚起见，图15到图22中示出半导体封装件中的一个的制造工艺。举例来说，图15中示出由一些通孔113包围的处理器管芯110b'中的一个。
在一些实施例中，通孔113可预先形成，且随后放置在载体C1上。在替代实施例中，通孔113可通过例如镀覆工艺形成。通孔113的镀覆可在放置处理器管芯110b'之前执行，且可包含在载体C1上方形成晶种层(未绘示)、形成并图案化光刻胶层(未绘示)以及镀覆晶种层的经由光刻胶层暴露的部分上的通孔113。可随后去除光刻胶层和晶种层的由光刻胶层覆盖的部分。通孔113的材料可包含铜、铝或类似物。相应地，通孔113的底端与处理器管芯110b'的背表面大体上齐平。
在一些示例性实施例中，多个导电通孔1101(例如，铜通孔)可形成于处理器管芯110b'的衬底1103上方的处理器管芯110b'的有源表面(例如，顶表面)上。在一些实施例中，介电层1102'可形成于处理器管芯110b'的有源表面(例如，顶表面)上，且可覆盖导电通孔1101的顶表面。在其它实施例中，介电层1102'的顶表面可与导电通孔1101的顶表面大体上齐平。替代地，可省略介电层1102'。在一些实施例中，通孔113的顶端可与导电通孔1101的顶表面大体上齐平。在其它实施例中，通孔113的顶端可大体上高于或低于导电通孔1101的顶表面。
随后，载体C1上的处理器管芯110b'和通孔113由包封材料115至少侧向地包封。换句话说，包封材料115设置在载体C1上方以至少侧向地包封通孔113和处理器管芯110b'。在一些实施例中，包封材料115填充处理器管芯110b'与通孔113之间的间隙。包封材料115可包含模制化合物、环氧树脂或树脂等。
在一些实施例中，包封材料115首先覆盖通孔113的顶端和介电层1102'的顶表面。随后，执行薄化工艺(可以是研磨工艺)以薄化包封材料115(以及介电层1102')，直到显露通孔113的顶端以及导电通孔1101的顶表面为止。所得结构绘示于图16中。由于薄化工艺，通孔113的顶端与导电通孔1101的顶表面大体上齐平，且与包封材料115的顶表面以及介电层1102的顶表面大体上齐平，如图16中所绘示。在整个描述中，包含如图16中所绘示的处理器管芯110、通孔113以及包封材料115的所得结构被称作包封处理器管芯101，其在工艺中可具有晶片形状。相应地，在包封处理器管芯101中，处理器管芯110安置于管芯区域处，通孔113延伸穿过管芯区域A1外部的包封处理器管芯101，且包封材料115侧向地包封处理器管芯110和通孔113。换句话说，包封材料115包封其中的处理器管芯110，且通孔113延伸穿过包封材料115。
接着，参考图17，重布线电路结构114形成于处理器管芯110b和包封材料115上方。重布线电路结构114电连接到处理器管芯110b和通孔113。在一些实施例中，重布线电路结构114形成于包封处理器管芯101上方以连接到处理器管芯110b的导电通孔以及通孔113。重布线电路结构114可通过例如以下形成：沉积导电层，图案化导电层以形成重布线电路1141，部分地覆盖重布线电路1141，以及填充重布线电路1141与介电层1142之间的间隙等。重布线电路1141的材料可包含金属或金属合金，其包含铝、铜、钨和/或其合金。介电层1142可由例如氧化物、氮化物、碳化物、碳氮化物、其组合的介电材料和/或其多层来形成。重布线电路1141形成于介电层1142中且电连接到处理器管芯110b和通孔113。
参考图18，接点(导电凸块)150中的至少一个安置在根据一些示例性实施例的重布线电路结构114上。在一些实施例中，至少一个集成无源装置(integrated passivedevice；IPD)152也可安置在重布线电路结构114上。接点150的形成可包含将焊料球放置在UBM层上(或重布线电路结构114上)，且随后回焊焊料球。在替代实施例中，接点150的形成可包含执行镀覆工艺以在重布线电路结构114上形成焊料区域，且随后回焊焊料区域。接点150还可包含导电柱，或具有焊料盖的导电柱，其也可通过镀覆形成。IPD 152可使用例如薄膜和光刻工艺的标准晶片制造技术来制造，且可经由例如倒装芯片接合或引线接合等来安装在重布线电路结构114上。
随后，参考图19，可去除载体C1。在一些实施例中，通过使粘合层A1失去或降低粘合力来从包封处理器管芯101和绝缘层106(如果存在)拆离载体C1。随后，粘合层A1与载体C1一起被去除。举例来说，粘合层A1可暴露于UV光，使得粘合层A1失去或降低粘合力，且因此可从包封处理器管芯101去除载体C1和粘合层A1。
在省略绝缘层106的实施例中，在去除载体C1之后，通孔113的底端显露。在示出的结构中，通孔113的底端与处理器管芯110b的底表面以及包封材料115的底表面齐平。可执行研磨工艺以轻微地研磨处理器管芯110b的背表面和通孔113的底端。替代地，可跳过研磨工艺。
参考图20，在具有绝缘层106的实施例中，可随后对绝缘层106执行图案化工艺以形成多个开口1061。开口1061分别位于通孔113上以显露通孔113的底端。在一些实施例中，开口1061可通过光刻工艺、激光钻孔工艺等形成。
参考图21，多个导电凸块140可形成在包封处理器管芯101上以电连接到通孔113。在一些实施例中，导电凸块140安置在绝缘层106的开口1061中以连接到通孔113。在一些实施例中，导电凸块140可包含微凸块或类似物。在整个描述中，包含如图21中所绘示的处理器管芯110b、通孔113、包封材料115以及重布线电路结构114的所得结构被称作处理器封装件105，其在工艺中可具有晶片形状。相应地，在处理器封装件105中，处理器管芯110b由延伸穿过包封材料115的通孔113包围，且包封材料115包封处理器管芯110b和通孔113。重布线电路结构114安置于处理器管芯110b和包封材料115上方。
随后，参考图22，存储模块120、存储模块120'或存储模块120”安置在处理器封装件105上且经由处理器封装件105的导电凸块140电连接到通孔113。存储模块120、存储模块120'或存储模块120”以存储模块120、存储模块120'或存储模块120”通过导电凸块140的方式安装在处理器封装件105上。在一些实施例中，存储模块120、存储模块120'或存储模块120”可以是封装件、装置管芯和/或类似物。处理器封装件105与存储模块120、存储模块120'或存储模块120”一起可随后锯切成多个个别封装件，且随后封装件中的一个安裝到封装衬底130上以形成半导体封装件100b。在其它实施例中，处理器封装件105首先可锯切成多个个别封装件，存储模块120、存储模块120'或存储模块120”随后安装在封装件中的一个上，且所得结构随后安装在封装衬底130上以形成半导体封装件100b。本公开不限制方法的顺序。相应地，半导体封装件100b包含处理器封装件105以及包含存储阵列和高速缓存阵列的竖直分散式存储模块120、存储模块120'或存储模块120”。存储模块120、存储模块120'或存储模块120”可经由处理器封装件105的通孔113电连接到封装衬底130。
基于以上论述，可看出本公开提供各种优势。然而，应理解，并非所有优势都必须在本文中论述，且其它实施例可提供不同优势，并且对于所有实施例并不要求特定优势。
还可包含其它特征和工艺。举例来说，可包含测试结构以辅助对3D封装或3DIC装置的校验测试。测试结构可包含例如形成于重布线层中或衬底上的测试墊，所述衬底允许对3D封装或3DIC的测试、对探针和/或探针卡的使用以及类似操作。可对中间结构以及最终结构执行校验测试。另外，本文中所公开的结构和方法可与并有已知良好管芯的中间校验的测试方法结合使用以增加良率并降低成本。
根据本公开的一些实施例，一种半导体封装件包含处理器管芯、存储模块以及封装衬底。存储模块包含彼此堆叠的高速缓存单元阵列和存储单元阵列且电连接到处理器管芯，其中高速缓存单元阵列配置成保留存储在存储单元阵列中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯和存储模块。
根据本公开的一些实施例，所述高速缓存单元阵列的类型包括磁阻式随机存取存储器。
根据本公开的一些实施例，所述存储单元阵列的类型包括非易失性存储器、竖直与非型闪存存储器、或非型闪存存储器、动态随机存取存储器、闪存存储器、相变存储器、电阻性随机存取存储器。
根据本公开的一些实施例，所述的半导体封装件更包括安置在所述封装衬底上的中介层，且所述处理器管芯和所述存储模块并排地安置在所述中介层的一侧上。
根据本公开的一些实施例，所述存储模块安置在所述处理器管芯上，且所述处理器管芯安置在所述封装衬底上。
根据本公开的一些实施例，所述存储模块包括具有所述高速缓存单元阵列的高速缓存管芯和堆叠在所述高速缓存管芯上方且具有所述存储单元阵列的存储器管芯。
根据本公开的一些实施例，所述存储器管芯经由多个导电凸块接合到所述高速缓存管芯。
根据本公开的一些实施例，所述存储器管芯和所述高速缓存管芯通过多个微凸块接合。
根据本公开的一些实施例，所述存储模块是存储器管芯，且所述存储单元阵列包括竖直堆叠式存储单元阵列。
根据本公开的一些实施例，所述处理器管芯包括延伸穿过所述处理器管芯且将所述存储模块和所述封装衬底电连接的多个通孔。
根据本公开的一些实施例，所述的半导体封装件更包括至少侧向地包封所述处理器管芯的包封材料，且包括延伸穿过所述包封材料且将所述存储模块和所述封装衬底电连接的多个通孔。
根据本公开的一些实施例，一种半导体封装件包含处理器管芯、高速缓存管芯、存储器管芯以及封装衬底。高速缓存管芯包含MRAM高速缓存单元阵列且电连接到处理器管芯。存储器管芯堆叠在高速缓存管芯上方且包含存储单元阵列，其中存储器管芯电连接到高速缓存管芯和处理器管芯，且高速缓存管芯配置成保留存储在存储器管芯中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯、高速缓存管芯以及存储器管芯。
根据本公开的一些实施例，所述的半导体封装件更包括安置在所述封装衬底上的中介层，且所述处理器管芯与所述高速缓存管芯和所述存储器管芯的堆叠并排地安置在所述中介层上。
根据本公开的一些实施例，所述高速缓存管芯和所述存储器管芯的堆叠安置在所述处理器管芯上，且所述处理器管芯安置在所述封装衬底上。
根据本公开的一些实施例，所述高速缓存管芯更包括竖直地延伸穿过所述高速缓存管芯的衬底且将所述高速缓存管芯和所述存储器管芯电连接的衬底通孔。
根据本公开的一些实施例，一种半导体封装件包含处理器管芯、存储器管芯以及封装衬底。存储器管芯电连接到处理器管芯且包含在衬底上彼此堆叠的高速缓存单元阵列和竖直堆叠式存储单元阵列，其中高速缓存单元阵列配置成保留存储在竖直堆叠式存储单元阵列中且由处理器管芯频繁地使用的数据的副本。封装衬底上安置有处理器管芯和存储器管芯。
根据本公开的一些实施例，所述高速缓存单元阵列安置在所述衬底与所述竖直堆叠式存储单元阵列之间。
根据本公开的一些实施例，所述的半导体封装件更包括安置在所述封装衬底上的中介层，且所述处理器管芯和所述存储器管芯并排地安置在所述中介层上。
根据本公开的一些实施例，所述存储器管芯安置在所述处理器管芯上，且所述处理器管芯安置在所述封装衬底上。
根据本公开的一些实施例，所述高速缓存单元阵列的类型包括磁阻式随机存取存储器(MRAM)。
前文概述若干实施例的特征，使得本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解，其可容易地将本公开用作设计或修改用于实现本文中所引入的实施例的相同目的和/或达成相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到，这类等效构造并不脱离本公开的精神和范围，且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代以及更改。

Claims (1)

1.一种半导体封装件，包括：
处理器管芯；
存储模块，包括彼此堆叠的高速缓存单元阵列和存储单元阵列且电连接到所述处理器管芯，其中所述高速缓存单元阵列配置成保留存储在所述存储单元阵列中且由所述处理器管芯频繁地使用的数据的副本；以及
封装衬底，在其上安置所述处理器管芯和所述存储模块。
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