CN111354686A - 电子封装件及其制法暨封装用基板及其制法 - Google Patents

电子封装件及其制法暨封装用基板及其制法 Download PDF

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Publication number
CN111354686A
CN111354686A CN201811569234.2A CN201811569234A CN111354686A CN 111354686 A CN111354686 A CN 111354686A CN 201811569234 A CN201811569234 A CN 201811569234A CN 111354686 A CN111354686 A CN 111354686A
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China
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metal structure
circuit
layer
circuit structure
conductive elements
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CN201811569234.2A
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CN111354686B (zh
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丁俊彰
张宏达
许习彰
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority to CN201811569234.2A priority Critical patent/CN111354686B/zh
Priority to US16/285,813 priority patent/US10903167B2/en
Publication of CN111354686A publication Critical patent/CN111354686A/zh
Priority to US17/125,195 priority patent/US11600571B2/en
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Abstract

一种电子封装件及其制法暨封装用基板及其制法，该电子封装件包括：具有相对的第一侧与第二侧的线路结构、设于该第一侧上的电子元件、形成于该第一侧上以包覆该电子元件的封装层、形成于该第二侧上的金属结构、以及形成于该金属结构上的多个导电元件，以通过将该多个导电元件形成于该金属结构上，而非直接形成于该线路结构上，以提升该导电元件与该线路结构之间的结合性，避免该多个导电元件发生脱落的问题。

Description

电子封装件及其制法暨封装用基板及其制法
技术领域
本发明有关一种半导体封装制程，尤指一种电子封装件及其制法暨封装用基板及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势，随此趋势，目前应用于芯片封装领域的技术包含有芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模组、或将芯片立体堆叠化整合为三维集成电路(3D IC)芯片堆叠技术等。
图1A至图1F为悉知半导体封装件1的制法的剖面示意图。
如图1A所示，提供一半导体结构，该半导体结构包含一玻璃板10、经由胶材100形成于该玻璃板10上的一线路部11、覆晶结合于该线路部11上的多个半导体芯片12、及形成于该线路部11与各该半导体芯片12之间的底胶13。
如图1B所示，形成一封装层14于该线路部11上以包覆各该半导体芯片12与该底胶13。
如图1C所示，移除部分该封装层14的顶部材质以外露出该半导体芯片12。
如图1D所示，移除该玻璃板10及胶材100，以外露该线路部11。
如图1E所示，形成一绝缘保护层17于该线路部11上，且该绝缘保护层17外露部分该线路部11，以结合多个焊锡球18于该线路部11上。
如图1F所示，沿如图1E所示的切割路径S进行切单制程，以获得多个半导体封装件1。
然而，悉知半导体封装件1的制法中，需透过胶材100以在该玻璃板10上形成该线路部11，故于移除该胶材100时，容易于该线路部11上残留构成该胶材100的多个颗粒，致使后续形成的焊锡球18与该线路部11之间的结合性差，导致该多个焊锡球18接置的可靠度下降而产生掉球问题。
此外，该多个焊锡球18的焊锡材也容易因该胶材100的颗粒而向外扩散，导致该多个焊锡球18之间发生短路。
因此，如何克服悉知技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述悉知技术的种种缺失，本发明提供一种电子封装件及其制法暨封装用基板及其制法，以提升导电元件与线路结构之间的结合性。
本发明的电子封装件，包括：一线路结构，其具有相对的第一侧与第二侧；至少一电子元件，其设于该线路结构的第一侧上；一封装层，其形成于该线路结构的第一侧上，以包覆该至少一电子元件；金属结构，其形成于该线路结构的第二侧上；以及多个导电元件，其形成于该金属结构上。
本发明又提供一种电子封装件的制法，包括：于承载件上经由结合层形成一具有相对的第一侧与第二侧的线路结构，且该线路结构以其第二侧结合该结合层；结合至少一电子元件于该线路结构的第一侧上；形成封装层于该线路结构的第一侧上，以包覆该至少一电子元件；移除该承载件及该结合层；形成金属结构于该线路结构的第二侧上；以及形成多个导电元件于该金属结构上。
本发明还提供一种封装用基板，包括：一线路结构，其具有相对的第一侧与第二侧；一金属结构，其形成于该线路结构的第二侧上；以及多个导电元件，其形成于该金属结构上。
本发明另提供一种封装用基板的制法，包括：于承载件上经由结合层形成一具有相对的第一侧与第二侧的线路结构，且该线路结构以其第二侧结合该结合层；移除该承载件及该结合层；形成金属结构于该线路结构的第二侧上；以及形成多个导电元件于该金属结构上。
前述的电子封装件的制法与封装用基板的制法中，形成该金属结构的方式为溅镀制程。
前述的电子封装件及其制法中，该封装层外露该电子元件的部分表面。
前述的电子封装件及其制法暨封装用基板及其制法中，该线路结构包含相互结合的绝缘层与线路层，且该电子元件电性连接该线路层。
前述的电子封装件及其制法暨封装用基板及其制法中，该线路结构的第二侧具有多个电性接触垫，且该金属结构仅设于该多个电性接触垫上。
前述的电子封装件及其制法暨封装用基板及其制法中，该金属结构例如为铜层。
前述的电子封装件及其制法暨封装用基板及其制法中，该金属结构电性连接该线路结构。
前述的电子封装件及其制法暨封装用基板及其制法中，该导电元件经由该金属结构电性连接该线路结构。
前述的电子封装件及其制法暨封装用基板及其制法中，复包括形成凸块底下金属部于该导电元件与该金属结构之间。
由上可知，本发明的电子封装件及其制法暨封装用基板及其制法中，主要经由先形成该金属结构于该线路结构上，再形成该多个导电元件于该金属结构上，以令该金属结构作为该线路结构与该导电元件之间讯号传递的介质，故相较于悉知技术，本发明的制法于移除该结合层后，即使于该线路结构上残留构成该结合层的多个颗粒，仍可由该金属结构覆盖该多个颗粒，使后续形成的导电元件能可靠地结合于该金属结构上，因而经由该金属结构能提升该导电元件与该线路结构之间的结合性。因此，本发明的制法能有效避免该多个导电元件发生掉球的问题，故能提升产品的品质。
此外，本发明通过该金属结构覆盖该结合层的残留颗粒，使该多个导电元件的材质不会因该多个残留颗粒而向外扩散，故相较于悉知技术，本发明的制法能有效避免该多个导电元件之间发生短路的问题。
附图说明
图1A至图1F为悉知半导体封装件的制法的剖面示意图。
图2A至图2G为本发明的电子封装件的制法的剖面示意图。
图2E’为图2E的局部放大剖面示意图。
图2G’为图2G的另一实施例的局部放大剖面示意图。
图3A至图3D为本发明的封装用基板的制法的剖面示意图。
图3D’为图3D的另一实施例。
符号说明
1 半导体封装件
10 玻璃板
100 胶材
11 线路部
12 半导体芯片
13,23 底胶
14,24 封装层
17 绝缘保护层
18 焊锡球
2 电子封装件
20 承载件
200 结合层
21,31 线路结构
21a,31a 第一侧
21b,31b 第二侧
210,310 绝缘层
211,311 线路层
212,312 电性接触垫
22 电子元件
22a 作用面
22b 非作用面
221 导电凸块
27 凸块底下金属部
28 金属结构
28’ 溅镀铜层
29 导电元件
3 封装用基板
S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一形成有线路结构21的承载件20，再结合多个(或至少一)电子元件22于该线路结构21上，且于该线路结构21与该电子元件22之间形成有底胶23。
在本实施例中，该承载件20为高分子有机物、玻璃、金属或半导体板材(如硅板)。
此外，该线路结构21为如具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，其定义有相对的第一侧21a与第二侧21b，并以其第二侧21b结合至该承载件20上，且该线路结构21包含相互结合的多个绝缘层210与多个线路层211，该线路层211于该第二侧21b形成有多个嵌埋于该绝缘层210中的电性接触垫212。例如，该线路结构21的制程可为扇出(fan out)型重布线路层(redistribution layer，简称RDL)的制程、一次成型双镶崁(Dual Damascene)结构的制程或其它制程。具体地，该一次成型双镶崁(Dual Damascene)结构的制程先形成氧化层与氮化层以作为绝缘层210，再蚀刻氧化层与氮化层以形成盲孔，接着以化学沉积、溅镀或电镀等方式形成钛层或铜层以作为导电层，之后电镀铜层以形成线路层211，最后移除多余的导电层。
又，该承载件20可经由一如离形膜的结合层200结合该线路结构21的第二侧21b。例如，该结合层200可利用加热而移除；或者，当该承载件20为玻璃板(或可透光材质)时，该结合层200可利用雷射光照射而移除。
另外，该电子元件22为主动元件、被动元件或其二者的组合者，且该主动元件例如为半导体芯片，而该被动元件为例如电阻、电容及电感。例如，该电子元件22为主动元件，且其具有相对的作用面22a与非作用面22b，使该作用面22a经由多个如焊锡材料的导电凸块221以覆晶方式设于该线路结构21的第一侧21a的线路层211上并电性连接该线路层211，再以底胶23包覆多个导电凸块221；或者，该电子元件22可经由多个焊线(图略)以打线方式电性连接该线路层211；亦或，该电子元件22可直接接触该线路层211。然而，有关该电子元件22电性连接该线路层211的方式不限于上述。
如图2B所示，进行模压制程，即形成一封装层24于该线路结构21的第一侧21a上以包覆各该电子元件22与该底胶23。
如图2C所示，可依需求移除该封装层24的顶部材质，以外露该多个电子元件22的非作用面22b，从而供散热。
如图2D所示，移除该承载件20及该结合层200，以外露该线路结构21的第二侧21b。
在本实施例中，经由该结合层200分离该承载件20与该线路结构21。
如图2E所示，形成一金属结构28于该线路结构21的第二侧21b上，以令该金属结构28接触该线路结构21的绝缘层210与该电性接触垫212。
在本实施例中，该金属结构28为单一层金属层，如溅镀铜层28’于该线路结构21的第二侧21b上，如图2E’所示。
如图2F所示，形成如焊锡材料或金属凸块(如铜凸块)的多个导电元件29于该金属结构28上。
在本实施例中，以电镀或印刷方式形成该多个导电元件29。应可理解地，有关该导电元件29的构造及制作方式繁多，并不限于上述。
如图2G所示，将该导电元件29作为蚀刻用阻层，移除该金属结构28外露于该导电元件29的部分，以形成图案化的金属结构28(也就是该图案化的金属结构28的位置对应多个导电元件29的位置)，使该导电元件29经由该图案化的金属结构28(该金属结构28的剩余部分)电性连接该多个电性接触垫212。
在本实施例中，如图2G’所示，可依需求于该金属结构28(溅镀铜层28’)上形成凸块底下金属部(under bump metallurgy，简称UBM)27，以利于结合该导电元件29。
在后续制程中，可进行切单制程，以获得多个电子封装件2，使该电子封装件2可经由回焊该多个导电元件29以结合至一如电路板的电子装置(图略)上。
本发明的制法中，主要经由先形成该金属结构28，再形成该多个导电元件29，以令该金属结构28作为该线路层211(或该电性接触垫212)与该导电元件29之间讯号传递的介质，故相较于悉知技术，本发明的制法于移除该结合层200后，即使于该线路层211(或该电性接触垫212)及/或绝缘层210上残留该结合层200的多个颗粒，仍可由该金属结构28覆盖该多个颗粒，使后续形成的导电元件29能可靠地结合于该金属结构28上，因而经由该金属结构28能提升该导电元件29与该线路层211(或该电性接触垫212)之间的结合性。因此，本发明的制法能有效避免该多个导电元件29发生掉球的问题，故能提升产品的品质。
此外，本发明经由该金属结构28覆盖该结合层200的残留颗粒，使该多个导电元件29的材质不会因该多个残留颗粒而向外扩散，故相较于悉知技术，本发明的制法能有效避免该多个导电元件29之间发生短路的问题。
又，本发明的制法经由该导电元件29作为蚀刻用阻层，因而无需形成悉知绝缘保护层，以令该线路结构21的第二侧21b的绝缘层210表面外露于环境，即该金属结构28的周面上并无绝缘材，故本发明的制法能节省该电子封装件2的制作成本。
图3A至图3D为本发明的封装用基板3的制法的剖面示意图。
如图3A所示，提供一形成有线路结构31的承载件20。
在本实施例中，此外，该线路结构31为如具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，其定义有相对的第一侧31a与第二侧31b，并以其第二侧31b结合至该承载件20上，且该线路结构31包含相互结合的多个绝缘层310与一线路层311。例如，该线路结构31的制程可为扇出(fan out)型重布线路层(redistribution layer，简称RDL)的制程、一次成型双镶崁(Dual Damascene)结构的制程或其它制程。具体地，该一次成型双镶崁(Dual Damascene)结构的制程先形成氧化层与氮化层以作为绝缘层310，再蚀刻氧化层与氮化层以形成盲孔，接着以化学沉积、溅镀或电镀等方式形成钛层或铜层以作为导电层，之后电镀铜层以形成线路层311，最后移除多余的导电层。
又，该承载件20可经由一如离形膜的结合层200结合该线路结构31的第二侧31b。
如图3B所示，移除该承载件20及该结合层200，以外露该线路结构31的第二侧31b，使该线路层311外露于该第二侧31b的部分作为电性接触垫312，如导电盲孔的端面。
在本实施例中，经由该结合层200分离该承载件20与该线路结构31。
如图3C所示，形成一金属结构28于该线路结构31的第二侧31b上，以令该金属结构28接触该线路结构31的绝缘层310与该电性接触垫312。接着，形成如焊锡材料或金属凸块(如铜凸块)的多个导电元件29于该金属结构28上。
在本实施例中，该金属结构28为单一层金属层，如溅镀铜层28’于该线路结构31的第二侧31b上，如图3D’所示。
再者，以电镀或印刷方式形成该多个导电元件29。
如图3D所示，将该导电元件29作为蚀刻用阻层，移除该金属结构28外露于该导电元件29的部分，以形成图案化的金属结构28(也就是该图案化的金属结构28的位置对应多个导电元件29的位置)，使该导电元件29经由该图案化的金属结构28(该金属结构28的剩余部分)电性连接该多个电性接触垫312。
在本实施例中，如图3D’所示，可依需求于该金属结构28(溅镀铜层28’)上形成凸块底下金属部(under bump metallurgy，简称UBM)27，以利于结合该导电元件29。
在后续制程中，可进行切单制程，以获得多个封装基板3。
本发明的制法中，主要经由先形成该金属结构28，再形成该多个导电元件29，以令该金属结构28作为该线路层311(或该电性接触垫312)与该导电元件29之间讯号传递的介质，故相较于悉知技术，本发明的制法于移除该结合层200后，即使于该线路层311(或该电性接触垫312)及/或绝缘层310上残留该结合层200的多个颗粒，仍可由该金属结构28覆盖该多个颗粒，使后续形成的导电元件29能可靠地结合于该金属结构28上，因而经由该金属结构28能提升该导电元件29与该线路层311(或该电性接触垫312)之间的结合性。因此，本发明的制法能有效避免该多个导电元件29发生掉球的问题，故能提升产品的品质。
此外，本发明经由该金属结构28覆盖该结合层200的残留颗粒，使该多个导电元件29的材质不会因该多个残留颗粒而向外扩散，故相较于悉知技术，本发明的制法能有效避免该多个导电元件29之间发生短路的问题。
又，本发明的制法经由该导电元件29作为蚀刻用阻层，因而无需形成悉知绝缘保护层，以令该线路结构31的第二侧31b的绝缘层310表面外露于环境，即该金属结构28的周面上并无绝缘材，故本发明的制法能节省该封装用基板3的制作成本。
本发明提供一种电子封装件2，包括：一具有相对的第一侧21a与第二侧21b的线路结构21、设于该线路结构21的第一侧21a上的多个电子元件22、一设于该线路结构21的第一侧21a上以包覆该电子元件22的封装层24、一设于该线路结构21的第二侧21b上的金属结构28、以及多个设于该金属结构28上的导电元件29。
所述的线路结构21包含相互结合的多个绝缘层210与多个线路层211，使该电子元件22电性连接该线路层211，且该线路结构21的第二侧21b具有多个嵌埋于该绝缘层210中的电性接触垫212。
所述的电子元件22具有相对的作用面22a与非作用面22b，并以其作用面22a电性连接该线路层211。
所述的金属结构28仅设于该电性接触垫212上。
在一实施例中，该封装层24外露该电子元件22的非作用面22b。
在一实施例中，该金属结构28为铜层。
在一实施例中，该金属结构28电性连接该线路结构21的电性接触垫212。
在一实施例中，该导电元件29经由该金属结构28电性连接该线路结构21的电性接触垫212。
在一实施例中，所述的电子封装件2还包括一凸块底下金属部27，其设于该导电元件29与该金属结构28之间。
本发明还提供一种封装用基板3，包括：一具有相对的第一侧21a,31a与第二侧21b,31b的线路结构21,31、一设于该线路结构21,31的第二侧21b,31b上的金属结构28、以及多个设于该金属结构28上的导电元件29。
所述的线路结构21,31包含相互结合的多个绝缘层210,310与多个线路层211,311，且该线路结构21,31的第二侧21b,31b具有多个电性接触垫212,312。
所述的金属结构28仅设于该电性接触垫212,312上。
在一实施例中，该金属结构28为铜层。
在一实施例中，该金属结构28电性连接该线路结构21,31的电性接触垫212,312。
在一实施例中，该导电元件29经由该金属结构28电性连接该线路结构21,31的电性接触垫212,312。
在一实施例中，所述的封装用基板3还包括一凸块底下金属部27，其设于该导电元件29与该金属结构28之间。
综上所述，本发明的电子封装件及其制法暨封装用基板及其制法，通过将该多个导电元件形成于该金属结构上，而非直接形成于该电性接触垫上，故相较于悉知技术，本发明的导电元件能可靠地结合于该金属结构上，因而能提升该导电元件与该线路结构之间的结合性，以避免该多个导电元件发生掉球的问题，进而能提升产品的品质。
此外，经由该金属结构覆盖该结合层的残留颗粒，使该多个导电元件的材质不会因该多个残留颗粒而向外扩散，故能有效避免该多个导电元件之间发生短路的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (32)

1.一种电子封装件，其特征在于，包括：
一线路结构，其具有相对的第一侧与第二侧；
至少一电子元件，其设于该线路结构的第一侧上；
一封装层，其形成于该线路结构的第一侧上，以包覆该至少一电子元件；
一金属结构，其形成于该线路结构的第二侧上；以及
多个导电元件，其形成于该金属结构上。
2.根据权利要求1所述的电子封装件，其特征在于，该线路结构包含相互结合的绝缘层与线路层，且该至少一电子元件电性连接该线路层。
3.根据权利要求1所述的电子封装件，其特征在于，该线路结构的第二侧具有多个电性接触垫，且该金属结构仅形成于该多个电性接触垫上。
4.根据权利要求1所述的电子封装件，其特征在于，该封装层外露该至少一电子元件的部分表面。
5.根据权利要求1所述的电子封装件，其特征在于，该金属结构为铜层。
6.根据权利要求1所述的电子封装件，其特征在于，该金属结构电性连接该线路结构。
7.根据权利要求1所述的电子封装件，其特征在于，该多个导电元件经由该金属结构电性连接该线路结构。
8.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括凸块底下金属部，其设于该多个导电元件与该金属结构之间。
9.一种电子封装件的制法，其特征在于，包括：
于承载件上经由结合层形成一具有相对的第一侧与第二侧的线路结构，且该线路结构以其第二侧结合该结合层；
结合至少一电子元件于该线路结构的第一侧上；
形成封装层于该线路结构的第一侧上，以包覆该至少一电子元件；
移除该承载件及该结合层；
形成金属结构于该线路结构的第二侧上；以及
形成多个导电元件于该金属结构上。
10.根据权利要求9所述的电子封装件的制法，其特征在于，该线路结构包含相互结合的绝缘层与线路层，且该至少一电子元件电性连接该线路层。
11.根据权利要求9所述的电子封装件的制法，其特征在于，该线路结构的第二侧具有多个电性接触垫，且该金属结构仅形成于该多个电性接触垫上。
12.根据权利要求9所述的电子封装件的制法，其特征在于，该封装层外露该至少一电子元件的部分表面。
13.根据权利要求9所述的电子封装件的制法，其特征在于，该金属结构为铜层。
14.根据权利要求9所述的电子封装件的制法，其特征在于，该金属结构电性连接该线路结构。
15.根据权利要求9所述的电子封装件的制法，其特征在于，该多个导电元件经由该金属结构电性连接该线路结构。
16.根据权利要求9所述的电子封装件的制法，其特征在于，该制法还包括形成凸块底下金属部于该多个导电元件与该金属结构之间。
17.根据权利要求9所述的电子封装件的制法，其特征在于，形成该金属结构的方式为溅镀制程。
18.一种封装用基板，其特征在于，包括：
一线路结构，其具有相对的第一侧与第二侧；
一金属结构，其形成于该线路结构的第二侧上；以及
多个导电元件，其形成于该金属结构上。
19.根据权利要求18所述的封装用基板，其特征在于，该线路结构包含相互结合的绝缘层与线路层。
20.根据权利要求18所述的封装用基板，其特征在于，该线路结构的第二侧具有多个电性接触垫，且该金属结构仅形成于该多个电性接触垫上。
21.根据权利要求20所述的封装用基板，其特征在于，该金属结构为铜层。
22.根据权利要求18所述的封装用基板，其特征在于，该金属结构电性连接该线路结构。
23.根据权利要求18所述的封装用基板，其特征在于，该多个导电元件经由该金属结构电性连接该线路结构。
24.根据权利要求18所述的封装用基板，其特征在于，该封装用基板还包括凸块底下金属部，其形成于该多个导电元件与该金属结构之间。
25.一种封装用基板的制法，其特征在于，包括：
于承载件上经由结合层形成一具有相对的第一侧与第二侧的线路结构，且该线路结构以其第二侧结合该结合层；
移除该承载件及该结合层；
形成金属结构于该线路结构的第二侧上；以及
形成多个导电元件于该金属结构上。
26.根据权利要求25所述的封装用基板的制法，其特征在于，该线路结构包含相互结合的绝缘层与线路层。
27.根据权利要求25所述的封装用基板的制法，其特征在于，该线路结构的第二侧具有多个电性接触垫，且该金属结构仅形成于该多个电性接触垫上。
28.根据权利要求25所述的封装用基板的制法，其特征在于，该金属结构为铜层。
29.根据权利要求25所述的封装用基板的制法，其特征在于，该金属结构电性连接该线路结构。
30.根据权利要求25所述的封装用基板的制法，其特征在于，该多个导电元件经由该金属结构电性连接该线路结构。
31.根据权利要求25所述的封装用基板的制法，其特征在于，该制法还包括形成凸块底下金属部于该多个导电元件与该金属结构之间。
32.根据权利要求25所述的封装用基板的制法，其特征在于，形成该金属结构的方式为溅镀制程。
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