TWI791818B - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
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- TWI791818B TWI791818B TW108113297A TW108113297A TWI791818B TW I791818 B TWI791818 B TW I791818B TW 108113297 A TW108113297 A TW 108113297A TW 108113297 A TW108113297 A TW 108113297A TW I791818 B TWI791818 B TW I791818B
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Abstract
本發明是有關於一種半導體封裝,所述半導體封裝包括:
第一半導體晶片,具有第一表面及第二表面且包括貫通孔,所述第一表面上配置有第一連接墊,所述第二表面上配置有第二連接墊,所述貫通孔連接至所述第二連接墊;連接結構,配置於所述第一表面上且包括第一重佈線層;第二重佈線層,配置於所述第二表面上;以及第二半導體晶片,配置於所述連接結構上。所述第一連接墊,連接至所述第一重佈線層的訊號圖案,且所述第二連接墊連接至所述第二重佈線層的電源圖案及接地圖案中的至少一者。
Description
[相關申請案的交叉引用]
本申請案主張2019年2月15日在韓國智慧財產局中申請的韓國專利申請案第10-2019-0017872號的優先權的權益,所述韓國專利申請案的揭露內容以全文引用的方式併入本文中。
本發明是有關於一種半導體封裝,且具體而言,是有關於一種扇出型半導體封裝(fan-out semiconductor package)。
隨著智慧型電子裝置近來的發展,越來越需要在此種智慧型電子裝置中所使用的組件滿足更高級的效能需要。舉例而言,近年來,作為智慧型電子裝置的核心組件中的一者,應用處理器(application processor,AP)的效能規格已有大幅提升。改善應用處理器的效能的諸多方法中的一者涉及按功能對應用處理器進行劃分。舉例而言,應用處理器可藉由以下方式來製造:按功能對晶粒進行劃分,且藉由適合於晶粒的特性的最佳製程將經劃分晶粒配置並封裝成半導體晶片,且如此製造而成的應用處理器可達成相較於傳統單一應用處理器而言優越的效能。然而,實施此種應用處理器需要更高級的半導體封裝技術。在此背景下,
有必要開發一種能夠對多個經劃分半導體晶片進行封裝以具有最佳訊號特性及功率特性的封裝結構。
本發明的態樣旨在提供一種能夠對多個半導體晶片進行封裝以具有最佳訊號特性及功率特性的封裝結構。
根據本發明的態樣,一種半導體封裝包括貫通孔,所述貫通孔穿透半導體晶片,且所述半導體晶片的連接墊被配置成在彼此不同的方向上傳輸不同的訊號。
本發明的態樣旨在提供一種半導體封裝,所述半導體封裝包括:第一半導體晶片,具有第一表面及與所述第一表面相對的第二表面,且包括第一連接墊及第二連接墊以及貫通孔,所述第一連接墊及所述第二連接墊分別配置於所述第一表面及所述第二表面上,所述貫通孔連接至所述第二連接墊;連接結構,配置於所述第一半導體晶片的所述第一表面上,且包括電性連接至所述第一半導體晶片的所述第一連接墊的第一重佈線層;第二重佈線層,配置於所述第一半導體晶片的所述第二表面上,且電性連接至所述第一半導體晶片的所述第二連接墊;以及第二半導體晶片,配置於所述連接結構的第三表面上,所述連接結構的所述第三表面與所述連接結構的上面配置有所述第一半導體晶片的第四表面相對。所述第二半導體晶片的上面配置有所述第二半導體晶片的第三連接墊的表面面對所述連接結構的所述第四表面。所述第一半導體晶片的所述第一連接墊連接至所述第一重佈線層的訊
號圖案,且所述第一半導體晶片的所述第二連接墊連接至所述第二重佈線層的電源圖案及接地圖案中的至少一者。
100A、100B、100C、100E、100F、1121:半導體封裝
100D:封裝/半導體封裝
110:框架
110H:貫穿孔
110Ha:孔洞
111a:絕緣層/第一絕緣層
111b:絕緣層/第二絕緣層
111c:絕緣層/第三絕緣層
112a:配線層/第一配線層
112b:配線層/第二配線層
112bM:終止元件層
112c:配線層/第三配線層
112d:配線層/第四配線層
113a:配線/通孔層/第一配線/通孔層
113b:配線/通孔層/第二配線/通孔層
113c:配線/通孔層/第三配線層/第三配線/通孔層
115:金屬層
117:連接部件
120:第一半導體晶片
120B、161B、162B:電性連接凸塊
120r:底部填充樹脂
120s、170s、172s:低熔點金屬
121:本體部分
122:第一連接墊
123:第二連接墊
125:貫通孔
130、130a、2130:包封體
131、141、2141、2241:絕緣層
132:第二重佈線層
133:連接通孔/第二連接通孔
140、2140、2240:連接結構
142:重佈線層/第一重佈線層
143:第一連接通孔
150:第一鈍化層
161:第二半導體晶片
161P:第三連接墊
161r、162r、2280:底部填充樹脂
161s、162s:低熔點金屬構件
162:第三半導體晶片
162P:第四連接墊
170、171、172:被動組件
180:第二鈍化層
190:電性連接金屬
191、2290:模製材料
1000:電子裝置
1010、2500:主板
1020:晶片相關組件
1030:網路相關組件
1040:其他組件
1050:照相機模組
1060:天線
1070:顯示器裝置
1080:電池
1090:訊號線
1100:智慧型電話
1101、2121、2221:本體
1110:印刷電路板
1120:組件
1130:照相機
2100:扇出型半導體封裝
2120、2220:半導體晶片
2122、2222:連接墊
2142:重佈線層
2143、2243:通孔
2160、2260:凸塊下金屬層
2170、2270:焊球
2200:扇入型半導體封裝
2223、2150、2250:鈍化層
2242:配線圖案
2243h:通孔孔洞
2251:開口
2301、2302:中介基板
I-I':線
結合附圖閱讀以下詳細說明,將更清楚地理解本發明的以上及其他態樣、特徵及優點,在附圖中:圖1為示意性地示出電子裝置系統的實例的方塊圖。
圖2為示意性地示出電子裝置的實例的立體圖。
圖3A及圖3B是示意性地示出扇入型半導體封裝(fan-in semiconductor package)在封裝前及封裝後的剖面圖。
圖4為示意性地示出扇入型半導體封裝的封裝製程的剖面圖。
圖5為示意性地示出扇入型半導體封裝安裝於中介基板(interposer substrate)上且最終安裝於電子裝置的主板上之情形的剖面圖。
圖6為示意性地示出扇入型半導體封裝嵌置於中介基板中且最終安裝於電子裝置的主板上之情形的剖面圖。
圖7為扇出型半導體封裝的剖面示意圖。
圖8為示意性地示出安裝於電子裝置的主板上的扇出型半導體封裝的剖面圖。
圖9為示意性地示出半導體封裝的實例的剖面圖。
圖10為沿圖9所示線I-I'截取的圖9所示半導體封裝的平面圖。
圖11為示意性地示出半導體封裝的另一實例的剖面圖。
圖12為示意性地示出半導體封裝的另一實例的剖面圖。
圖13為示意性地示出半導體封裝的另一實例的剖面圖。
圖14為示意性地示出半導體封裝的另一實例的剖面圖。
圖15為示意性地示出半導體封裝的另一實例的剖面圖。
在下文中,將參照附圖闡述本發明的例示性實施例。在附圖中,為清晰起見,可誇大或簡化各組件的形狀、尺寸等。
電子裝置
圖1為示意性地示出電子裝置系統的實例的方塊圖。
參照圖式,電子裝置1000中可容置主板1010。主板1010可包括物理連接至或電性連接至主板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件,以形成各種訊號線1090。
晶片相關組件1020可包括:記憶體晶片,例如揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory,DRAM))、非揮發性記憶體(例如唯讀記憶體(read only memory,ROM))、快閃記憶體等;應用處理器晶片,例如中央處理器(例如中央處理單元(central processing unit,CPU))、圖形處理器(例如圖形處理單元(graphics processing unit,GPU))、數位訊號處理器、密碼處理器(cryptoprocessor)、微處理器、微控制器等;以及邏輯晶片,例如類比至數位轉換器
(analog-to-digital converter,ADC)、應用專用積體電路(application-specific integrated circuit,ASIC)等。然而,晶片相關組件1020並非僅限於此,而是亦可包括其他類型的晶片相關組件。另外,該些晶片相關組件1020可與彼此組合。
網路相關組件1030可包括例如以下協定:無線保真(wireless fidelity,Wi-Fi)(電氣及電子工程師學會(Institute of Electrical And Electronics Engineers,IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access,WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution,LTE)、僅支援資料的演進(evolution data only,Ev-DO)、高速封包存取+(high speed packet access+,HSPA+)、高速下行封包存取+(high speed downlink packet access+,HSDPA+)、高速上行封包存取+(high speed uplink packet access+,HSUPA+)、增強型資料GSM環境(enhanced data GSM environment,EDGE)、全球行動通訊系統(global system for mobile communications,GSM)、全球定位系統(global positioning system,GPS)、通用封包無線電服務(general packet radio service,GPRS)、分碼多重存取(code division multiple access,CDMA)、分時多重存取(time division multiple access,TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications,DECT)、藍芽、3G協定、4G協定及5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而,網路相關組件1030並非僅限於此,而是亦可
包括各種其他無線標準或協定或者有線標準或協定。另外,網路相關組件1030可與以上所闡述的晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器(power inductor)、鐵氧體珠粒(ferrite beads)、低溫共燒陶瓷(low temperature co-fired ceramic,LTCC)、電磁干擾(electromagnetic interference,EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor,MLCC)等。然而,其他組件1040並非僅限於此,而是亦可包括用於各種其他目的的被動組件等。另外,其他組件1040可與以上所闡述的晶片相關組件1020或網路相關組件1030一起彼此組合。
視電子裝置1000的類型而定,電子裝置1000可包括可物理連接至及/或電性連接至主板1010的其他組件,或可不物理連接至及/或不電性連接至主板1010的其他組件。該些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存單元(例如硬碟驅動機)(圖中未示出)、光碟(compact disk,CD)驅動機(圖中未示出)、數位多功能光碟(digital versatile disk,DVD)驅動機(圖中未示出)等。然而,該些其他組件並非僅限於此,而是視電子裝置1000的類型而定亦可包括用於各種目的的
其他組件等。
電子裝置1000可為智慧型電話、個人數位助理(personal digital assistant,PDA)、數位攝影機、數位靜態照相機(digital still camera)、網路系統、電腦、監視器、平板個人電腦(tablet PC)、膝上型個人電腦、隨身型易網機個人電腦(netbook PC)、電視、視訊遊戲機(video game machine)、智慧型手錶、汽車組件等。然而,電子裝置1000並非僅限於此,而亦可為能夠處理資料的任何其他電子裝置。
圖2為示意性地示出電子裝置的實例的立體圖。
參照圖式,半導體封裝可如上所述應用於用於各種目的的各種電子裝置。舉例而言,印刷電路板(printed circuit board,PCB)1110容置於智慧型電話1100的本體1101內,且各種組件1120物理連接至及/或電性連接至印刷電路板1110。此外,例如照相機1130等其他組件亦容置於本體1101內,所述其他組件可物理連接至及/或電性連接至印刷電路板1110,或可不物理連接至及/或電性連接至印刷電路板1110。組件1120中的一些組件可為晶片相關組件,例如半導體封裝1121,但並非僅限於此。所述電子裝置不限於智慧型電話1100,而是可為如上所述的任何其他電子裝置。
半導體封裝
一般而言,在半導體晶片中整合有許多精密的電路。然而,半導體晶片自身不能充當已完成的半導體產品,乃因其易受
外部物理性或化學性影響所傷害。因此,半導體晶片不再以其裸露狀態被使用,而是經常以封裝狀態封裝於電子裝置等中且在電子裝置等中使用。
需要進行半導體封裝是因為在半導體晶片的電路與電子裝置的主板的電路之間存在電性連接方面的寬度差異。更具體而言,在半導體晶片的情形中,連接墊的尺寸及此種連接墊之間的間隙極為精細,而在用於電子裝置中的主板的情形中,組件安裝墊的尺寸及此種組件安裝墊之間的間隙在尺度上相較於半導體晶片而言顯著較大。因此,難以將半導體晶片直接安裝於此種主板上,且因此,一種能夠解決主板與半導體之間的此種不同電路寬度的封裝技術是必要的。
視半導體封裝的結構及預期用途而定,此種封裝技術所製作的半導體封裝可分類為扇入型半導體封裝或扇出型半導體封裝。
在下文中將參照圖式更詳細地闡述扇入型半導體封裝及扇出型半導體封裝。
扇入型半導體封裝
圖3A及圖3B為示意性地示出扇入型半導體封裝在封裝前及封裝後狀態的剖面圖。
圖4為示意性地示出扇入型半導體封裝的封裝製程的剖面圖。
參照圖式,半導體晶片2220可例如是處於裸露狀態下
的積體電路(integrated circuit,IC),半導體晶片2220包括:本體2221,含有矽(Si)、鍺(Ge)、砷化鎵(GaAs)等;連接墊2222,形成於本體2221的一個表面上且含有例如鋁(Al)等導電材料;以及鈍化層2223,其例如是氧化物膜、氮化物膜等,且形成於本體2221的一個表面上且被配置成覆蓋連接墊2222的至少部分。此處,由於連接墊2222極小,因此甚至難以將積體電路安裝於中級印刷電路板(PCB)上,更不用說安裝於電子裝置的主板上。
為解決此問題,可在半導體晶片2220上形成容置半導體晶片2220的尺寸的連接結構2240以對連接墊2222進行重佈線。可藉由以下步驟來形成連接結構2240:利用例如感光成像介電(photoimagable dielectric,PID)樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241,此後形成敞露連接墊2222的通孔孔洞2243h,並接著形成配線圖案2242及通孔2243。接下來,形成保護連接結構2240的鈍化層2250,形成開口2251,且形成凸塊下金屬層2260等。換言之,可藉由一系列製程來製作包括例如半導體晶片2220、連接結構2240、鈍化層2250及凸塊下金屬層2260的扇入型半導體封裝2200。
如上所述,扇入型半導體封裝是其中半導體晶片的所有連接墊(例如輸入/輸出(input/output,I/O)端子)均配置於半導體晶片內部的一種封裝形式,且扇入型半導體封裝具有優異的電性特性且可被廉價地製作。因此,諸多安裝於智慧型電話中的元件已以扇入型半導體封裝的形式製作。更具體而言,已開發出諸
多安裝於智慧型電話中的元件以在具有小尺寸的同時實施快速訊號傳遞。
然而,由於在扇入型半導體封裝中所有輸入/輸出端子皆需要配置於半導體晶片內部,因此扇入型半導體封裝具有顯著的空間限制。因此,難以將此結構應用於具有大量輸入/輸出端子的半導體晶片或具有緊湊尺寸的半導體晶片。再者,由於以上所述缺點,扇入型半導體封裝無法藉由直接安裝於電子裝置的主板上而在電子裝置的主板上使用,乃因即使當半導體晶片的輸入/輸出端子的尺寸及輸入/輸出端子之間的間隙藉由重佈線製程而增大時,半導體晶片的輸入/輸出端子的尺寸及輸入/輸出端子的間隙可能仍不足以允許扇入型半導體封裝直接安裝於電子裝置的主板上。
圖5為示意性地示出扇入型半導體封裝安裝於中介基板上且最終安裝於電子裝置的主板上之情形的剖面圖。
圖6為示意性地示出扇入型半導體封裝嵌置於中介基板中且最終安裝於電子裝置的主板上之情形的剖面圖。
參照圖式,在扇入型半導體封裝2200中,連接墊2222(即,半導體晶片2220的輸入/輸出端子)可經由中介基板2301重佈線,且扇入型半導體封裝2200可藉由安裝於中介基板2301上而最終安裝於電子裝置的主板2500上。在此種情形中,可藉由底部填充樹脂2280等來固定焊球2270等,且半導體晶片2220的外表面可以模製材料2290等覆蓋。作為另一選擇,扇入型半導體
封裝2200可嵌置於單獨的中介基板2302中,且在嵌置於中介基板2302中的同時,連接墊2222(即,半導體晶片2220的輸入/輸出端子)可經由中介基板2302重佈線,且接著扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。
如上所述,由於難以藉由將扇入型半導體封裝直接安裝於電子裝置的主板上來使用扇入型半導體封裝,因此扇入型半導體封裝可首先安裝於單獨的中介基板上,且接著藉由封裝製程而安裝於電子裝置的主板上,或者作為另一選擇,扇入型半導體封裝可在嵌置於中介基板中的同時安裝於電子裝置的主板上且在電子裝置的主板上使用。
扇出型半導體封裝
圖7為示意性地示出扇出型半導體封裝的剖面圖。
參照圖式,在扇出型半導體封裝2100中,半導體晶片2120的外側由包封體2130保護,且半導體晶片2120的連接墊2122藉由連接結構2140而甚至重佈線至半導體晶片2120的外側。此處,在連接結構2140上可進一步形成有鈍化層2150,且在鈍化層2150的開口中可進一步形成有凸塊下金屬層2160。在凸塊下金屬層2160上可進一步形成有焊球2170。半導體晶片2120可為包括本體2121、連接墊2122、鈍化膜(圖中未示出)等的積體電路。連接結構2140可包括絕緣層2141、形成於絕緣層2241上的重佈線層2142以及被配置成將連接墊2122、重佈線層2142等電性連接的通孔2143。
如上所述,扇出型半導體封裝可具有其中半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的連接構件進行重佈線並延伸至半導體晶片之外的形式。如上所述,在扇入型半導體封裝中,半導體晶片的所有輸入/輸出端子皆需要配置於半導體晶片內部。因此,當半導體晶片的尺寸減小時,球的尺寸及節距亦需要減小,藉此使得扇入型半導體封裝難以使用標準化球佈局(standardized ball layout)。另一方面,扇出型半導體封裝具有如上所述其中半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的內連線構件進行重佈線並配置於半導體晶片之外的形式。因此,即使當半導體晶片的尺寸減小時,扇出型半導體封裝仍可照樣使用標準化球佈局,而使得扇出型半導體封裝無須使用單獨的中介基板即可安裝於電子裝置的主板上,如下所述。
圖8為示意性地示出安裝於電子裝置的主板上的扇出型半導體封裝的剖面圖。
參照圖式,扇出型半導體封裝2100可藉由焊球2170等安裝於電子裝置的主板2500上。換言之,如上所述,扇出型半導體封裝2100包括連接結構2140,連接結構2140形成於半導體晶片2120上且能夠將連接墊2122重佈線至半導體晶片2120的尺寸之外的扇出區,進而使得標準化球佈局可照樣在扇出型半導體封裝2100中使用。因此,扇出型半導體封裝2100無需使用單獨的中介基板等即可安裝於電子裝置的主板2500上。
如上所述,由於扇出型半導體封裝無需使用單獨的中介
基板即可安裝於電子裝置的主板上,因此扇出型半導體封裝可具有較使用中介基板的扇入型半導體封裝的厚度小的厚度。因此,扇出型半導體封裝可小型化及薄化。另外,扇出型半導體封裝具有優異的熱特性及電性特性,進而使得扇出型半導體封裝尤其適宜用於行動產品。因此,扇出型半導體封裝可以較使用印刷電路板(PCB)的一般疊層封裝(package-on-package,POP)類型更緊湊的形式實施,且可解決因翹曲(warpage)現象出現而產生的問題。
同時,扇出型半導體封裝指代一種封裝技術,如上所述用於將半導體晶片安裝於電子裝置的主板等上且保護半導體晶片免受外部影響,且其與例如中介基板等印刷電路板(PCB)在概念上是不同的,印刷電路板亦具有與扇出型半導體封裝的尺度、目的等不同的尺度、目的等,且有扇入型半導體封裝嵌置於其中。
在下文中將參照圖式闡述一種能夠對多個半導體晶片進行封裝且具有最佳訊號特性及功率特性的封裝結構。
圖9為半導體封裝的實例的剖面示意圖。
圖10為沿圖9所示線I-I'截取的圖9所示半導體封裝的平面圖。
參照圖式,根據例示性實施例的半導體封裝100A包括:連接結構140,具有彼此相對的上表面與下表面;框架110,配置於連接結構140的下表面上且具有貫穿孔110H;第一半導體晶片120,在連接結構140的下表面上配置於貫穿孔110H中;包
封體130,配置於連接結構140的下表面上,覆蓋框架110及第一半導體晶片120中的每一者的至少部分,且填充貫穿孔110H的至少部分;第一鈍化層150,配置於連接結構140的上表面上;第二半導體晶片161及第三半導體晶片162,配置於第一鈍化層150上;模製材料191,配置於第一鈍化層150上且覆蓋第二半導體晶片161及第三半導體晶片162中的每一者的至少部分;第二重佈線層132,配置於框架110下面;第二鈍化層180,被配置成覆蓋第二重佈線層132;以及多個電性連接金屬190。
第一半導體晶片120包括本體部分121、第一連接墊122及第二連接墊123以及貫通孔125。第一半導體晶片120的上面配置有第一連接墊122的一個表面可為主動面,而與所述一個表面相對且上面配置有第二連接墊123的相對表面可為非主動面,但第一半導體晶片120並非僅限於此。具體而言,第二連接墊123可被配置成自第一半導體晶片120的非主動面突出,但並非僅限於此。貫通孔125連接至第二連接墊123,且藉由穿透第一半導體晶片120的本體部分121的至少部分而自第二連接墊123延伸至主動面或與所述主動面接近的區。舉例而言,貫通孔125可延伸以穿透整個第一半導體晶片120,或者可自第二連接墊123延伸以穿透被配置成與主動面接觸且上面配置有半導體裝置的主動層的至少部分。貫通孔125可電性連接至位於第一半導體晶片120內部的半導體裝置。在其中本體部分121由矽製成的情形中,貫通孔125可為矽貫通孔(through-silicon via,TSV)。
在第一半導體晶片120中,第一連接墊122電性連接至配置於第一連接墊122上方的連接結構140的第一重佈線層142。貫通孔125藉由第二連接墊123電性連接至配置於貫通孔125下面的第二重佈線層132。具體而言,第一連接墊122連接至第一重佈線層142的訊號圖案,且貫通孔125連接至第二重佈線層132的電源圖案及/或接地圖案。因此,在第一半導體晶片120中,訊號(例如,資料訊號)可經由第一連接墊122來傳輸及接收,且功率可經由貫通孔125來供應。
為改善作為智慧型電子裝置的核心組件中的一者的應用處理器的效能,可按功能對應用處理器進行劃分。舉例而言,應用處理器可藉由以下方式來製作:按功能對晶粒進行劃分,且根據晶粒的特性藉由最佳製程而將經劃分晶粒設計並封裝成半導體晶片,且如此製作而成的應用處理器可展現出相較於傳統單一應用處理器而言優越的效能。
在此背景下,在根據例示性實施例的半導體封裝100A中,能夠執行彼此不同的功能的第一半導體晶片120與第二半導體晶片161及第三半導體晶片162各自配置於包括一或多個第一重佈線層142的連接結構140的任一表面上,進而使得第一連接墊122與第二半導體晶片161的第三連接墊161P及第三半導體晶片162的第四連接墊162P被配置成彼此面對且使連接結構140配置於其間。第一半導體晶片120配置於連接結構140的下表面上,進而使得上面配置有第一連接墊122的主動面面對連接結構140
的下表面。第二半導體晶片161及第三半導體晶片162配置於連接結構140的上表面上,進而使得第二半導體晶片161的主動面及第三半導體晶片162的主動面面對連接結構140的上表面,第二半導體晶片161的主動面及第三半導體晶片162的主動面上分別配置有第三連接墊161P及第四連接墊162P。第二半導體晶片161及第三半導體晶片162可被配置成使得:當自平面圖觀察時,第二半導體晶片161及第三半導體晶片162中的每一者的至少部分在垂直方向上交疊第一半導體晶片120。第一半導體晶片120、第二半導體晶片161及第三半導體晶片162中的每一者可為構成應用處理器(AP)的功能的至少部分的晶片。換言之,第一半導體晶片120、第二半導體晶片161及第三半導體晶片162中的每一者可構成應用處理器的局部功能或整體功能。
如圖10中所示,第一連接墊122可被配置成大部分位於第一半導體晶片120的主動面上與第二半導體晶片161或第三半導體晶片162交疊的交疊區中。另一方面,貫通孔125及連接至貫通孔125的第二連接墊123配置於包括第一半導體晶片120的中心區的區中,同時,貫通孔125及第二連接墊123的至少部分可配置於第一半導體晶片120的不與第二半導體晶片161或第三半導體晶片162交疊的區中。第一連接墊122及第二連接墊123可被排列成當自平面圖觀察時不彼此交疊,但並非僅限於此。舉例而言,當在平面圖中觀察時,第一連接墊122及貫通孔125的列數及行數可經各式修改。
此處,第一連接墊122的部分於交疊區中藉由訊號圖案而在垂直方向上電性連接至第三連接墊161P及第四連接墊162P的部分。第一連接墊122的另一部分藉由第一重佈線層142及框架110電性連接至第二重佈線層132。第三連接墊161P及第四連接墊162P中的每一者的另一部分(大部分在不與第一半導體晶片120交疊的區中)可電性連接至第一重佈線層142的電源圖案及/或接地圖案。如上所述,藉由連接結構140的第一重佈線層142的訊號圖案以及連接至所述訊號圖案的第一連接通孔143,第一半導體晶片120與第二半導體晶片161及第三半導體晶片162可在垂直方向上進行連接且亦彼此進行訊號連接。因此,由於第一半導體晶片120、第二半導體晶片161及第三半導體晶片162可以最短距離連接至彼此,因此訊號特性可最佳化,且再者,由於第一半導體晶片120與電性連接金屬190可以最短距離連接至彼此,因此功率特性可最佳化。
在下文中將更詳細地闡述根據例示性實施例的半導體封裝100A中所包括的各個組件。
框架110包括呈貫穿孔形狀的貫穿孔110H。第一半導體晶片120配置於貫穿孔110H中,進而使得第一半導體晶片120的上面配置有第一連接墊122的表面面對連接結構140的下表面。此處,第一連接墊122可在不利用凸塊的情況下連接至連接結構140的第一連接通孔143。再者,框架110包括:第一絕緣層111a,被配置成接觸連接結構140的下表面;第一配線層112a,
被配置成接觸連接結構140的下表面且埋置於第一絕緣層111a的一個表面中;第二配線層112b,配置於第一絕緣層111a的另一表面上,第一絕緣層111a的所述另一表面與第一絕緣層111a的其中埋置有第一配線層112a的所述一個表面相對;第二絕緣層111b,配置成覆蓋第二配線層112b的至少部分;第三配線層112c,配置於第二絕緣層111b的一個表面上,第二絕緣層111b的所述一個表面與第二絕緣層111b的其中埋置有第二配線層112b的另一表面相對;第一配線/通孔層113a,被配置成穿透第一絕緣層111a以將第一配線層112a與第二配線層112b電性連接至彼此;以及第二配線/通孔層113b,穿透第二絕緣層111b以將第二配線層112b與第三配線層112c電性連接至彼此。框架110可充當支撐構件。
第一配線層112可凹陷至第一絕緣層111a中。換言之,第一絕緣層111a與連接結構140的下表面接觸的那側可相對於第一配線層112a與連接結構140接觸的那側具有台階(step)。此可防止包封材料在利用包封體130包封第一半導體晶片120及框架110時流出而污染第一配線層112a。第一配線層112a、第二配線層112b及第三配線層112c中的每一者的厚度可大於第一重佈線層142中的每一者的厚度。
由於第一配線層112a的一些接墊可在形成第一配線/通孔層113a的孔洞時充當終止元件,因此,若第一配線/通孔層113a中的每一者的連接通孔為錐形而使得連接通孔的上表面的寬度小於連接通孔的下表面的寬度,則在加工方面可為有利的。在此種
情形中,第一配線/通孔層113a的配線通孔可與第二配線層112b的圖案整合。相同地,由於第二配線層112b的一些接墊可在形成第二配線/通孔層113b的孔時充當終止元件,因此,若第二配線/通孔層113b的連接通孔為錘形而使得連接通孔的上表面的寬度小於連接通孔的下表面的寬度,則在加工方面可為有利的。在此種情形中,第二配線/通孔層113b的配線通孔可與第三配線層112c的接墊圖案整合。
對於第一絕緣層111a及第二絕緣層111b,可使用絕緣材料。在此種情形中,所述絕緣材料可為熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;或將熱固性樹脂、熱塑性樹脂等與無機填料一起浸入例如玻璃纖維等(玻璃布、玻璃纖維布等)的核心材料中的樹脂。舉例而言,可使用預浸體(prepreg)、味之素構成膜(Ajinomoto Build up Film,ABF)、FR-4、雙馬來醯亞胺三嗪(Bismaleimide Triazine,BT)等。
第一配線層112a、第二配線層112b及第三配線層112c可起到對第一半導體晶片120的第一連接墊122進行重佈線的作用,且可起到為配線/通孔層113a及113b提供接墊圖案以對半導體封裝100A的上部部分與下部部分進行連接的作用。第一配線層112a、第二配線層112b及第三配線層112c可由金屬材料形成。所述金屬材料的實例包括銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)及其合金。第一配線層112a、第二配線層112b及第三配線層112c可根據對應層的電路設計而
執行各種功能。舉例而言,第一配線層112a、第二配線層112b及第三配線層112c可包括接地(GrouND:GND)圖案、電源(PoWeR:PWR)圖案、訊號(Signal:S)圖案等。此處,訊號圖案包括各種訊號(例如資料訊號),不包括與電源等相關的接地圖案及電源圖案。
第一配線/通孔層113a與第二配線/通孔層113b被配置成將形成於不同水平高度處的第一配線層112a、第二配線層112b及第三配線層112c電性連接至彼此而在框架110內部形成電性路徑。另外,第一配線/通孔層113a及第二配線/通孔層113b在連接結構140與電性連接金屬190之間形成電性路徑。第一配線/通孔層113a及第二配線/通孔層113b可由金屬材料形成。第一配線/通孔層113a及第二配線/通孔層113b中的每一者可為被金屬材料完全填充的填充型通孔,或者可為其中金屬材料沿通孔孔洞的內壁形成的共形型通孔。此外,第一配線/通孔層113a及第二配線/通孔層113b中的每一者可具有錐形形狀。再者,第一配線/通孔層113a及第二配線/通孔層113b可與第一配線層112a、第二配線層112b及第三配線層112c的至少部分整合,但並非僅限於此。
第一半導體晶片120可為其中將大於數百至數百萬個裝置整合於單一晶片中的積體電路(IC)。舉例而言,第一半導體晶片120可為例如中央處理器(例如中央處理單元)、圖形處理器(例如圖形處理單元)、場域可程式閘陣列(field-programmable gate array,FPGA)、數位訊號處理器、加密處理器、微處理器、微控
制器等處理器晶片,且具體而言,第一半導體晶片120可為應用處理器(AP),但並非僅限於此。第一半導體晶片120可為形成應用處理器的局部功能的晶片,經劃分晶片的實例包括中央處理器(中央處理單元)、圖形處理器(圖形處理單元)、微處理器及/或微控制器等。作為另一選擇,第一半導體晶片120可為具有本文中所未揭露的功能的經劃分晶片。
第一半導體晶片120可利用主動晶圓來形成,且在此種情形中,可使用矽(Si)、鍺(Ge)、砷化鎵(GaAs)等作為用於形成本體部分121的基礎材料(base material)。本體部分121可具有形成於其中的各種半導體裝置及電路。第一連接墊122及第二連接墊123以及貫通孔125被配置成將第一半導體晶片120電性連接至其他組件,且可由例如鋁(Al)及銅(Cu)等導電材料形成,但並非僅限於此。在本體部分121中,可進一步形成有鈍化膜,所述鈍化膜暴露出第一連接墊122及第二連接墊123,其中所述鈍化膜可為氧化物膜、氮化物膜等,或者可為包括氧化物層及氮化物層的雙層。第一半導體晶片120可為裸晶粒(bare die),或者若有必要,則可為其中在上面配置有第一連接墊122的表面(即,主動面)上進一步形成有附加重佈線層的封裝晶粒(packaged die)。
包封體130可用於保護框架110、第一半導體晶片120等。包封體130的包封形式並不限於任何具體形式。舉例而言,包封體130可被配置成覆蓋上面配置有框架110及第一半導體晶
片120的第二連接墊123的表面,且可填充貫穿孔110H的至少部分。由於包封體130填充貫穿孔110H,因此,視構成包封體130的材料的具體類型而定,包封體130可充當黏合劑且同時減少翹曲(buckling)。
包封體130並不限於任何具體材料。舉例而言,包封體130可由絕緣材料形成,且所述絕緣材料的實例可為:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺樹脂;將熱固性樹脂、熱塑性樹脂等與無機填料一起浸入例如玻璃纖維等(玻璃布、玻璃纖維布等)的核心材料中的樹脂。舉例而言,可使用預浸體、味之素構成膜、FR-4、雙馬來醯亞胺三嗪等。若有必要,則可使用感光成像包封體(photoimagable encapsulant,PIE)樹脂。
連接結構140可對第一半導體晶片120的第一連接墊122、第二半導體晶片161的第三連接墊161P及第三半導體晶片162的第四連接墊162P進行重佈線。此外,連接結構140可根據第一連接墊122、第三連接墊161P及第四連接墊162P的功能將第一連接墊122、第三連接墊161P及第四連接墊162P電性連接至彼此。此外,連接結構140可根據第一連接墊122、第三連接墊161P及第四連接墊162P的功能將第一連接墊122、第三連接墊161P及第四連接墊162P電性連接至框架110的配線層112a、112b及112c。數十至數百萬個具有各種功能的第一連接墊122、第三連接墊161P及第四連接墊162P可藉由連接結構140進行重佈線。此外,第一連接墊122、第三連接墊161P及第四連接墊162P
可根據其各自的功能藉由電性連接金屬190進一步物理連接及/或電性連接至外部組件。
絕緣層141可由絕緣材料形成。除絕緣材料的前述實例以外,所述絕緣材料的實例亦包括感光性絕緣材料,例如感光成像介電樹脂。換言之,絕緣層141中的每一者可為感光性絕緣層。當絕緣層141具有感光性質時,絕緣層141可被更薄地製作而使得能夠更容易地實施第一連接通孔143的精密節距。絕緣層141中的每一者可為含有絕緣樹脂及無機填料的感光性絕緣層。當絕緣層141是以多層提供時,絕緣層141可視需要而為相同的材料或不同的材料。若絕緣層141是以多層提供,則絕緣層141可視需要而為相同的材料或不同的材料。以多層提供的絕緣層141可被加工成使得絕緣層141彼此整合,且兩個相鄰絕緣層141之間的邊界可為模糊的;然而,絕緣層141並非僅限於此。
第一重佈線層142可對第一連接墊122、第三連接墊161P及第四連接墊162P進行實質上重佈線,且可提供以上所闡述的電性路徑。第一重佈線層142可由金屬材料形成。所述金屬材料的實例包括銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)及其合金。第一重佈線層142可根據對應層的電路設計而提供各種功能。舉例而言,第一重佈線層142可包括接地圖案、電源圖案、訊號圖案等。訊號圖案包括各種訊號(例如資料訊號),不包括接地圖案及電源圖案。此處,使用用語「圖案」以包括配線及接墊。第一重佈線層142在其中第一
半導體晶片120與第二半導體晶片161或第三半導體晶片162交疊的交疊區中主要包括訊號圖案,且在其他(非交疊)區中通常包括電源圖案及/或接地圖案。
第一連接通孔143用於將形成於不同水平高度處的層(例如,第一重佈線層142、第一連接墊122、第三連接墊161P及第四連接墊162P以及配線層112a、112b及112c)電性連接至彼此,藉此在連接結構140內部形成電性路徑。第一連接通孔143可由金屬材料形成。金屬材料的實例包括銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)及其合金。第一連接通孔143中的每一者可為被金屬材料填充的填充型通孔,或者可為其中金屬材料沿通孔孔洞的內壁形成的共形型通孔。第一連接通孔143中的每一者可具有錐形剖面。第一連接通孔143的錐化方向可與框架110的配線/通孔層113a及113b的錐化方向相反。
第一鈍化層150是用於保護連接結構140免受外部物理性或化學性損傷的附加組件。第一鈍化層150可包含熱固性樹脂。舉例而言,第一鈍化層150可由味之素構成膜製成,但並非僅限於此。第一鈍化層150可具有多個開口,所述多個開口各自暴露出最上側第一重佈線層142的至少部分。所述開口可以數十至數萬個的數量提供,或者以大於數十至數萬個的數量或小於數十至數萬個的數量提供。所述開口中的每一者可包括多個孔洞。
第二半導體晶片161及第三半導體晶片162中的每一者
可為其中將大於數百至數百萬個裝置整合於單一晶片中的積體電路。舉例而言,第二半導體晶片161及第三半導體晶片162中的每一者可為例如中央處理單元、圖形處理單元、場域可程式閘陣列、數位訊號處理器、加密處理器、微處理器及/或微控制器等處理器晶片,且具體而言,第二半導體晶片161及第三半導體晶片162中的每一者可為應用處理器,但並非僅限於此。第二半導體晶片161及第三半導體晶片162中的每一者可為構成應用處理器的局部功能的經劃分晶片,經劃分晶片的實例包括中央處理單元、圖形處理單元、場域可程式閘陣列、數位訊號處理器、加密處理器、微處理器及/或微控制器等。作為非限制性實例,第一半導體晶片120、第二半導體晶片161及第三半導體晶片162可被組合於一起以形成一個完整的應用處理器。此處,第一半導體晶片120可充當應用處理器的主晶片,且第二半導體晶片161及第三半導體晶片162可充當應用處理器的子晶片。然而,第二半導體晶片161及第三半導體晶片162並非僅限於此,且各自可為例如動態隨機存取記憶體、唯讀記憶體及快閃記憶體等記憶體。
第二半導體晶片161及第三半導體晶片162中的每一者可為基於主動晶圓的晶粒,且第二半導體晶片161的本體部分及第三半導體晶片162的本體部分可使用矽(Si)、鍺(Ge)、砷化鎵(GaAs)等作為基礎材料來形成。各種電路可形成於其相應的本體部分中。第三連接墊161P及第四連接墊162P被配置成將第二半導體晶片161及第三半導體晶片162電性連接至其他組件,
且可使用例如銅(Cu)及鋁(Al)等金屬材料作為基礎材料來形成。在第二半導體晶片161的本體部分及第三半導體晶片162的本體部分上可分別形成有暴露出第三連接墊161P及第四連接墊162P的鈍化層,且所述鈍化層可為氧化物層、氮化物層等,或者可為由氧化物層與氮化物層構成的雙層。再者,若有必要,則可在其上配置絕緣層等。第二半導體晶片161及第三半導體晶片162中的每一者可為裸晶粒,但若有必要,則可為其中在第二半導體晶片161及第三半導體晶片162中的每一者的主動面上形成附加重佈線層的封裝晶粒,所述主動面是上面配置有第三連接墊161P及第四連接墊162P的表面。
第二半導體晶片161及第三半導體晶片162藉由表面安裝技術(surface mount technology,SMT)在表面安裝狀態下安裝於連接結構140的上表面上。第二半導體晶片161及第三半導體晶片162可包括分別配置於第三連接墊161P及第四連接墊162P上的電性連接凸塊161B及162B。電性連接凸塊161B及162B可由例如銅(Cu)等金屬製成。第二半導體晶片161及第三半導體晶片162可藉由低熔點金屬構件161s及162s(例如包含錫(Sn)的焊料或包含錫(Sn)的合金)安裝於連接結構140的上表面上。低熔點金屬構件161s及162s可配置於第一鈍化層150的多個開口中以連接至被暴露出的第一重佈線層142,且因此,可提供電性連接路徑。根據例示性實施例,低熔點金屬構件161s及162s可分別直接連接至第三連接墊161P及第四連接墊162P。在第二半導體
晶片161及第三半導體晶片162下面可分別配置有底部填充樹脂161r及162r。底部填充樹脂161r及162r可分別固定第二半導體晶片161及第三半導體晶片162。底部填充樹脂161r及162r可被配置成至少局部地覆蓋第三連接墊161P及第四連接墊162P、電性連接凸塊161B及162B以及低熔點金屬構件161s及162s。舉例而言,底部填充樹脂161r及162r可為環氧樹脂黏合劑,但並非僅限於此。
第二重佈線層132及第二連接通孔133可配置於包封體130下面。第二連接通孔133可穿透包封體130的至少部分以將第三配線層112c與第二重佈線層132電性連接至彼此。
第二重佈線層132可用於對第一連接墊122、第二連接墊123、第三連接墊161P及第四連接墊162P進行重佈線,且可提供以上所述電性連接路徑。第二重佈線層132可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)及其合金等金屬材料形成。第二重佈線層132可根據對應層的電路設計而提供各種功能。舉例而言,第二重佈線層132可包括接地圖案、電源圖案、訊號圖案等。接地圖案及訊號圖案可為彼此相同的圖案。此處,本文中所使用的用語「圖案」包括配線及接墊。
第二連接通孔133可將第三配線層112c與第二重佈線層132電性連接至彼此。連接通孔133可使用例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)
及其合金等金屬材料形成。第二連接通孔133可為被金屬材料填充的填充型通孔或者其中金屬材料沿通孔孔洞的內壁形成的共形型通孔。第二連接通孔133中的每一者可具有錐形剖面。錐化方向可與第一配線/通孔層113a及第二配線/通孔層113b的錐化方向相同。在例示性實施例中,第二重佈線層132及第二連接通孔133的層數可經各式修改。
第二鈍化層180是用於保護框架110免受外部物理性或化學性損傷的附加組件。第二鈍化層180亦可包括熱固性樹脂。舉例而言,第二鈍化層180可由味之素構成膜製成,但並非僅限於此。第二鈍化層180可具有多個開口,所述多個開口各自暴露出第二重佈線層132的至少部分。所述開口可以數十至數萬個的數量提供,或者以大於數十至數萬個的數量或小於數十至數萬個的數量提供。所述開口中的每一者可包括多個孔洞。
電性連接金屬190可為用於將半導體封裝100A物理連接及/或電性連接至外部組件的附加組件。舉例而言,半導體封裝100A可藉由電性連接金屬190安裝於電子裝置的主板上。電性連接金屬190可分別配置於第二鈍化層180的多個開口中。因此,電性連接金屬190可電性連接至被暴露出的第二重佈線層132。若有必要,可視需要在第二鈍化層180的多個開口中形成凸塊下金屬,且在此種情形中,電性連接金屬190可連接至經由凸塊下金屬而暴露出的第二重佈線層132。電性連接金屬190中的每一者可包含低熔點金屬,例如,錫(Sn)或包含錫(Sn)的合金。更具
體而言,舉例而言,電性連接金屬190可由焊料等形成。然而,該些僅為實例,且電性連接金屬190並不限於任何具體材料。
電性連接金屬190可為接腳(land)、球、引腳(pin)等。電性連接金屬190可形成為多層或單層。電性連接金屬190當形成為多層時可包括銅柱及焊料。作為另一選擇,電性連接金屬190當形成為單層時可包括錫銀焊料或銅,但該些僅為實例,且電性連接金屬190並非僅限於此。電性連接金屬190在其數目、間隔、排列等方面上並無特別限制,且可由熟習此項技術者根據具體設計而經各式修改。舉例而言,電性連接金屬190的數目可視第一連接墊122、第二連接墊123、第三連接墊161P及第四連接墊162P的數目而介於數十至數萬個,或者可大於此範圍或小於此範圍。
電性連接金屬190中至少一者可配置於扇出區中。扇出區指代第一半導體晶片120所配置的區之外的區。因此,根據實例的半導體封裝100A可為扇出型半導體封裝。扇出型封裝相較於扇入型封裝而言具有優異的可靠性,可實施多個輸入/輸出端子,且有利於三維內連線(3D interconnection)。此外,相較於球柵陣列(ball grid array,BGA)封裝、接腳柵陣列(land grid array,LGA)封裝等而言,扇出型封裝可被製作成具有較小的厚度,且可具有更有競爭力的價格。
模製材料191是用於保護第二半導體晶片161及第三半導體晶片162的附加組件。模製材料191可被配置成覆蓋第二半
導體晶片161及第三半導體晶片162中的每一者的至少部分。模製材料191可包括不同於包封體130的材料。舉例而言,模製材料191可為環氧樹脂模製化合物(epoxy moldng compound,EMC)。若有必要,為對第二半導體晶片161及第三半導體晶片162進行散熱,模製材料191可經歷研磨處理(grinding treatment)。作為研磨處理的結果,第二半導體晶片161及第三半導體晶片162的上表面(非主動面)可被暴露出。根據例示性實施例,在模製材料191頂部上可以疊層封裝(POP)形式進一步配置有例如記憶體封裝等附加封裝。
圖11為示意性地示出半導體封裝的另一實例的剖面圖。
參照圖式,根據另一實例的半導體封裝100B更包括配置於連接結構140上的一或多個被動組件170。另外,半導體封裝100B可更包括配置於框架110的貫穿孔110H內的被動組件171。第一連接墊122、第二連接墊123、第三連接墊161P及第四連接墊162P可視其功能而定電性連接至被動組件170及171。被動組件170的部分可配置於第二半導體晶片161與第三半導體晶片162之間以與第一半導體晶片120交疊,且並非僅限於此。此處,當被動組件170被配置成交疊第一半導體晶片120時,連接結構140的配置於被動組件170下面的第一重佈線層142可主要包括電源圖案及/或接地圖案,因此使與被動組件170的功率路徑最佳化。此外,根據例示性實施例,第一半導體晶片120的貫通孔125的上端可連接至連接結構140的第一重佈線層142的電源圖案及/或
接地圖案。
被動組件170藉由例如焊料等低熔點金屬170s而在表面安裝狀態下進行配置。位於貫穿孔110H內部的被動組件171可藉由連接通孔133連接至第二重佈線層132,但並非僅限於此。根據例示性實施例,被動組件171可嵌置於框架110內部以電性連接至第一配線層112a、第二配線層112b及第三配線層112c的至少部分,或者可與框架110一起被模組化以電性連接至第一重佈線層142。
舉例而言,被動組件170及171中的每一者可為例如多層陶瓷電容器及低溫共燒陶瓷等晶片型電容器或者例如功率電感器等晶片型電感器,但並非僅限於此。作為另一選擇,被動組件170及171中的每一者可為先前技術中通常所知的不同種類的被動組件。換言之,被動組件170及171可為先前技術中通常所知的晶片型被動組件。此處,晶片型組件指代呈獨立晶片形式的組件,所述獨立晶片具有本體、形成於本體內的內部電極及形成於本體上的外部電極。被動組件170及171可為相同種類,或者可為彼此不同的種類。被動組件170及171的數目並無特別限制,且視電路設計而可較圖式中所示者多或較圖式中所示者少。
除以上所述組件以外的組件實質上相同於參照半導體封裝100A等所闡述的組件,且因此將不再對其予以贅述。
圖12為示意性地示出半導體封裝的另一實例的剖面圖。
參照圖式,根據另一實例的半導體封裝100C可具有呈
不同形式的框架110。具體而言,框架110包括:第一絕緣層111a;第一配線層112a,配置於第一絕緣層111a的一個表面上;第二配線層112b,配置於第一絕緣層111a的另一表面上;第二絕緣層111b,配置於第一絕緣層111a的一個表面上以覆蓋第一配線層112a;第三絕緣層111c,配置於第一絕緣層111a的另一表面上以覆蓋第二配線層112b;第三配線層112c,配置於第二絕緣層111b的一個表面上,第二絕緣層111b的所述一個表面與第二絕緣層111b的上面埋置有第一配線層112a的另一表面相對;第四配線層112d,配置於第三絕緣層111c的一個表面上,第三絕緣層111c的所述一個表面與第三絕緣層111c的上面埋置有第二配線層112b的另一表面相對;第一配線/通孔層113a,被配置成穿透第一絕緣層111a以將第一配線層112a與第二配線層112b電性連接至彼此;第二配線/通孔層113b,被配置成穿透第二絕緣層111b以將第一配線層112a與第三配線層112c電性連接至彼此;以及第三配線/通孔層113c,被配置成穿透第三絕緣層111c以將第二配線層112b與第四配線層112d電性連接至彼此。框架110可由於在其中包括數目較大的配線層112a、112b、112c及112d而進一步使連接結構140簡化。
第一絕緣層111a可較第二絕緣層111b及第三絕緣層111c中的每一者厚。第一絕緣層111a可被形成為相對較厚以維持基礎硬度,且第二絕緣層111b及第三絕緣層111c可被合併至框架110中以容置數目較大的配線層112c及112d。自相似的角度來
看,穿透第一絕緣層111a的第一配線/通孔層113a的配線通孔可被形成為具有較穿透第二絕緣層111b及第三絕緣層111c的第二配線/通孔層113b及第三配線/通孔層113c中的每一者的配線通孔的高度及/或平均直徑大的高度及/或平均直徑。此外,在第一配線/通孔層113a的配線通孔中的每一者可具有沙漏形狀或圓筒形狀的同時,第二配線/通孔層113b的配線通孔中的每一者可具有在與第三配線/通孔層113c的配線通孔中的每一者的方向相反的方向上錐化的錐形形狀。第一配線層112a、第二配線層112b、第三配線層112c及第四配線層112d中的每一者的厚度可大於單一第一重佈線層142的厚度。
若有必要,則金屬層115可進一步配置於框架110的貫穿孔110H的內壁上,且金屬層115可被形成為完全覆蓋內壁的表面。金屬層115可包含例如銅(Cu)等金屬材料。第一半導體晶片120可藉由金屬層115而具有改善的電磁場屏蔽效應及熱輻射。
除以上所述組件以外的組件在實質上相同於參照半導體封裝100A所闡述的組件,且因此將不再對其予以贅述。此外,應理解,半導體封裝100C的前述特性特徵適用於根據另一例示性實施例的半導體封裝100B。
圖13為示意性地示出半導體封裝的另一實例的剖面圖。
參照圖式,在根據另一實例的半導體封裝100D中,框架110的孔洞110Ha具有盲空腔形狀。因此,框架110的孔洞110Ha包括配置於孔洞110Ha的底表面上的終止元件層112bM。框架110
包括多個絕緣層111a、111b及111c、多個配線層112a、112b、112c及112d以及多個配線/通孔層113a、113b及113c。第一半導體晶片120的上面配置有第二連接墊123的表面利用例如位於第二連接墊123的下表面上的低熔點金屬120s等連接端子而貼附至終止元件層112bM。因此,當第一半導體晶片120(其發熱最多)配置於孔洞110Ha內時,熱可經由終止元件層112bM(其為金屬板)而自封裝100D的下表面容易地釋放。舉例而言,當半導體封裝100D安裝於印刷電路板等上時,熱可容易地釋放至所述印刷電路板。底部填充樹脂120r可配置於第一半導體晶片120下面以固定第一半導體晶片120。底部填充樹脂120r可被配置成覆蓋第二連接墊123及低熔點金屬120s中的每一者的至少部分。此外,多個配線層112a、112b、112c及112d的至少一個配線層112d可配置於終止元件層112bM下面。此種配線層112d可以與圖9所示第二重佈線層132相似的方式充當背側配線層,且因此,半導體封裝100D因其不需要附加背側製程而具有優勢。
孔洞110Ha可藉由噴砂製程(sandblasting process)形成,且可被形成為具有預定傾斜角度。在此種情形中,第一半導體晶片120的放置可更為容易。再者,儘管未示出,然而,在框架110的孔洞110Ha的內壁上可進一步配置有金屬層,且電磁場屏蔽效應及散熱可藉由所述金屬層而改善。
終止元件層112bM配置於第一絕緣層111a的下表面上,且終止元件層112bM的下表面被第三絕緣層111c覆蓋,同時
終止元件層112bM的上表面的至少部分藉由孔洞110Ha而被暴露出。孔洞110Ha穿透第一絕緣層111a及第二絕緣層111b,且不穿透第三絕緣層111c。然而,該些僅為實例,且藉由配置於第三絕緣層111c的下表面上的終止元件層112bM,孔洞110Ha可穿透第一絕緣層111a、第二絕緣層111b及第三絕緣層111c中的所有者。接觸第一絕緣層111a的終止元件層112bM的邊緣區可具有較終止元件層112bM的藉由孔洞110Ha而自第一絕緣層111a暴露出的暴露區的厚度大的厚度,且此歸因於終止元件層112bM的暴露區的部分亦可在噴砂製程期間被移除。
終止元件層112bM可為包含例如鈦(Ti)、銅(Cu)等金屬的金屬板。然而,終止元件層112bM的材料並非僅限於此,且可包含在噴砂製程中的蝕刻速率(etching rate)較銅(Cu)的蝕刻速率低的材料以提高噴砂製程的可加工性(processability)。舉例而言,終止元件層112bM可為包含絕緣材料的絕緣膜。更具體而言,舉例而言,終止元件層112bM可為包含感光性聚合物的乾膜光阻(dry film photo-resist,DFR)。
第一半導體晶片120可更包括連接至第一連接墊122的電性連接凸塊120B。電性連接凸塊120B可由例如銅(Cu)等金屬材料製成。根據例示性實施例的半導體封裝100D可經歷針對包封體130的研磨製程,且因此,第三配線層112c(框架110的最上側配線層)的表面(被配置成接觸連接通孔143的表面)可配置於與電性連接凸塊120B的被配置成接觸連接通孔143的表面相
同的水平高度處。此處,相同的水平高度包括由於製作誤差而造成的微小變化。因此,將電性連接凸塊120B連接至重佈線層142的連接通孔143的高度可在實質上相同於將第三配線層112c連接至重佈線層142的連接通孔143的高度。因此,當上面形成有連接結構140的表面為平面的時,絕緣層141亦可被形成為平面的。因此,可製作更精密的重佈線層142、連接通孔143等。若有必要,則為防止形成銅(Cu)毛邊(burr)等,在第三配線層112c上可配置附加電性連接金屬。在此種情形中,由於附加電性連接金屬經歷研磨,因此被配置成接觸連接通孔143的電性連接金屬的表面可達成前述關係。
圖14為示意性地示出半導體封裝的另一實例的剖面圖。
參照圖式,根據另一實例的半導體封裝100E可更包括以下中的至少一者:配置於連接結構140上的被動組件170、配置於框架110的孔洞110Ha內的被動組件171及配置於框架110下面的被動組件172。第一連接墊122、第二連接墊123、第三連接墊161P及第四連接墊162P可視其功能而定電性連接至被動組件170、171及172。配置於連接結構140上方的被動組件170的部分可被配置成交疊第一半導體晶片120,但並非僅限於此。被動組件170藉由例如焊料等低熔點金屬170s而在表面安裝狀態下進行配置。孔洞110Ha內的被動組件171可藉由第一連接通孔143連接至配置於被動組件171上方的第一重佈線層142,可連接至框架110的配置於被動組件171下面的第二配線層112b,但並非僅限
於此。根據例示性實施例,被動組件171可埋置於框架110內且電性連接至第一配線層112a、第二配線層112b、第三配線層112c及第四配線層112d的至少部分,或者可與框架一起模組化且電性連接至第一重佈線層142。配置於框架110下面的被動組件172可連接至框架110的第四配線層112d,且舉例而言,可藉由例如焊料等低熔點金屬172s而在表面安裝狀態下進行配置。
被動組件170、171及172可為例如多層陶瓷電容器及低溫共燒陶瓷等晶片型電容器或者例如功率電感器等晶片型電感器。被動組件170、171及172可為彼此相同的類型,或者為彼此不同的類型。被動組件170、171及172的數目並無特別限制,且可根據特定電路設計較圖式中所示者多或較圖式中所示者少。
除以上所提及的組件以外的組件在實質上相同於參照半導體封裝100B及100D等所闡述的組件,且因此將不再對其予以贅述。
圖15為示意性地示出半導體封裝的另一實例的剖面圖。
參照圖式,與圖9所示半導體封裝100A不同,根據另一實例的半導體封裝100F不包括框架110。第一半導體晶片120被配置成包封於包封體130a中。連接結構140的第一重佈線層142藉由穿透包封體130a的連接部件117而電性連接至位於配置於第一重佈線層142下面的絕緣層131上的第二重佈線層132。電性連接凸塊120B可代替圖9所示第二連接墊123配置於第一半導體晶片120的非主動面上。根據例示性實施例,半導體封裝100F可更
包括第二連接墊(圖中未示出),電性連接凸塊120B分別配置於所述第二連接墊上。
除以上所提及的組件以外的組件在實質上相同於參照半導體封裝100A所闡述的組件,且因此將不再對其予以贅述。
根據本文中所揭露的例示性實施例,可提供一種能夠對多個半導體晶片進行封裝且具有最佳訊號特性及功率特性的封裝結構。
本文中所使用的用語「下側(lower side)」、「下部部分(lower portion)」、「下表面(lower surface)」等指代面對扇出型半導體封裝的安裝表面的側、部分、表面等,而「上側(upper side)」、「上部部分(upper portion)」、「上表面(upper surface)」等用於指代面對扇出型半導體封裝的安裝表面的相反方向的側、部分、表面等。然而,該些用語是為方面說明起見而被如此定義,且因此,不應用於限制本發明的範圍。
元件「連接(connected)」或「耦合(coupled)」至另一元件此一陳述包括其中元件直接連接或直接耦合至所述另一元件或者利用黏合劑層等間接連接或間接耦合至所述另一元件的情形。此外,一個元件「電性連接(electrically connected)」至另一元件此一陳述包括其中所述兩個元件物理地連接至彼此的情形,且亦包括其中所述兩個元件不物理地連接至彼此的情形。此外,本文中所使用的用語「第一(first)」、「第二(second)」及其變型不表示任何次序及/或重要性等,而是用於區分各個元件。在一些
情形中,在不背離本發明的範圍的條件下,第一元件可被指定為第二元件,反之亦然。
本發明中所使用用語「實施例(embodiments)」不指代相同的實施例,且提供實施例是為突出各個實施例的特性特徵。然而,本文中所闡述的任意一個實施例可與參照另一實施例所闡述的其他特徵或特性加以組合。舉例而言,應理解,除非另外明確陳述,否則參照一個實施例所闡述的特徵可應用於另一實施例。
本發明中所使用的用語僅用於示出本發明的實施例而非限制本發明的範圍。再者,除非另外具體陳述,否則單數的用法亦包括複數。
100A:半導體封裝
110:框架
110H:貫穿孔
111a:絕緣層/第一絕緣層
111b:絕緣層/第二絕緣層
112a:配線層/第一配線層
112b:配線層/第二配線層
112c:配線層/第三配線層
113a:配線/通孔層/第一配線/通孔層
113b:配線/通孔層/第二配線/通孔層
120:第一半導體晶片
121:本體部分
122:第一連接墊
123:第二連接墊
125:貫通孔
130:包封體
132:第二重佈線層
133:連接通孔/第二連接通孔
140:連接結構
141:絕緣層
142:重佈線層/第一重佈線層
143:第一連接通孔
150:第一鈍化層
161:第二半導體晶片
161B、162B:電性連接凸塊
161P:第三連接墊
161r、162r:底部填充樹脂
161s、162s:低熔點金屬構件
162:第三半導體晶片
162P:第四連接墊
180:第二鈍化層
190:電性連接金屬
191:模製材料
I-I':線
Claims (10)
- 一種半導體封裝,包括:第一半導體晶片,具有第一表面及與所述第一表面相對的第二表面,且包括第一連接墊及第二連接墊以及貫通孔,所述第一連接墊及所述第二連接墊分別配置於所述第一表面及所述第二表面上,所述貫通孔連接至所述第二連接墊;連接結構,配置於所述第一半導體晶片的所述第一表面上,且包括電性連接至所述第一半導體晶片的所述第一連接墊的第一重佈線層;第二重佈線層,配置於所述第一半導體晶片的所述第二表面上,且電性連接至所述第一半導體晶片的所述第二連接墊;以及第二半導體晶片,配置於所述連接結構的第三表面上,所述連接結構的所述第三表面與所述連接結構的上面配置有所述第一半導體晶片的第四表面相對,其中所述第二半導體晶片的上面配置有所述第二半導體晶片的第三連接墊的表面面對所述連接結構的所述第三表面,且其中所述第一半導體晶片的所述第一連接墊連接至所述第一重佈線層的訊號圖案,且所述第一半導體晶片的所述第二連接墊連接至所述第二重佈線層的電源圖案及接地圖案中的至少一者。
- 如申請專利範圍第1項所述的半導體封裝,其中在所述第一半導體晶片中,所述貫通孔及所述第二連接墊配置於所述第一半導體晶片的中心區中,且所述第一連接墊配置於所述第一半 導體晶片的周邊區中。
- 如申請專利範圍第1項所述的半導體封裝,其中所述第二半導體晶片被配置成在垂直方向上與所述第一半導體晶片局部地交疊。
- 如申請專利範圍第3項所述的半導體封裝,其中所述第二半導體晶片的所述第三連接墊的部分藉由所述第一重佈線層的所述訊號圖案而電性連接至所述第一半導體晶片的配置於所述第三連接墊的所述部分下面的所述第一連接墊。
- 如申請專利範圍第1項所述的半導體封裝,其中所述第一半導體晶片的所述貫通孔藉由穿透所述第一半導體晶片而自所述第二連接墊延伸至所述第一表面或與所述第一表面接近的區。
- 如申請專利範圍第1項所述的半導體封裝,其中所述第一半導體晶片及所述第二半導體晶片中的每一者構成應用處理器(AP)的局部功能或整體功能。
- 如申請專利範圍第1項所述的半導體封裝,更包括配置於所述連接結構的所述第三表面上的被動組件。
- 如申請專利範圍第1項所述的半導體封裝,更包括配置於所述連接結構的所述第四表面上且具有孔洞的框架,所述第一半導體晶片配置於所述孔洞中,其中所述框架包括電性連接至所述第一重佈線層的一或多個配線層。
- 一種半導體封裝,包括:第一半導體晶片,具有第一表面及與所述第一表面相對的第 二表面,且包括第一連接墊及第二連接墊以及貫通孔,所述第一連接墊配置於所述第一表面上且用於傳輸及接收訊號,所述第二連接墊配置於所述第二表面上且用於接收功率,所述貫通孔連接至所述第二連接墊;連接結構,配置於所述第一半導體晶片的所述第一表面上,且包括電性連接至所述第一半導體晶片的所述第一連接墊的第一重佈線層;以及至少一個第二半導體晶片,配置於所述連接結構的第三表面上,所述連接結構的所述第三表面與所述連接結構的上面配置有所述第一半導體晶片的第四表面相對,且所述至少一個第二半導體晶片的上面配置有所述至少一個第二半導體晶片的第三連接墊的表面面對所述連接結構的所述第三表面。
- 如申請專利範圍第9項所述的半導體封裝,更包括第二重佈線層,所述第二重佈線層配置於所述第一半導體晶片的所述第二表面上且電性連接至所述第一半導體晶片的所述第二連接墊,其中所述第一連接墊電性連接至配置於所述的所述連接結構的所述第一重佈線層,且所述貫通孔及所述第二連接墊電性連接至配置於所述貫通孔及所述第二連接墊下面的所述第二重佈線層。
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