CN113140475A - 存储器封装件及其形成方法 - Google Patents

存储器封装件及其形成方法 Download PDF

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Publication number
CN113140475A
CN113140475A CN202010263253.3A CN202010263253A CN113140475A CN 113140475 A CN113140475 A CN 113140475A CN 202010263253 A CN202010263253 A CN 202010263253A CN 113140475 A CN113140475 A CN 113140475A
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China
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memory
layer
forming
structures
die
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CN202010263253.3A
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余振华
蔡仲豪
王垂堂
王奕
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113140475A publication Critical patent/CN113140475A/zh
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Abstract

一种封装件包括贴合到逻辑装置的存储器堆叠，所述存储器堆叠包括：第一存储器结构；第一重布线层，位于所述第一存储器结构之上并电连接到所述第一存储器结构；第二存储器结构，位于所述第一重布线层上；第二重布线层，位于所述第二存储器结构之上并电连接到所述第二存储器结构；以及第一金属柱，位于所述第一重布线层上并邻近所述第二存储器结构，所述第一金属柱电连接所述第一重布线层与所述第二重布线层，其中所述第一存储器结构中的每一第一存储器结构包括：存储器管芯，包括第一接触垫；以及周边电路系统管芯，包括第二接触垫，其中所述存储器管芯的所述第一接触垫结合到所述周边电路系统管芯的所述第二接触垫。

Description

存储器封装件及其形成方法
技术领域
本公开实施例是有关于存储器封装件及其形成方法。
背景技术
高性能计算(High-Performance Computing，HPC)系统通常包括结合到逻辑管芯的高带宽存储器(High-Bandwidth-Memory，HBM)堆叠。HBM堆叠通常包括堆叠在一起的多个存储器管芯，其中较高的存储器管芯通过焊料结合或利用微凸块实现的金属直接结合而结合到较低的存储器管芯。在存储器管芯中形成有硅穿孔(Through-Silicon Via，TSV)，使得上部管芯可通过TSV电连接到逻辑管芯。
发明内容
根据本公开的一些实施例，一种存储器封装件的形成方法包括：形成第一组存储器结构及第二组存储器结构，其中形成所述第一组存储器结构及所述第二组存储器结构中的每一存储器结构包括在第一衬底上形成包括存储器组件的第一装置、在第二衬底上形成第二装置、以及将所述第二装置结合到所述第一装置，以将所述第一装置电耦合到所述第二装置；形成存储器结构堆叠，包括将所述第一组存储器结构放置在载体上、在所述第一组存储器结构上形成电连接到所述第一组存储器结构的第一重布线结构、在所述第一重布线结构上形成电连接到所述第一重布线结构的第一组穿孔、以及将所述第二组存储器结构放置在所述第一重布线结构上；以及将所述存储器结构堆叠贴合到逻辑管芯。
根据本公开的一些实施例，一种存储器封装件的形成方法包括：形成堆叠式存储器装置，包括：将第一存储器结构放置在载体衬底上，所述第一存储器结构包括结合到第一逻辑管芯的第一存储器管芯，在所述第一存储器结构上形成第一重布线结构，其中所述第一重布线结构电连接到所述第一存储器结构，形成从所述第一重布线结构延伸的第一金属柱，其中所述第一金属柱电连接到所述第一重布线结构，将第二存储器结构邻近所述第一金属柱放置在所述第一重布线结构上，所述第二存储器结构包括结合到第二逻辑管芯的第二存储器管芯，在所述第二存储器结构及所述第一金属柱之上形成第二重布线结构，其中所述第二重布线结构电连接到所述第一金属柱，以及在所述第二重布线结构上形成外部连接件，其中所述外部连接件电连接到所述第二重布线结构；以及将所述堆叠式存储器装置贴合到第三逻辑管芯，其中所述堆叠式存储器装置的所述外部连接件电连接到所述第三逻辑管芯。
根据本公开的一些实施例，一种存储器封装件包括贴合到逻辑装置的存储器堆叠，所述存储器堆叠包括：多个第一存储器结构；第一重布线层，位于所述第一存储器结构之上并电连接到所述多个第一存储器结构；多个第二存储器结构，位于所述第一重布线层上；第二重布线层，位于所述第二存储器结构之上并电连接到所述第二存储器结构；以及多个第一金属柱，位于所述第一重布线层上并邻近所述多个第二存储器结构，所述多个第一金属柱电连接所述第一重布线层与所述第二重布线层；其中所述第一存储器结构中的每一第一存储器结构包括：存储器管芯，包括第一接触垫；以及周边电路系统管芯，包括第二接触垫，其中所述存储器管芯的所述第一接触垫结合到所述周边电路系统管芯的所述第二接触垫。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1示出根据一些实施例的存储器结构的周边装置的剖视图。
图2A及图2B示出根据一些实施例的存储器结构的存储器装置的剖视图。
图3A至图3F示出根据一些实施例在形成存储器结构时的中间阶段的剖视图。
图4A至图4H是根据一些实施例在用于形成存储器堆叠的工艺期间的中间步骤的剖视图。
图5A至图5E是根据一些实施例在用于形成存储器封装件的工艺期间的中间步骤的剖视图。
图6至图9示出根据一些实施例的存储器封装件的剖视图。
图10A至图10D是根据一些实施例在用于形成存储器封装件的工艺期间的中间步骤的剖视图。
图11A及图11B示出根据一些实施例并入有存储器封装件的封装结构。
具体实施方式
以下公开内容提供用于实作本公开的不同特征的许多不同的实施例或实例。以下阐述组件及构造的具体实例以简化本公开。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在……之下(underlying)”、“在……下面(below)”、“下部的(lower)”、“上覆在……上(overlying)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
根据各种实施例，提供包括存储器结构堆叠的存储器封装件及其形成方法。根据一些实施例，示出在形成存储器堆叠时的中间阶段。论述了一些实施例的一些变化。在所有各视图及说明性实施例中，相同的参考编号用于标示相同的元件。根据本公开的一些实施例，存储器结构包括存储器装置(例如，存储器管芯)，所述存储器装置结合到周边装置(例如，另一管芯)。例如，存储器装置可被混合结合到周边装置。通过将周边装置结合到存储器装置，可减小周边装置与存储器装置之间的电布线距离，这可减少等待时间并改善操作速度。另外，存储器装置及周边装置可使用不同的技术或工艺单独地形成。
应了解，将关于特定上下文(即包括结合到装置管芯的存储器管芯的管芯堆叠)来阐述实施例。所论述实施例的概念也可应用于其他结构的结构及加工，包括但不限于逻辑管芯堆叠、输入/输出(input-output，I/O)管芯堆叠或包括混合的逻辑管芯、I/O管芯、存储器管芯等的管芯堆叠的形成。本文中所论述的实施例是为了提供能够制作或使用本公开主题的实例，且所属领域中的普通技术人员将容易理解在不同实施例的预期范围内可进行的修改。下图中相同的参考编号及字符指代相同的组件。尽管方法实施例可被论述为以特定次序执行，但其他方法实施例可以任何逻辑次序执行。
图1、图2A、图2B及图3A至图3F示出根据本公开一些实施例在形成存储器结构300时的中间阶段的剖视图。图1示出根据一些实施例的周边装置100，且图2A及图2B示出根据一些实施例的存储器装置200。图3A至图3F示出由周边装置100及存储器装置200形成存储器结构300。可使用除所示技术或工艺阶段之外的技术或工艺阶段来形成存储器结构300。所示的周边装置100、存储器装置200及存储器结构300是说明性实例，且在不背离本公开的范围的条件下，其他实施例可具有除所示配置或特征之外的配置或特征。例如，在图6至图8所示的实施例中示出具有不同配置的一些存储器结构。
图1示出根据一些实施例的周边装置100。周边装置100可例如是集成电路管芯、芯片、封装件或与存储器装置200介接的其他装置。周边装置100可例如包括与存储器结构300中的存储器装置200进行通信或控制存储器装置200操作的逻辑电路、控制电路、I/O电路、测试电路等。图1中所示的周边装置100可例如在晶片中形成，所述晶片可包括在后续步骤中被单体化以形成多个周边装置的不同装置区。可根据适用于形成周边装置的制造工艺来加工周边装置100。例如，周边装置100包括半导体衬底102，半导体衬底102可包含例如经掺杂硅或未掺杂硅等材料、或者绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的有源层。半导体衬底102可包含：其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其组合。也可使用其他衬底，例如多层式或梯度衬底。半导体衬底102具有有时被称为前侧的有源表面(例如，图1中面朝上的表面)以及有时被称为背侧的非有源表面(例如，图1中面朝下的表面)。
装置104可形成在半导体衬底102的前表面处。装置104可包括有源装置(例如，晶体管、二极管等)及/或无源装置(例如，电容器、电阻器等)。内连结构110形成在衬底102及装置104之上，且可包括介电层、金属化图案106(例如，金属线、通孔等)等等。介电层可包括低介电常数(低k)介电层及/或非低介电常数介电层。在一些实施例中，内连结构110的一个或多个介电层由氧化硅、氮化硅、碳化硅、氮氧化硅、其组合及/或其多层体形成。内连结构110的金属化图案106电耦合到装置104以形成周边装置100。金属化图案106可由钨、钴、镍、铜、银、金、铝等或其组合形成。金属化图案106可使用合适的工艺(例如双镶嵌工艺(dualdamascene process)或另一工艺)形成。
在一些实施例中，周边装置100包括延伸穿过半导体衬底102并进入内连结构110的穿孔(有时称为衬底穿孔(Through-Substrate Via，TSV))112。例如，TSV 112可延伸穿过半导体衬底102，且电连接到内连结构110的金属化图案106。在一些实施例中，一个或多个TSV 112可延伸穿过内连结构110，且电连接到内连结构110的接触垫108(以下阐述)。TSV112可由衬里113环绕。图1中示出一个TSV 112，但在其他实施例中可存在多于一个TSV112。在其他实施例中，周边装置100不包括TSV 112。
周边装置100进一步包括在内连结构110中形成的结合垫108。结合垫108可由利于混合结合(hybrid bonding)的金属(例如铜、铜合金或另一种合适的金属)形成。结合垫108电连接到金属化图案106及/或TSV 112，或者结合垫108可为金属化图案106的一部分。结合垫108可与内连结构110的顶表面共面。内连结构110的顶表面可为介电材料，例如氧化硅。图1中示出一个结合垫108，但在其他实施例中可存在多于一个结合垫108。
参考图2A及图2B，示出存储器装置200的两个实施例。存储器装置200可包括不同类型的存储器技术，例如动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(Static Random Access Memory，SRAM)、磁性随机存取存储器(Magnetic Random Access Memory，MRAM)或其他类型的存储器技术。例如，图2A示出包括DRAM的存储器装置200，而图2B示出包括MRAM的存储器装置200。存储器装置200可包括衬底202及在衬底202的前表面处形成的装置204。在一些实施例中，存储器装置200可为存储器管芯、包括存储器组件的集成电路管芯等。装置204可包括有源装置(例如，晶体管、二极管等)及/或无源装置(例如，电容器、电阻器等)。使用不同类型存储器技术的存储器装置可包括不同的存储器组件。例如，根据一些实施例，图2A所示的DRAM存储器装置200的存储器组件包括连接到顶部金属触点252及底部接触金属250的堆叠电容器254。根据一些实施例，底部接触金属250用作位线。在一些实施例中，字线256可形成在衬底202中。作为另一实例，根据一些实施例，图2B所示的MRAM存储器装置200的存储器组件包括连接到字线256及位线250的磁性隧道结(magnetic tunnel junction，MTJ)222。在一些实施例中，MRAM存储器装置200的字线256或位线250可为以下所述的内连结构210的金属化图案206。图2A及图2B所示的存储器装置200是说明性实例，且可存在其他类型或配置的存储器装置200。
内连结构210形成在衬底202及装置204之上，且可包括介电层、金属化图案206(例如，金属线、通孔等)等等。在一些实施例中，存储器的组件(例如，堆叠电容器254或其他组件)可形成在内连结构210内。介电层可包括低介电常数介电层及/或非低介电常数介电层。在一些实施例中，内连结构210的一个或多个介电层由氧化硅、氮化硅、碳化硅、氮氧化硅、其组合及/或其多层体形成。内连结构210的金属化图案206电耦合到装置204及存储器组件，以形成存储器装置200。金属化图案206可由钨、钴、镍、铜、银、金、铝等或其组合形成。金属化图案206可使用合适的工艺(例如双镶嵌工艺或另一工艺)形成。
存储器装置200进一步包括形成在内连结构210中的结合垫208。结合垫208可由利于混合结合的金属(例如铜、铜合金或另一种合适的金属)形成。结合垫208电连接到金属化图案206，或者结合垫208可为金属化图案206的一部分。结合垫208可与内连结构210的顶表面共面。内连结构210的顶表面可为介电材料，例如氧化硅。图2A及图2B中示出两个结合垫208，但在其他实施例中可存在一个结合垫208或者多于两个结合垫208。
图3A至图3F是根据一些实施例在用于形成存储器结构300(参见图3E)的工艺期间的中间步骤的剖视图。图3A至图3F中所示的工艺是说明性实例，且可例如示出完整存储器结构300、完整存储器结构300的一部分或者随后被单体化的几个存储器结构300之一的形成。存储器结构300的其他配置涵盖在本公开的范围内。在图3A中，将周边装置100结合到存储器装置200。周边装置100与存储器装置200的结合部分在图3A至图3F中由虚线指示。
在一些实施例中，可使用例如混合结合技术将周边装置100结合到存储器装置200。例如，可将周边装置100的一个或多个结合垫108结合到存储器装置200的结合垫208，且可将周边装置100的内连结构110的顶表面结合到存储器装置200的内连结构210的顶表面。在执行结合之前，可对周边装置100及/或存储器装置200执行表面处理。表面处理可例如是等离子体处理工艺，且用于产生等离子体的工艺气体可为含氢气体，所述含氢气体包括包含氢(H2)及氩(Ar)的第一气体、包含H2及氮(N2)的第二气体或者包含H2及氦(He)的第三气体。通过所述处理，可增加周边装置100的及存储器装置200的表面处OH基团的数目。接下来，可执行预结合工艺，其中将周边装置100与存储器装置200对准。将周边装置100与存储器装置200压靠在一起，以在周边装置100的内连结构110的顶表面与存储器装置200的内连结构210的顶表面之间形成弱结合。在预结合工艺之后，执行退火以加强所述弱结合并形成熔融结合(fusion bond)。在退火期间，OH键的H被除气，从而在内连结构110与内连结构210之间形成Si-O-Si键，从而加强所述结合。在混合结合期间，在周边装置100的结合垫108与存储器装置200的结合垫208之间也发生直接金属间(metal-to-metal)结合。因此，所得的结合是包括Si-O-Si键及金属间直接结合的混合结合。
通过将周边装置100结合到存储器装置200，可减小周边装置100与存储器装置200之间的布线距离，这可减少等待时间并改善高频操作。例如，与在与存储器装置200相同的衬底202上形成周边装置100的装置104相比，布线距离可减小。在一些实施例中，用于形成周边装置100的工艺技术可不同于用于形成存储器装置200的工艺技术。例如，周边装置100可使用用于形成互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)的工艺(“CMOS工艺”)来形成，而存储器装置200可使用用于形成DRAM的工艺(“DRAM工艺”)来形成。此为实例，且在其他实施例中可使用其他类型的工艺。这样一来，可使用特定工艺技术来优化周边装置100的形成或配置，且可使用不同的特定工艺技术来优化存储器装置200的形成或配置。通过使用适当的工艺形成不同的周边装置100及存储器装置200，可形成具有改善性能的存储器结构300。
在一些实施例中，可将多于一个周边装置100结合到存储器装置200，且所述多于一个周边装置100可包括相似及/或不同的周边装置。在一些实施例中，周边装置100的长度或宽度可小于存储器装置200的对应长度或宽度，如图3A所示。在一些实施例中，周边装置100可具有介于约12mm与约3mm之间的长度或宽度，而存储器装置200可具有介于约15mm与约5mm之间的长度或宽度。在一些实施例中，周边装置100可具有介于存储器装置200的对应长度或宽度的约30％与约100％之间的长度或宽度。在一些实施例中，周边装置100可具有介于约9mm2与约144mm2之间的面积，且存储器装置200可具有介于约25mm2与约225mm2之间的面积。这样一来，可以各种布置形式组合多种大小及形状的装置以形成存储器结构300，这容许例如针对特定应用具有大的设计弹性。
参考图3B，根据一些实施例，在周边装置100及存储器装置200之上形成介电材料310。在一些实施例中，介电材料310包括例如氧化硅等的氧化物，其可例如使用原硅酸四乙酯(tetraethyl orthosilicate，TEOS)或另一种技术形成。介电材料310可使用例如化学气相沉积(Chemical Vapor Deposition，CVD)、高密度等离子体化学气相沉积(High-DensityPlasma Chemical Vapor Deposition，HDPCVD)等来形成。根据其他实施例，介电材料310由例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺等聚合物形成。可执行平坦化工艺以移除介电材料310的多余部分，以便暴露出周边装置100，这可暴露出周边装置100的TSV 112。平坦化工艺可包括研磨工艺、化学机械抛光(chemical-mechanical polish，CMP)工艺等。
图3C示出介电穿孔(Through-Dielectric Via，TDV)312的形成，TDV312延伸穿过介电材料310并与存储器装置200形成电连接。可通过蚀穿介电材料310以形成通孔开口且然后用导电材料填充通孔开口来形成TDV312。刻蚀可例如包括各向异性干刻蚀工艺。在一些实施例中，所述刻蚀暴露出结合垫208。在一些实施例中，可使用结合垫208作为刻蚀停止层来执行刻蚀。在一些实施例中，TDV 312由同质导电材料形成，所述同质导电材料可包括金属或金属合金，包括铜、铝、钨等。根据本公开的其他实施例，TDV 312包括复合结构，所述复合结构包括由钛、氮化钛、钽、氮化钽等形成的导电阻挡层以及所述阻挡层之上的含金属材料。TDV 312的形成可包括将导电材料沉积到通孔开口中，且然后执行平坦化工艺以移除介电材料310及周边装置100之上所沉积导电材料的多余部分。在图3C至图3E中示出一个TDV 312，但在其他实施例中可存在多于一个TDV 312。
参考图3D，在介电材料310之上形成金属化图案316以形成与TDV 312的电连接，且在周边装置100之上形成金属化图案316以形成与TSV 112的电连接。在一些实施例中，在形成金属化图案316之前，可在介电材料310及周边装置100之上形成隔离层313。隔离层313可为一层氧化物、氮化物等，且可被形成为防止金属化图案316的导电材料扩散到介电材料310或周边装置100中。金属化图案316可通过以下来形成：形成毯覆晶种层(未示出)，形成并图案化镀覆掩模(例如光刻胶)以露出金属晶种层的与金属化图案316对应的部分，在镀覆掩模的开口中镀覆导电材料，移除镀覆掩模，且刻蚀晶种层的先前由镀覆掩模覆盖的部分。根据本公开的一些实施例，晶种层包括钛层及钛层之上的铜层。晶种层的形成可例如包括物理气相沉积(Physical Vapor Deposition，PVD)工艺或另一种合适的工艺。在一些实施例中，所镀覆材料包括铜或铜合金。镀覆可例如包括电化学镀覆工艺或无电镀覆工艺。
仍参照图3D，在介电材料310、周边装置100及金属化图案316之上形成绝缘层314。在一些实施例中，绝缘层314可包括一个或多个低介电常数介电层及/或非低介电常数介电层。例如，绝缘层314可包含例如氧化硅、氮化硅、碳化硅、氮氧化硅、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、其组合等绝缘材料，且可使用CVD、PVD、原子层沉积(Atomic Layer Deposition，ALD)、旋转涂布工艺(spin-on coatingprocess)、其组合等来形成。在其他实施例中，绝缘层314可包括一层或多层例如聚苯并恶唑(PBO)、聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)、其组合等的绝缘材料，且可使用旋转涂布工艺等来形成。在一些实施例中，例如使用CMP工艺对绝缘层314进行平坦化。
参考图3E，根据一些实施例，形成导电垫318及钝化层320，从而形成存储器结构300。在一些实施例中，在绝缘层314中形成开口以暴露出金属化图案316的区。绝缘层314中的开口可使用合适的技术来形成，例如，在绝缘层314之上形成经图案化光刻胶层，然后使用经图案化光刻胶层作为刻蚀掩模来刻蚀绝缘层314。
在一些实施例中，可通过以下来形成导电垫318：首先在绝缘层314之上及绝缘层314中的开口内形成晶种层(未示出)，且然后形成并图案化镀覆掩模(例如光刻胶)以展露出晶种层的与导电垫318对应的部分。可使用镀覆工艺在镀覆掩模的开口中形成导电垫318的导电材料，移除镀覆掩模，且通过刻蚀而移除金属晶种层的先前被镀覆掩模覆盖的部分。晶种层可包含铜、钛、镍、金、钯等或其组合。
导电垫318可使用其他技术来形成。例如，可将导电垫318的导电材料沉积为毯覆层，且然后使用合适的光刻及刻蚀工艺进行图案化以形成导电垫318。可通过电化学镀覆工艺、无电镀覆工艺、CVD、ALD、PVD等或其组合来形成导电垫318的导电材料。在一些实施例中，导电垫318的导电材料包括铜、钨、铝、银、金等或其组合。在一些实施例中，一些导电垫318可为用于对存储器结构300进行电测试的测试垫。
根据一些实施例，在形成导电垫318之后，在绝缘层314及导电垫318之上形成钝化层320。钝化层320可包括一个或多个低介电常数介电层及/或非低介电常数介电层。例如，钝化层320可包含例如氧化硅、氮化硅、碳化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼的磷硅酸盐玻璃(BPSG)、其组合等绝缘材料，且可使用CVD、PVD、ALD、旋转涂布工艺、其组合等来形成。在其他实施例中，钝化层320可包括一层或多层例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合等的绝缘材料，且可使用旋转涂布工艺等来形成。在一些实施例中，如图3E所示，可在钝化层320中刻蚀开口以暴露出导电垫318。在其他实施例中，使用例如CMP工艺对钝化层320进行平坦化以暴露出导电垫318。
如图3A至图3F所示，通过在两个不同的衬底上形成存储器装置200及其相关联的周边装置100并将其结合在一起以形成存储器结构300，周边装置100的电路系统可更靠近存储器装置200的组件放置。这样一来，可减小布线距离，且可改善存储器结构300的一些操作特性，例如等待时间。在一些实施例中，可在单个衬底202上形成多个存储器装置200，且在其上形成多个存储器结构300。然后，可使用例如合适的锯切工艺或其他切割工艺将所述多个存储器结构300单体化成单独的存储器结构300。
图4A至图4H是根据一些实施例在用于形成存储器堆叠450(参见图4H)的工艺期间的中间步骤的剖视图。在图4A至图4H中，堆叠多个存储器结构(例如，存储器结构400)，并在其间形成电连接(例如，重布线结构422或导电柱438，参见图4D至图4H)，以形成存储器堆叠450。应了解，存储器结构及/或电连接的类型、数目、配置或布置可不同于本公开的各图中所示的那些，且所有这些变化等均涵盖在本公开的范围内。在一些实施例中，存储器堆叠450是高带宽存储器(HBM)堆叠，但应了解，实施例可应用于其他三维集成电路(three-dimensional integrated circuit，3DIC)封装件、存储器封装件、晶片上芯片(chip-on-wafer，CoW)封装件等。
在图4A中，提供载体衬底402，并在载体衬底402上形成释放层404。载体衬底402可为玻璃载体衬底、陶瓷载体衬底等。载体衬底402可为晶片、面板等，使得多个封装件可同时形成在载体衬底402上。释放层404可由聚合物系材料形成，所述聚合物系材料可与载体衬底402一起从将在后续步骤中形成的上覆结构移除。在一些实施例中，释放层404是在受热时会失去其粘合性质的环氧树脂系热释放材料，例如光/热转换(light-to-heat-conversion，LTHC)释放涂层。在其他实施例中，释放层404可为紫外(ultra-violet，UV)胶，其在被暴露于UV光时会失去其粘合性质。释放层404可作为液体进行施配并进行固化，可为被积层到载体衬底402上的积层体膜(laminate film)，或可为类似形式。释放层404的顶表面可为平整的(leveled)，且可具有高平面度(degree of planarity)。
在释放层404上可形成可选的介电层408。介电层408的底表面可与释放层404的顶表面接触。在一些实施例中，介电层408由例如聚苯并恶唑、聚酰亚胺、苯并环丁烯(BCB)等聚合物形成。在其他实施例中，介电层408由以下形成：例如氮化硅等氮化物；例如氧化硅等氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼的磷硅酸盐玻璃(BPSG)等；或者类似物。介电层408可通过任何可接受的沉积工艺(例如旋转涂布、CVD、积层等或者其组合)形成。
在图4B中，通过粘合剂418将存储器结构400粘附到介电层408。在图4B至图4H所示的实施例中，所示的存储器结构400与先前在图3E与图3F中阐述的存储器结构300相似，只不过每一存储器结构400包括两个周边装置100，所述两个周边装置100可为每一存储器结构400内不同类型的周边装置。每一存储器结构400中的周边装置100之一还包括完全延伸穿过其的TSV 112。图4B至图4H所示的存储器结构400是说明性实例，且其他实施例可包括与所示存储器结构不同的存储器结构。另外，为了清楚起见，图4B至图4H所示的存储器结构400的一些特征已被省略或简化。在一些实施例中，可将比所示更多或更少的存储器结构400粘附到电介质408。存储器结构400可例如是存储器堆叠450的第一层存储器结构400(参见图4H)。
粘合剂418形成在存储器结构400的背侧上，并将存储器结构400粘附到载体衬底402，例如粘附到介电层408。粘合剂418可为任何合适的粘合剂、环氧树脂、管芯贴合膜(dieattach film，DAF)等。粘合剂418可被施加到存储器结构400的背侧，或者可被施加在载体衬底402之上。例如，粘合剂418可在分离单独的存储器结构400的单体化工艺之前施加到存储器结构400的背侧。
在图4C中，在各种组件上及周围形成包封体442。在形成之后，包封体442包封存储器结构400。包封体442可为模塑化合物、环氧树脂等。包封体442可通过压缩模塑(compression molding)、转移模塑(transfer molding)等施加，且可形成在载体衬底402之上，以掩埋或覆盖存储器结构400。包封体442进一步形成在存储器结构400之间的间隙区中。包封体442可以液体或半液体形式施加，且然后进行固化。
仍参照图4C，对包封体442执行平坦化工艺。在一些实施例中，平坦化工艺可移除每一存储器结构400的钝化层320的部分，以暴露出每一存储器结构400的导电垫318，如图4C所示。在一些实施例中，平坦化工艺不暴露出导电垫318，且执行合适的光刻及刻蚀工艺以在钝化层320中形成暴露出导电垫318的开口。在平坦化工艺之后，导电垫318的、钝化层320的及包封体442的顶表面可为共面的。平坦化工艺可例如是化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果导电垫318已被暴露出，则可省略平坦化。
在图4D中，在包封体442及存储器结构400之上形成重布线结构422。重布线结构422包括介电层424及428以及金属化图案426。金属化图案也可被称为重布线层或重布线。重布线结构422被示为具有单一金属化图案的实例。可在重布线结构422中或其他重布线结构(例如图4G至图4H所示的重布线结构422中的任一者或本公开中所提及的其他重布线结构)中形成更多或更少的介电层及金属化图案。如果将形成更少的介电层及金属化图案，则可省略以下论述的步骤及工艺。如果将形成更多的介电层及金属化图案，则可重复以下论述的步骤及工艺。
在图4D中，在包封体442及存储器结构400上沉积介电层424。在一些实施例中，介电层424由例如PBO、聚酰亚胺、BCB等光敏性材料形成，所述光敏性材料可使用光刻掩模进行图案化。介电层424可通过旋转涂布、积层、CVD等或其组合来形成。然后对介电层424进行图案化。所述图案化会形成将导电垫318的部分暴露出的开口。图案化可通过可接受的工艺进行，例如当介电层424是光敏性材料时通过将介电层424暴露于光，或者通过使用例如各向异性刻蚀工艺进行刻蚀。如果介电层424是光敏性材料，则可在曝光之后将介电层424显影。
然后形成金属化图案426。金属化图案426包括在介电层424的主表面上并沿着所述主表面延伸的线部分(也称为导电线)。金属化图案426进一步包括延伸穿过介电层424的通孔部分(也称为导电通孔)，以将存储器结构400实体及电耦合到随后形成的结构。作为形成金属化图案426的实例，在介电层424之上及延伸穿过介电层424的开口中形成晶种层。在一些实施例中，晶种层是金属层，其可为单一层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及钛层之上的铜层。晶种层可使用例如PVD等形成。然后在晶种层上形成并图案化光刻胶。光刻胶可通过旋转涂布等形成，且可暴露于光以进行图案化。光刻胶的图案对应于金属化图案426。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。然后在光刻胶的开口中及晶种层的被暴露出的部分上形成导电材料。导电材料可通过镀覆(例如电镀或无电镀覆等)形成。导电材料可包括金属，如铜、钛、钨、铝等。导电材料与晶种层的下伏部分的组合形成金属化图案426。移除光刻胶及晶种层的上面未形成导电材料的部分。光刻胶可例如使用氧等离子体等通过可接受的灰化或剥除工艺移除。一旦光刻胶被移除，便例如通过使用可接受的刻蚀工艺(例如通过湿刻蚀或干刻蚀)移除晶种层的被暴露出的部分。
在图4E中，根据一些实施例，形成导电柱438。导电柱438电连接到重布线结构422，且因此可电连接到存储器结构400。可首先对重布线结构422的最顶部介电层(例如，介电层428)进行图案化，以形成开口，开口暴露出重布线结构422的最顶部金属化图案(例如，金属化图案426)的部分。可使用可接受的工艺来执行图案化，例如当介电层428是光敏性材料时通过将介电层428暴露于光，或者通过使用例如各向异性刻蚀进行刻蚀。
作为形成导电柱438的实例，可在重布线结构422之上(例如，在介电层428上及金属化图案426的被暴露出的部分上)形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可为单一层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层及钛层之上的铜层。晶种层可使用例如PVD等形成。然后可在晶种层上形成并图案化光刻胶。光刻胶可通过旋转涂布等形成，且可暴露于光以进行图案化。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中及晶种层的被暴露出的部分上形成导电材料。导电材料可通过镀覆(例如电镀或无电镀覆等)形成。导电材料可包括金属，如铜、钛、钨、铝等。移除光刻胶及晶种层的上面未形成导电材料的部分。可例如使用氧等离子体等通过可接受的灰化或剥除工艺移除光刻胶。一旦光刻胶被移除，便例如通过使用可接受的刻蚀工艺(例如通过湿刻蚀或干刻蚀)移除晶种层的被暴露出的部分。晶种层的剩余部分及导电材料形成导电柱438。在图4E中示出四个导电柱438，但在其他实施例中可形成更多或更少的导电柱438。在一些情形中，导电柱438可被认为是穿孔，例如绝缘层穿孔(through-insulation via，TIV)。
在图4F中，根据一些实施例，将附加存储器结构400(在图4F中被标记且有时被阐述为存储器结构400’)贴合到重布线结构422。附加存储器结构400’可例如是存储器堆叠450(参见图4H)的第二层存储器结构400。图4F所示的附加存储器结构400’可与先前贴合的存储器结构400相似或不同。在一些实施例中，如图4F至图4H所示，附加存储器结构400’或随后贴合的存储器结构可与先前贴合的存储器结构400分隔开不同的距离(例如，更大的距离)。附加存储器结构400’可以与先前贴合的存储器结构400相似的方式被贴合。例如，可使用可与先前在图4B中阐述的粘合剂418相似的粘合剂418将附加存储器结构400’贴合到重布线结构422。在贴合存储器结构400’之后，在存储器结构400’及导电柱438上以及周围形成包封体442。包封体442可与先前在图4C中阐述的包封体442相似。
在图4G中，在包封体442、存储器结构400及导电柱438之上形成第二重布线结构422(在图4G中被标记且有时被阐述为重布线结构422’)。第二重布线结构422’包括介电层424及428以及金属化图案426，且可与在图4D中阐述的重布线结构422相似。第二重布线结构422’可以与在图4D中阐述的重布线结构422相似的方式形成，且这些细节在此不再予以赘述。在一些实施例中，在形成第二重布线结构422’之前，对包封体442进行平坦化，以暴露出导电垫318及导电柱438。然后可形成第二重布线结构422’，以电连接到导电垫318及导电柱438。
图4H示出根据一些实施例形成附加层的存储器结构400、重布线结构422及导电柱438，以形成存储器堆叠450。在图4H中，在图4G所示第二重布线结构422’之上形成两个附加层的存储器结构400。这样一来，存储器堆叠450可被认为是堆叠式存储器结构。每一附加层的存储器结构400形成有相关联的重布线结构422及相关联的导电柱438。如图4H所示，导电柱438可交错，使得一层的导电柱438相对于相邻层的导电柱438横向偏移。在其他实施例中，存储器堆叠450可具有更少或更多层的存储器结构400以及相关联的重布线结构及/或导电柱438。附加存储器结构400、重布线结构422及导电柱438可与先前在图4B至图4G中阐述的那些相似。附加存储器结构400、重布线结构422及导电柱438可以与先前在图4B至图4G中阐述的那些相似的方式形成，且形成细节在此不再予以赘述。
仍参照图4H，形成用于外部连接到最顶部重布线结构422的凸块下金属(underbump metallurgy，UBM)446。UBM 446具有在最顶部介电层428的主表面上并沿着所述主表面延伸的凸块部分，且具有延伸穿过介电层428的通孔部分，以实体及电耦合最顶部重布线结构422的金属化图案426。因此，UBM 446电耦合到存储器堆叠450的多个重布线结构422及存储器结构400。在一些情形中，使用将周边装置100结合到存储器装置200的存储器结构400可容许存储器结构400之间及每一存储器结构400内具有更短的电连接，这可改善在操作期间存储器堆叠450的响应速度。UBM 446可由与金属化图案426相同的材料形成。在一些实施例中，UBM 446的大小与金属化图案426的大小不同。
仍参照图4H，在UBM 446上形成导电连接件448。导电连接件448可为球栅阵列(ball grid array，BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlledcollapse chip connection，C4)凸块、微凸块、无电镀镍钯浸金技术(electrolessnickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。导电连接件448可包含例如焊料、铜、铝、金、镍、银、钯、锡等或其组合等导电材料。在一些实施例中，通过利用蒸镀(evaporation)、电镀、印刷、焊料转移(solder transfer)、植球(ballplacement)等最初形成焊料层来形成导电连接件448。一旦已在结构上形成焊料层，便可执行回焊(reflow)以便将所述材料成形为所需凸块形状。在另一实施例中，导电连接件448包括通过溅镀(sputtering)、印刷、电镀、无电镀覆、CVD等而形成的金属柱(例如铜柱)。所述金属柱可为无焊料的且具有实质上垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属顶盖层(metal cap layer)。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，且可通过镀覆工艺来形成。在一些实施例中，可形成不电连接到最顶部重布线结构422的虚设UBM 446及虚设导电连接件448(图4H中未示出)，以在后续加工步骤期间提供稳定性。
如图4H所示，可执行剥离(de-bond)以使载体衬底402从介电层408脱离(或“剥离”)。根据一些实施例，剥离包括将例如激光或UV光等的光投射在释放层404上，使得释放层404在光的热量下分解，且载体衬底402可被移除。在一些实施例中，多个存储器堆叠450可形成在载体衬底402上，且然后被单体化以形成单独的存储器堆叠450。
图5A至图5E是根据一些实施例在用于形成存储器封装件500(参见图5E)的工艺期间的中间步骤的剖视图。在图5A至图5E中，将存储器堆叠(例如，存储器堆叠450)贴合到逻辑装置520以形成存储器封装件500。在一些实施例中，存储器封装件500包括高带宽存储器(HBM)堆叠，但应了解，实施例可应用于其他三维集成电路(3DIC)封装件、存储器封装件、晶片上芯片(CoW)封装件等。
在图5A中，提供载体衬底502，且在载体衬底502上形成释放层504。载体衬底502可为与先前针对载体衬底402(参见图4A)阐述的衬底相似的衬底。释放层504可为与先前针对释放层404(参见图4A)阐述的层相似的层。
根据一些实施例，将逻辑装置520放置在释放层504上，且可使用DAF等(未示出)将逻辑装置520贴合到释放层504。逻辑装置520可例如是逻辑管芯或包括多个逻辑装置520的逻辑晶片。根据其他实施例，逻辑装置520是另一种类型的装置或晶片，例如输入-输出晶片、中介层晶片等。逻辑装置520可例如包括中央处理器(Central Processing Unit，CPU)管芯、图形处理器(Graphic Processing Unit，GPU)管芯、应用处理器(ApplicationProcessor，AP)管芯、混合逻辑管芯、I/O管芯、与这些示例性管芯中的一者或多者相似操作的电路系统、其组合等。逻辑装置520包括衬底510、内连结构506及穿孔526。
衬底510可为块状半导体衬底、SOI衬底、多层式半导体衬底等。衬底510的半导体材料可为：硅、锗、包含硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟的化合物半导体；包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半导体；或者其组合。也可使用其他衬底，例如多层式或梯度衬底。衬底510可为经掺杂的或未掺杂的。装置508可形成在衬底510的表面处。装置508可包括有源装置(例如，晶体管、二极管等)及/或无源装置(例如，电容器、电阻器等)。
穿孔526被形成为从衬底510的表面延伸到衬底510中。当衬底510是硅衬底时，穿孔526有时也被称为衬底穿孔或硅穿孔(TSV)。穿孔526可通过例如刻蚀、铣削、激光技术、其组合等在衬底510中形成凹槽来形成。可例如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、其组合等在衬底510的前侧之上及开口中沉积薄阻挡层528。阻挡层528可由氧化物、氮化物或氮氧化物(例如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、氧化硅、其组合等)形成。可在薄阻挡层之上及开口中沉积导电材料，从而形成穿孔526。导电材料可通过电化学镀覆工艺、CVD、ALD、PVD、其组合等形成。导电材料的实例是铜、钨、铝、银、金及其组合等。可使用例如CMP工艺从衬底510的前侧移除多余的导电材料及阻挡层528。因此，穿孔526可包含导电材料，在所述导电材料与衬底510之间具有薄阻挡层528。
内连结构506形成在衬底510的表面之上，且用于将衬底510的装置508(如果有的话)及/或穿孔526电连接在一起及/或电连接到外部装置。内连结构506可形成在衬底510的与装置508相同的侧上。内连结构506可包括一个或多个介电层及介电层中的相应金属化图案。所述金属化图案可包括用以将任何装置及/或穿孔526内连在一起及/或内连到外部装置的通孔及/或迹线。介电层可由氧化硅、氮化硅、碳化硅、氮氧化硅、低介电常数介电材料(例如PSG、BPSG、掺氟的硅酸盐玻璃(fluorine-doped silicate glass，FSG)、碳氧化硅、旋涂玻璃(Spin-On-Glass)、旋涂聚合物(Spin-On-Polymer)、碳化硅材料、其化合物、其复合物、其组合等)形成。介电层可通过任何合适的方法(例如旋转涂布、CVD、PECVD、HDP-CVD等)沉积。金属化图案可例如通过以下形成在介电层中：使用光刻技术在介电层上沉积并图案化光刻胶材料，以暴露出介电层的将变为金属化图案的部分。可使用刻蚀工艺(例如各向异性干刻蚀工艺)在介电层中形成与介电层的被暴露出的部分对应的凹槽及/或开口。可给所述凹槽及/或开口衬砌扩散阻挡层并填充导电材料。扩散阻挡层可由一层或多层的氮化钽、钽、氮化钛、钛、钴钨、其组合等形成，且可通过ALD等沉积。导电材料可由铜、铝、钨、银、其组合等形成，且可通过CVD、PVD等沉积。可例如通过使用CMP工艺来移除介电层上的任何过量的扩散阻挡层及/或导电材料。
在图5B中，执行平坦化工艺以薄化逻辑装置520的衬底510并暴露出穿孔526。平坦化工艺可例如是研磨工艺或CMP工艺。
参考图5C，根据一些实施例，将存储器堆叠贴合到逻辑装置520。在图5C至图5E中，所示的存储器堆叠是如图4A至图4H中所阐述的存储器堆叠450，但在其他实施例中可使用其他存储器堆叠，例如以下在图6至图8中阐述的存储器堆叠等。存储器堆叠450的导电连接件448连接到逻辑装置520的穿孔526，因此在存储器堆叠450与逻辑装置520之间形成实体及电连接。在将导电连接件448放置在穿孔526上之后，可执行回焊工艺以将导电连接件448的材料结合到穿孔526。在一些实施例中，在贴合导电连接件448之前，可在穿孔526上形成焊料凸块等。
在图5D中，根据一些实施例，在存储器堆叠450上形成底部填充材料514及模塑材料516。底部填充材料514被施配在存储器堆叠450与逻辑装置520之间，使得底部填充材料514环绕导电连接件448。底部填充材料514可为任何可接受的材料，例如聚合物、环氧树脂、模塑底部填充剂等。在一些实施例中，可使用毛细管流动工艺(capillary flow process)来施配底部填充材料514。然后，在存储器堆叠450之上形成模塑材料516。模塑材料516可为包封体、模塑化合物、环氧树脂等，且可使用压缩模塑、转移模塑等来施加。模塑材料516可形成在存储器堆叠450之上，使得存储器堆叠450及底部填充材料514被掩埋或覆盖。随后可使模塑材料516固化。在一些实施例中，可执行平坦化工艺(例如，研磨或CMP工艺)以从存储器堆叠450之上移除多余的模塑材料516。在一些实施例中，平坦化工艺可暴露出介电层108，或者可移除存储器堆叠450的介电层108。
在图5E中，根据一些实施例，将载体衬底502剥离，且形成外部连接件524，从而形成存储器封装件500。如图5E所示，可执行剥离以使载体衬底502从逻辑装置520脱离(或“剥离”)。根据一些实施例，剥离包括将例如激光或UV光等的光投射在释放层504上，使得释放层504在光的热量下分解，且载体衬底502可被移除。
仍参照图5E，可形成用于与逻辑装置520的内连结构506外部连接的UBM 522。UBM522具有在内连结构506的主表面上并沿着所述主表面延伸的凸块部分，且可具有延伸穿过内连结构506的通孔部分。在UBM 522上形成外部连接件524。外部连接件524可为BGA连接件、焊料球、金属柱、C4凸块、微凸块、ENEPIG形成的凸块等。外部连接件524可包含例如焊料、铜、铝、金、镍、银、钯、锡等或者其组合等的导电材料。在一些实施例中，通过利用蒸镀、电镀、印刷、焊料转移、植球等最初形成焊料层来形成外部连接件524。一旦已在结构上形成焊料层，便可执行回焊，以将材料成形为所需凸块形状。在另一实施例中，外部连接件524包括通过溅镀、印刷、电镀、无电镀覆、CVD等而形成的金属柱(例如铜柱)。金属柱可为无焊料的，且具有实质上垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属顶盖层。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，且可通过镀覆工艺形成。
图6至图8示出根据一些实施例的存储器封装件600、700及800。存储器封装件600、700及800与图5E所示的存储器封装件500相似，只不过存储器封装件600、700及800中分别包括的存储器结构610、710及810具有不同的特征。图6至图8所示的存储器结构610、710及810旨在作为说明性实例，且示出的特征的变化或组合及/或未示出的其他特征旨涵盖于本公开的范围内。与先前阐述的存储器结构300及400相似，存储器结构610、710及810中的每一者包括将周边装置100结合到存储器装置200，且因此具有一些相似的优点，例如等待时间减少及高速操作改善。本公开中阐述的任何存储器结构可以任何合适的配置或组合用于本公开中阐述的任何存储器堆叠或存储器封装件中。
参考图6，所示的存储器封装件600包括具有存储器结构610的存储器堆叠650。存储器结构610与先前阐述的存储器结构300及400相似，只不过每一存储器结构610包括与存储器装置200大小相同的周边装置100。存储器结构610可通过例如在第一晶片上形成周边装置100并在第二晶片上形成存储器装置200且然后使用晶片间混合结合(wafer-to-waferhybrid bonding)等将周边装置100结合到存储器装置200来形成。这样一来，可消除与介电材料310(参见图3B)的形成相关联的工艺步骤。这可减少处理步骤的数目及存储器结构610的加工成本。
参考图7，所示的存储器封装件700包括具有存储器结构710的存储器堆叠750。存储器结构710与先前阐述的存储器结构300及400相似，只不过每一存储器结构710包括比存储器装置200大的周边装置100。存储器结构710可以与在图3A至图3F中阐述的方式相似的方式形成，只不过介电材料310可环绕较小的存储器装置200形成。换句话说，相对于存储器结构300，周边装置100与存储器装置200的位置相反。在一些实施例中，周边装置100可具有介于约15mm与约5mm之间的长度或宽度，且存储器装置200可具有介于约12mm与约3mm之间的长度或宽度。在一些实施例中，周边装置或处理器装置100的长度或宽度介于存储器装置200的对应长度或宽度的约300％与约100％之间。在一些实施例中，周边装置或处理器装置100的面积介于约25mm2与约225mm2之间，且存储器装置200的面积介于约9mm2与约144mm2之间。这样一来，本文阐述的工艺及存储器封装件可与具有不同尺寸或大小的周边装置100或存储器装置200一起使用。
参考图8，所示的存储器封装件800包括具有存储器结构810的存储器堆叠850。存储器结构810与先前阐述的存储器结构300及400相似，只不过每一存储器结构810除了周边装置100之外还包括结合到存储器装置200的装置820。装置820可为与周边装置100不同的周边装置或者不同类型的装置。例如，装置820可为集成无源装置(integrated passivedevice，IPD)、电压调节器、电容器、存储器装置、逻辑装置等、或者包括有源及/或无源组件的任何合适的装置。装置820可例如包括深沟槽电容器、金属-绝缘体-金属电容器、电感器、电阻器等或其组合。可在存储器结构内包括类型相似或不同的多于一个周边装置100或装置820。这样一来，存储器封装件可包括可使用不同技术形成的不同类型的装置。
参考图9，示出根据一些实施例的存储器封装件900。存储器封装件900与图5E所示的存储器封装件500相似，只不过所述存储器封装件除了逻辑装置520之外还包括贴合到内连结构506的装置920。装置920可为附加逻辑装置(与逻辑装置520相似或不同)、IPD、I/O装置等、或者包括有源及/或无源组件的任何合适的装置。装置920可例如包括深沟槽电容器、金属-绝缘体-金属电容器、电感器、电阻器等或其组合。在存储器封装件(例如存储器封装件900)内可包括相似或不同类型的多于一个装置920。在一些实施例中，可例如通过将逻辑装置520及装置920贴合到载体衬底(未示出)并通过模塑材料912进行包封来形成存储器封装件900。可对模塑材料912进行平坦化(例如通过CMP工艺)，并在逻辑装置520及装置920的前侧之上形成内连结构506，如先前在图5A中所述。可执行另一平坦化工艺以暴露出穿孔526，然后可在逻辑装置520及装置920的背侧之上形成第二内连结构906。第二内连结构906可以与内连结构506相似的方式形成，或者可使用不同的技术形成。内连结构506及/或第二内连结构906可电连接到装置920。在一些实施例中，可省略第二内连结构906。然后可以与在图5C中阐述的方式相似的方式来贴合存储器堆叠450。这样一来，可将多个装置及不同的装置并入到存储器封装件中。在一些情形中，如所阐述的那样并入多个装置可减小装置之间的电布线距离，这可减少存储器封装件的等待时间并改善存储器封装件的高速操作。
图10A至图10D是根据一些实施例在用于形成存储器封装件1000(参见图10D)的工艺期间的中间步骤的剖视图。在图10A至图10D中，将逻辑装置1020及1030贴合到存储器堆叠1050以形成存储器封装件1000。在一些实施例中，存储器封装件500包括高带宽存储器(HBM)堆叠，但应了解，实施例可应用于其他三维集成电路(3DIC)封装件、存储器封装件、晶片上芯片(CoW)封装件等。
参考图10A，示出根据一些实施例的存储器堆叠1050。存储器堆叠1050与图4H所示的存储器堆叠450相似，只不过UBM 446及导电连接件448未形成在最顶部重布线结构422上，且载体衬底402未被剥离。存储器堆叠1050可以与在图4A至图4H中针对存储器堆叠450阐述的工艺相似的工艺来形成。
在图10B中，根据一些实施例，形成导电柱1038。导电柱1038电连接到存储器堆叠1050的最顶部重布线结构422，且因此可电连接到存储器堆叠1050内的存储器结构。首先可对重布线结构422的最顶部介电层(例如，介电层428)进行图案化，以形成将重布线结构422的最顶部金属化图案(例如，金属化图案426)的部分暴露出的开口。图案化可使用可接受的工艺来执行，例如当介电层428是光敏性材料时通过将介电层428暴露于光，或者通过使用例如各向异性刻蚀进行刻蚀。
作为形成导电柱1038的实例，可在最顶部重布线结构422之上(例如，在介电层428上及金属化图案426的被暴露出的部分上)形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可为单一层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层及钛层之上的铜层。晶种层可使用例如PVD等形成。然后可在晶种层上形成并图案化光刻胶。光刻胶可通过旋转涂布等形成，且可暴露于光以进行图案化。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中及晶种层的被暴露出的部分上形成导电材料。导电材料可通过镀覆(例如电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。移除光刻胶及晶种层的上面未形成导电材料的部分。可例如使用氧等离子体等通过可接受的灰化或剥除工艺移除光刻胶。一旦光刻胶被移除，便例如通过使用可接受的刻蚀工艺(例如通过湿刻蚀或干刻蚀)移除晶种层的被暴露出的部分。晶种层的剩余部分及导电材料形成导电柱1038。在图10B中示出四个导电柱1038，但在其他实施例中可形成更多或更少的导电柱1038。在一些情形中，导电柱1038可被认为是穿孔，例如绝缘层穿孔(TIV)。
在图10C中，根据一些实施例，将逻辑装置1020及1030贴合到存储器堆叠1050(例如，贴合到最顶部重布线结构422)。逻辑装置1020及/或1030可为与以上关于逻辑装置520(参见图5A)阐述的装置相似的装置，或者可为与以上关于装置920(参见图9)阐述的装置相似的装置。逻辑装置1020可与逻辑装置1030相似或不同，且在其他实施例中可贴合多于两个逻辑装置。根据一些实施例，可使用DAF等(未示出)将逻辑装置1020及1030贴合到存储器堆叠1050。在一些实施例中，如图10C所示，逻辑装置1020或1030不包括穿孔。在其他实施例中，与图5A所示的逻辑装置520相似，逻辑装置1020或1030可包括穿孔。
在贴合逻辑装置1020及1030之后，在逻辑装置1020及1030以及导电柱1038之上及周围形成包封体1042。包封体1042可与例如先前在图4C中阐述的包封体442相似。在形成包封体1042之后，可执行平坦化工艺(例如，CMP工艺)以移除多余的包封体1042。在一些实施例中，平坦化工艺可暴露出导电柱1038，且可暴露出逻辑装置1020及1030的接触垫或其他导电特征(未示出)。
参考图10D，根据一些实施例，在逻辑装置1020及1030之上形成内连结构1006，且在内连结构1006上形成外部连接件1024，以形成存储器封装件1000。内连结构1006形成在逻辑装置1020及1030、导电柱1038以及包封体1042之上，且用于将逻辑装置1020及1030彼此电连接及/或电连接到存储器堆叠1050(通过导电柱1038)。在一些实施例中，内连结构1006可与内连结构506(参见图5A)相似且以相似的方式形成，或者内连结构1006可与重布线结构422(参见图4D)相似且以相似的方式形成。例如，内连结构1006可包括一个或多个介电层及介电层中的相应金属化图案，所述金属化图案可包括通孔及/或迹线。
仍参照图10D，可形成用于外部连接到内连结构1006的UBM 1022。UBM 1022具有在内连结构1006的主表面上并沿着所述主表面延伸的凸块部分，且可具有通孔部分。在UBM1022上形成外部连接件1024。外部连接件1024可为BGA连接件、焊料球、金属柱、C4凸块、微凸块、ENEPIG形成的凸块等。外部连接件1024可包含例如焊料、铜、铝、金、镍、银、钯、锡等或者其组合等的导电材料。在一些实施例中，通过利用蒸镀、电镀、印刷、焊料转移、植球等最初形成焊料层来形成外部连接件1024。一旦已在结构上形成焊料层，便可执行回焊，以将材料成形为所需凸块形状。在另一实施例中，外部连接件1024包括通过溅镀、印刷、电镀、无电镀覆、CVD等而形成的金属柱(例如铜柱)。金属柱可为无焊料的，且具有实质上垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属顶盖层。金属顶盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，且可通过镀覆工艺形成。在形成外部连接件1024之后，可对存储器封装件1000进行单体化，及/或可使用先前所述的技术来剥离载体衬底402。
如图10A至图10D所示，形成包括多个逻辑装置1020及1030的存储器封装件1000。并非使用例如焊料凸块将存储器堆叠1050结合到逻辑装置1020及1030，而是将逻辑装置1020及1030贴合到存储器堆叠1050。以此种方式形成存储器封装件可减少工艺步骤的数目或加工成本。另外，可将不同逻辑装置的功能组合在单一存储器封装件中，从而容许具有更大的设计弹性。
图11A及图11B示出根据一些实施例的封装结构1100及1200。封装结构1100及1200是并入有本公开中阐述的存储器封装件的封装结构的说明性实例。例如，封装结构1100并入有图9所示的存储器封装件900，而封装结构1200并入有图10D所示的存储器封装件1000。在其他封装结构中可使用其他存储器封装件，且封装结构及/或存储器封装件可存在其他配置。
如图11A及图11B所示，封装结构1100/1200的存储器封装件900/1000可贴合到中介层衬底1110。一个或多个装置管芯1102也可贴合到中介层衬底1110。装置管芯1102可包括逻辑管芯，所述逻辑管芯可为中央处理器(CPU)管芯、微控制单元(Micro Control Unit，MCU)管芯、输入/输出(I/O)管芯、基带(BaseBand，BB)管芯、应用处理器(AP)管芯等或者其组合。可环绕装置管芯1102及存储器封装件900/1000形成包封体1104。
视需要，可在装置管芯1102及存储器封装件900/1000之上形成散热器1106。散热器1106可由具有高导热性的材料(例如钢、不锈钢、铜等或其组合)形成。散热器1106保护封装结构1100/1200，并形成从封装结构1100/1200的各个组件传导热量的热路径。
中介层衬底1110可由例如硅、锗、玻璃等半导体材料制成。作为另一选择，也可使用化合物材料，例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、硅锗碳化物、镓砷磷化物、镓铟磷化物及其组合等。另外，中介层衬底1110可为SOI衬底，其可包含一层半导体材料，例如外延硅、锗、硅锗、SOI或其组合。在一个替代实施例中，中介层衬底1110是基于绝缘芯，例如玻璃纤维增强树脂芯(fiberglass reinforced resin core)。
中介层衬底1110可包括内连结构1114，装置管芯1102及存储器封装件900/1000可连接到内连结构1114。内连结构1114可包括金属化层及通孔，且可包括金属化层及通孔之上的结合垫。金属化层可被设计成连接封装结构1100/1200的各种装置以形成功能性电路系统，且可为重布线层。金属化层可由交替的介电层(例如低介电常数介电材料)及导电材料层(例如铜)以及将导电材料层内连的通孔形成，且可通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。
中介层衬底1110可包括有源及/或无源装置，在图11A及图11B中示出为装置1112。如所属领域中的普通技术人员将认识到，可使用各种各样的装置(例如晶体管、电容器、电阻器、其组合等)来满足封装结构1100/1200的结构性及功能性要求。例如，装置1112中的一者或多者可为集成无源装置(IPD)、电压调节器芯片等。装置1112可包括深沟槽电容器、金属/绝缘体/金属电容器、电感器、电阻器、后段工艺(back-end of line，BEOL)装置、金属线等或其组合。装置1112可使用任何合适的方法形成。装置1112可电连接到内连结构1114。在一些实施例中，中介层衬底1110实质上不含有源及无源装置。
在一些实施例中，中介层衬底1110可包括穿孔1118，穿孔1118将内连结构1114电连接到中介层衬底1110相对侧上的导电特征，例如附加内连结构、附加金属化层等。可环绕穿孔1118及装置1112形成包封体1116。封装结构1100/1200可通过导电连接件1122贴合到外部组件1120，导电连接件1122可为焊料球等。在一些实施例中，导电连接件1122可通过穿孔1118电连接到内连结构1114。
在上述实施例中，根据本公开的一些实施例论述了一些工艺及特征，以形成三维(3D)封装件。也可包括其他特征及工艺。例如，可包括测试结构，以帮助对3D封装或3DIC装置进行验证测试。测试结构可例如包括测试垫，所述测试垫在重布线层中、在内连结构中形成或在容许对3D封装或3DIC进行测试、容许使用探针及/或探针卡等的衬底上形成。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可与包括对已知良好管芯进行中间验证的测试方法一起使用，以提高良率并降低成本。
本公开的实施例具有一些有利的特征。通过在单独的衬底上形成存储器装置及周边装置并将其结合在一起以形成存储器结构，可减小存储器装置的组件与相关联周边装置的电路系统之间的布线距离。通过减小布线距离，可减少存储器结构的等待时间。这可改善使用存储器结构形成的存储器堆叠或存储器封装件的高速操作。另外，可使用不同的技术形成存储器装置及周边装置，且因此可针对特定应用来优化或调适每一类型的装置的设计或制造技术，这可进一步改善存储器结构的操作。存储器结构可包括呈不同组合的多个周边装置或其他类型的装置，以容许具有更弹性的设计。
根据本公开的一些实施例，一种方法包括：形成第一组存储器结构及第二组存储器结构，其中形成所述第一组存储器结构及所述第二组存储器结构中的每一存储器结构包括在第一衬底上形成包括存储器组件的第一装置、在第二衬底上形成第二装置、以及将所述第二装置结合到所述第一装置，以将所述第一装置电耦合到所述第二装置；形成存储器结构堆叠，包括将所述第一组存储器结构放置在载体上、在所述第一组存储器结构上形成电连接到所述第一组存储器结构的第一重布线结构、在所述第一重布线结构上形成电连接到所述第一重布线结构的第一组穿孔、以及将所述第二组存储器结构放置在所述第一重布线结构上；以及将所述存储器结构堆叠贴合到逻辑管芯。在实施例中，将所述第一装置结合到所述第二装置包括混合结合工艺。在实施例中，形成所述第一组存储器结构及所述第二组存储器结构中的每一存储器结构进一步包括：在将所述第一装置结合到所述第二装置之后，在所述第一装置上并环绕所述第二装置形成介电材料；以及形成延伸穿过所述介电材料的至少一个介电穿孔，其中所述至少一个介电穿孔电连接到所述第一装置。在实施例中，形成所述第一组存储器结构及所述第二组存储器结构中的每一存储器结构进一步包括：在第三衬底上形成第三装置；以及将所述第三装置结合到所述第一装置，以将所述第三装置电耦合到所述第一装置。在实施例中，所述第三装置包括集成无源装置(IPD)。在实施例中，所述第一装置具有与所述第二装置相同的横向尺寸。在实施例中，形成所述存储器结构堆叠进一步包括：在所述第二组存储器结构及所述第一组穿孔上形成电连接到所述第二组存储器结构及所述第一组穿孔的第二重布线结构；以及在所述第二重布线结构上形成电连接到所述第二重布线结构的第二组穿孔。在实施例中，所述第一装置的所述存储器组件包括DRAM组件。在实施例中，所述第一装置是使用DRAM工艺技术形成，且所述第二装置是使用CMOS工艺技术形成。
根据本公开的一些实施例，一种方法包括：形成堆叠式存储器装置，包括：将第一存储器结构放置在载体衬底上，所述第一存储器结构包括结合到第一逻辑管芯的第一存储器管芯，在所述第一存储器结构上形成第一重布线结构，其中所述第一重布线结构电连接到所述第一存储器结构，形成从所述第一重布线结构延伸的第一金属柱，其中所述第一金属柱电连接到所述第一重布线结构，将第二存储器结构邻近所述第一金属柱放置在所述第一重布线结构上，所述第二存储器结构包括结合到第二逻辑管芯的第二存储器管芯，在所述第二存储器结构及所述第一金属柱之上形成第二重布线结构，其中所述第二重布线结构电连接到所述第一金属柱，以及在所述第二重布线结构上形成外部连接件，其中所述外部连接件电连接到所述第二重布线结构；以及将所述堆叠式存储器装置贴合到第三逻辑管芯，其中所述堆叠式存储器装置的所述外部连接件电连接到所述第三逻辑管芯。在实施例中，所述方法进一步包括形成所述第一存储器结构，包括：将所述第一逻辑管芯的前表面结合到所述第一存储器管芯的前表面；以及在所述第一存储器管芯的所述前表面上形成介电材料；形成延伸穿过所述介电材料的穿孔，其中所述穿孔电连接到所述第一存储器管芯。在实施例中，所述方法进一步包括形成所述第二存储器结构，包括：将所述第二逻辑管芯的前表面结合到所述第二存储器管芯的前表面；在所述第二逻辑管芯的所述前表面上形成介电材料；以及形成延伸穿过所述介电材料的穿孔，其中所述穿孔电连接到所述第二逻辑管芯。在实施例中，所述第三逻辑管芯包括衬底穿孔，且其中所述堆叠式存储器装置的所述外部连接件贴合到所述衬底穿孔。在实施例中，形成堆叠式存储器装置进一步包括在所述第一金属柱及所述第一存储器结构之上并环绕所述第一金属柱及所述第一存储器结构形成包封体。在实施例中，所述方法进一步包括将第三存储器结构放置在所述载体衬底上。
根据本公开的一些实施例，一种封装件包括贴合到逻辑装置的存储器堆叠，所述存储器堆叠包括：多个第一存储器结构；第一重布线层，位于所述第一存储器结构之上并电连接到所述多个第一存储器结构；多个第二存储器结构，位于所述第一重布线层上；第二重布线层，位于所述第二存储器结构之上并电连接到所述第二存储器结构；以及多个第一金属柱，位于所述第一重布线层上并邻近所述多个第二存储器结构，所述多个第一金属柱电连接所述第一重布线层与所述第二重布线层；其中所述第一存储器结构中的每一第一存储器结构包括：存储器管芯，包括第一接触垫；以及周边电路系统管芯，包括第二接触垫，其中所述存储器管芯的所述第一接触垫结合到所述周边电路系统管芯的所述第二接触垫。在实施例中，所述存储器管芯是MRAM存储器管芯。在实施例中，所述周边电路系统管芯的横向面积小于所述存储器管芯的横向面积。在实施例中，所述第一存储器结构中的每一第一存储器结构进一步包括环绕所述周边电路系统管芯的介电材料及延伸穿过所述介电材料以与所述存储器管芯的第一接触垫接触的介电穿孔(TDV)。在实施例中，所述第一金属柱及所述第二存储器结构被模塑材料环绕并分隔开。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应了解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，且可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。
[符号的说明]
100：周边装置/处理器装置
102：半导体衬底/衬底
104、204、508、820、920、1112：装置
106、206、316、426：金属化图案
108、208：结合垫
110、210、506、1006、1114：内连结构
112：穿孔/衬底穿孔(TSV)
113：衬里
200：存储器装置
202、510：衬底
222：磁性隧道结(MTJ)
250：底部接触金属/位线
252：顶部金属触点
254：堆叠电容器
256：字线
300、400、400’、610、710、810：存储器结构
310：介电材料
312：介电穿孔(TDV)
313：隔离层
314：绝缘层
318：导电垫
320：钝化层
402、502：载体衬底
404、504：释放层
408：介电层/电介质
418：粘合剂
422：重布线结构
422’：重布线结构/第二重布线结构
424、428：介电层
438、1038：导电柱
442、1042、1104、1116：包封体
446、522、1022：凸块下金属(UBM)
448、1122：导电连接件
450、650、750、850、1050：存储器堆叠
500、600、700、800、900、1000：存储器封装件
514：底部填充材料
516、912：模塑材料
520、1020、1030：逻辑装置
524、1024：外部连接件
526、1118：穿孔
528：阻挡层
906：第二内连结构
1100、1200：封装结构
1102：装置管芯
1106：散热器
1110：中介层衬底
1120：外部组件

Claims (1)

1.一种方法，包括：
形成第一组存储器结构及第二组存储器结构，其中形成所述第一组存储器结构及所述第二组存储器结构中的每一存储器结构包括：
在第一衬底上形成包括存储器组件的第一装置；
在第二衬底上形成第二装置；以及
将所述第二装置结合到所述第一装置，以将所述第一装置电耦合到所述第二装置；
形成存储器结构堆叠，包括：
将所述第一组存储器结构放置在载体上；
在所述第一组存储器结构上形成电连接到所述第一组存储器结构的第一重布线结构；
在所述第一重布线结构上形成电连接到所述第一重布线结构的第一组穿孔；以及
将所述第二组存储器结构放置在所述第一重布线结构上；以及
将所述存储器结构堆叠贴合到逻辑管芯。
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