TW202129913A - 記憶體封裝件及其形成方法 - Google Patents

記憶體封裝件及其形成方法 Download PDF

Info

Publication number
TW202129913A
TW202129913A TW109111681A TW109111681A TW202129913A TW 202129913 A TW202129913 A TW 202129913A TW 109111681 A TW109111681 A TW 109111681A TW 109111681 A TW109111681 A TW 109111681A TW 202129913 A TW202129913 A TW 202129913A
Authority
TW
Taiwan
Prior art keywords
memory
layer
conductive
die
rewiring
Prior art date
Application number
TW109111681A
Other languages
English (en)
Inventor
余振華
蔡仲豪
王垂堂
奕 王
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202129913A publication Critical patent/TW202129913A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/80048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/80379—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

一種封裝件包括貼合到邏輯裝置的記憶體堆疊，所述記憶體堆疊包括：多個第一記憶體結構；第一重佈線層，位於所述第一記憶體結構之上並電連接到所述多個第一記憶體結構；多個第二記憶體結構，位於所述第一重佈線層上；第二重佈線層，位於所述第二記憶體結構之上並電連接到所述第二記憶體結構；以及多個第一金屬柱，位於所述第一重佈線層上並鄰近所述多個第二記憶體結構，所述多個第一金屬柱電連接所述第一重佈線層與所述第二重佈線層；其中所述第一記憶體結構中的每一第一記憶體結構包括：記憶體晶粒，包括第一接觸墊；以及周邊電路系統晶粒，包括第二接觸墊，其中所述記憶體晶粒的所述第一接觸墊接合到所述周邊電路系統晶粒的所述第二接觸墊。

Description

記憶體封裝件及其形成方法
本揭露實施例是有關於記憶體封裝件及其形成方法。
高性能計算（High-Performance Computing，HPC）系統通常包括接合到邏輯晶粒的高頻寬記憶體（High-Bandwidth-Memory，HBM）堆疊。HBM堆疊通常包括堆疊在一起的多個記憶體晶粒，其中較高的記憶體晶粒通過焊料接合或利用微凸塊實現的金屬直接接合而接合到較低的記憶體晶粒。在記憶體晶粒中形成有矽穿孔（Through-Silicon Via，TSV），使得上部晶粒可通過TSV電連接到邏輯晶粒。
根據本發明的一些實施例，一種方法包括：形成第一組記憶體結構及第二組記憶體結構，其中形成所述第一組記憶體結構及所述第二組記憶體結構中的每一記憶體結構包括在第一基底上形成包括記憶體元件的第一裝置、在第二基底上形成第二裝置、以及將所述第二裝置接合到所述第一裝置，以將所述第一裝置電耦合到所述第二裝置；形成記憶體結構堆疊，包括將所述第一組記憶體結構放置在載體上、在所述第一組記憶體結構上形成電連接到所述第一組記憶體結構的第一重佈線結構、在所述第一重佈線結構上形成電連接到所述第一重佈線結構的第一組穿孔、以及將所述第二組記憶體結構放置在所述第一重佈線結構上；以及將所述記憶體結構堆疊貼合到邏輯晶粒。
根據本發明的一些實施例，一種方法包括：形成堆疊式記憶體裝置，包括：將第一記憶體結構放置在載體基底上，所述第一記憶體結構包括接合到第一邏輯晶粒的第一記憶體晶粒，在所述第一記憶體結構上形成第一重佈線結構，其中所述第一重佈線結構電連接到所述第一記憶體結構，形成從所述第一重佈線結構延伸的第一金屬柱，其中所述第一金屬柱電連接到所述第一重佈線結構，將第二記憶體結構鄰近所述第一金屬柱放置在所述第一重佈線結構上，所述第二記憶體結構包括接合到第二邏輯晶粒的第二記憶體晶粒，在所述第二記憶體結構及所述第一金屬柱之上形成第二重佈線結構，其中所述第二重佈線結構電連接到所述第一金屬柱，以及在所述第二重佈線結構上形成外部連接件，其中所述外部連接件電連接到所述第二重佈線結構；以及將所述堆疊式記憶體裝置貼合到第三邏輯晶粒，其中所述堆疊式記憶體裝置的所述外部連接件電連接到所述第三邏輯晶粒。
根據本發明的一些實施例，一種封裝件包括貼合到邏輯裝置的記憶體堆疊，所述記憶體堆疊包括：多個第一記憶體結構；第一重佈線層，位於所述第一記憶體結構之上並電連接到所述多個第一記憶體結構；多個第二記憶體結構，位於所述第一重佈線層上；第二重佈線層，位於所述第二記憶體結構之上並電連接到所述第二記憶體結構；以及多個第一金屬柱，位於所述第一重佈線層上並鄰近所述多個第二記憶體結構，所述多個第一金屬柱電連接所述第一重佈線層與所述第二重佈線層；其中所述第一記憶體結構中的每一第一記憶體結構包括：記憶體晶粒，包括第一接觸墊；以及周邊電路系統晶粒，包括第二接觸墊，其中所述記憶體晶粒的所述第一接觸墊接合到所述周邊電路系統晶粒的所述第二接觸墊。
以下公開內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及構造的具體實例以簡化本發明。當然，這些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在……之下（underlying）”、“在……下面（below）”、“下部的（lower）”、“上覆在……上（overlying）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據各種實施例，提供包括記憶體結構堆疊的記憶體封裝件及其形成方法。根據一些實施例，示出在形成記憶體堆疊時的中間階段。論述了一些實施例的一些變化。在所有各視圖及說明性實施例中，相同的參考編號用於標示相同的元件。根據本發明的一些實施例，記憶體結構包括記憶體裝置（例如，記憶體晶粒），所述記憶體裝置接合（hybrid-bonded）到周邊裝置（例如，另一晶粒）。例如，記憶體裝置可被混合接合到周邊裝置。通過將周邊裝置接合到記憶體裝置，可減小周邊裝置與記憶體裝置之間的電繞線距離，這可減少延遲時間（latency）並改善操作速度。另外，記憶體裝置及周邊裝置可使用不同的技術或製程單獨地形成。
應瞭解，將關於特定上下文（即包括接合到裝置晶粒的記憶體晶粒的晶粒堆疊）來闡述實施例。所論述實施例的概念也可應用於其他結構的結構及製程，包括但不限於邏輯晶粒堆疊、輸入輸出（input-output，I/O）晶粒堆疊或包括混合的邏輯晶粒、I/O晶粒、記憶體晶粒等的晶粒堆疊的形成。本文中所論述的實施例是為了提供能夠製作或使用本發明主題的實例，且所屬領域中的普通技術人員將容易理解在不同實施例的預期範圍內可進行的修改。下圖中相同的參考編號及字元指代相同的元件。儘管方法實施例可被論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1、圖2A、圖2B及圖3A至圖3F示出根據本發明一些實施例在形成記憶體結構300時的中間階段的剖視圖。圖1示出根據一些實施例的周邊裝置100，且圖2A及圖2B示出根據一些實施例的記憶體裝置200。圖3A至圖3F示出由周邊裝置100及記憶體裝置200形成記憶體結構300。可使用除所示技術或製程階段之外的技術或製程階段來形成記憶體結構300。所示的周邊裝置100、記憶體裝置200及記憶體結構300是說明性實例，且在不悖離本發明的範圍的條件下，其他實施例可具有除所示配置或特徵之外的配置或特徵。例如，在圖6至圖8所示的實施例中示出具有不同配置的一些記憶體結構。
圖1示出根據一些實施例的周邊裝置100。周邊裝置100可例如是積體電路晶粒、晶圓、封裝件或與記憶體裝置200介接的其他裝置。周邊裝置100可例如包括與記憶體結構300中的記憶體裝置200進行通信或控制記憶體裝置200操作的邏輯電路、控制電路、I/O電路、測試電路等。圖1中所示的周邊裝置100可例如在晶圓中形成，所述晶圓可包括在後續步驟中被單體化以形成多個周邊裝置的不同裝置區。可根據適用於形成周邊裝置的製造製程來製程周邊裝置100。例如，周邊裝置100包括半導體基底102，半導體基底102可包含例如經摻雜矽或未摻雜矽等材料、或者絕緣體上半導體（SOI）基底的主動層。半導體基底102可包含：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。也可使用其他基底，例如多層式或梯度基底。半導體基底102具有有時被稱為前側的主動表面（例如，圖1中面朝上的表面）以及有時被稱為背側的非主動表面（例如，圖1中面朝下的表面）。
裝置104可形成在半導體基底102的前表面處。裝置104可包括主動裝置（例如，電晶體、二極體等）及/或被動裝置（例如，電容器、電阻器等）。內連結構110形成在基底102及裝置104之上，且可包括介電層、金屬化圖案106（例如，金屬線、通孔等）等等。介電層可包括低介電常數（低k）介電層及/或非低介電常數介電層。在一些實施例中，內連結構110的一個或多個介電層由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合及/或其多層體形成。內連結構110的金屬化圖案106電耦合到裝置104以形成周邊裝置100。金屬化圖案106可由鎢、鈷、鎳、銅、銀、金、鋁等或其組合形成。金屬化圖案106可使用合適的製程（例如雙鑲嵌製程（dual damascene process）或另一製程）形成。
在一些實施例中，周邊裝置100包括延伸穿過半導體基底102並進入內連結構110的穿孔（有時稱為基底穿孔（Through-Substrate Via，TSV））112。例如，TSV 112可延伸穿過半導體基底102，且電連接到內連結構110的金屬化圖案106。在一些實施例中，一個或多個TSV 112可延伸穿過內連結構110，且電連接到內連結構110的接觸墊108（以下闡述）。TSV 112可由襯裡113環繞。圖1中示出一個TSV 112，但在其他實施例中可存在多於一個TSV 112。在其他實施例中，周邊裝置100不包括TSV 112。
周邊裝置100更包括在內連結構110中形成的接合墊108。接合墊108可由利於混合接合（hybrid bonding）的金屬（例如銅、銅合金或另一種合適的金屬）形成。接合墊108電連接到金屬化圖案106及/或TSV 112，或者接合墊108可為金屬化圖案106的一部分。接合墊108可與內連結構110的頂表面共面。內連結構110的頂表面可為介電材料，例如氧化矽。圖1中示出一個接合墊108，但在其他實施例中可存在多於一個接合墊108。
參考圖2A及圖2B，示出記憶體裝置200的兩個實施例。記憶體裝置200可包括不同類型的記憶體技術，例如動態隨機存取記憶體（DRAM）、靜態隨機存取記憶體（SRAM）、磁性隨機存取記憶體（MRAM）或其他類型的記憶體技術。例如，圖2A示出包括DRAM的記憶體裝置200，而圖2B示出包括MRAM的記憶體裝置200。記憶體裝置200可包括基底202及在基底202的前表面處形成的裝置204。在一些實施例中，記憶體裝置200可為記憶體晶粒、包括記憶體組件的積體電路晶粒等。裝置204可包括主動裝置（例如，電晶體、二極體等）及/或被動裝置（例如，電容器、電阻器等）。使用不同類型記憶體技術的記憶體裝置可包括不同的記憶體組件。例如，根據一些實施例，圖2A所示的DRAM記憶體裝置200的記憶體元件包括連接到頂部金屬觸點252及底部接觸金屬250的堆疊電容器254。根據一些實施例，底部接觸金屬250用作位元線。在一些實施例中，字元線256可形成在基底202中。做為另一實例，根據一些實施例，圖2B所示的MRAM記憶體裝置200的記憶體元件包括連接到字元線256及位元元線250的磁性隧道接面（magnetic tunnel junction，MTJ）222。在一些實施例中，MRAM記憶體裝置200的字元線256或位元線250可為以下所述的內連結構210的金屬化圖案206。圖2A及圖2B所示的記憶體裝置200是說明性實例，且可存在其他類型或配置的記憶體裝置200。
內連結構210形成在基底202及裝置204之上，且可包括介電層、金屬化圖案206（例如，金屬線、通孔等）等等。在一些實施例中，記憶體的元件（例如，堆疊電容器254或其他元件）可形成在內連結構210內。介電層可包括低介電常數介電層及/或非低介電常數介電層。在一些實施例中，內連結構210的一個或多個介電層由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合及/或其多層體形成。內連結構210的金屬化圖案206電耦合到裝置204及記憶體元件，以形成記憶體裝置200。金屬化圖案206可由鎢、鈷、鎳、銅、銀、金、鋁等或其組合形成。金屬化圖案206可使用合適的製程（例如雙鑲嵌製程或另一製程）形成。
記憶體裝置200更包括形成在內連結構210中的接合墊208。接合墊208可由利於混合接合的金屬（例如銅、銅合金或另一種合適的金屬）形成。接合墊208電連接到金屬化圖案206，或者接合墊208可為金屬化圖案206的一部分。接合墊208可與內連結構210的頂表面共面。內連結構210的頂表面可為介電材料，例如氧化矽。圖2A及圖2B中示出兩個接合墊208，但在其他實施例中可存在一個接合墊208或者多於兩個接合墊208。
圖3A至圖3F是根據一些實施例在用於形成記憶體結構300（參見圖3E）的製程期間的中間步驟的剖視圖。圖3A至圖3F中所示的製程是說明性實例，且可例如示出完整記憶體結構300、完整記憶體結構300的一部分或者隨後被單體化的數個記憶體結構300之一的形成。記憶體結構300的其他配置涵蓋在本發明的範圍內。在圖3A中，將周邊裝置100接合到記憶體裝置200。周邊裝置100與記憶體裝置200的接合部分在圖3A至圖3F中以虛線表示。
在一些實施例中，可使用例如混合接合技術將周邊裝置100接合到記憶體裝置200。例如，可將周邊裝置100的一個或多個接合墊108接合到記憶體裝置200的接合墊208，且可將周邊裝置100的內連結構110的頂表面接合到記憶體裝置200的內連結構210的頂表面。在執行接合之前，可對周邊裝置100及/或記憶體裝置200執行表面處理。表面處理可例如是電漿處理製程，且用於產生電漿的製程氣體可為含氫氣體，所述含氫氣體包括包含氫（H2 ）及氬（Ar）的第一氣體、包含H2 及氮（N2 ）的第二氣體或者包含H2 及氦（He）的第三氣體。通過所述處理，可增加周邊裝置100的及記憶體裝置200的表面處OH基團的數目。接下來，可執行預接合製程，其中將周邊裝置100與記憶體裝置200對準。將周邊裝置100與記憶體裝置200壓靠在一起，以在周邊裝置100的內連結構110的頂表面與記憶體裝置200的內連結構210的頂表面之間形成弱接合。在預接合製程之後，執行退火以加強所述弱接合並形成熔融接合（fusion bond）。在退火期間，OH鍵的H被除氣，從而在內連結構110與內連結構210之間形成Si-O-Si鍵，從而加強所述接合。在混合接合期間，在周邊裝置100的接合墊108與記憶體裝置200的接合墊208之間也發生直接金屬間（metal-to-metal）接合。因此，所得的接合是包括Si-O-Si鍵及金屬間直接接合的混合接合。
通過將周邊裝置100接合到記憶體裝置200，可減小周邊裝置100與記憶體裝置200之間的繞線距離，這可減少延遲時間並改善高頻操作。例如，與在與記憶體裝置200相同的基底202上形成周邊裝置100的裝置104相比，繞線距離可減小。在一些實施例中，用於形成周邊裝置100的製程技術可不同於用於形成記憶體裝置200的製程技術。例如，周邊裝置100可使用用於形成互補金屬氧化物半導體的製程（“CMOS製程”）來形成，而記憶體裝置200可使用用於形成DRAM的製程（“DRAM製程”）來形成。此為實例，且在其他實施例中可使用其他類型的製程。這樣一來，可使用特定製程技術來優化周邊裝置100的形成或配置，且可使用不同的特定製程技術來優化記憶體裝置200的形成或配置。通過使用適當的製程形成不同的周邊裝置100及記憶體裝置200，可形成具有改善性能的記憶體結構300。
在一些實施例中，可將多於一個周邊裝置100接合到記憶體裝置200，且所述多於一個周邊裝置100可包括相似及/或不同的周邊裝置。在一些實施例中，周邊裝置100的長度或寬度可小於記憶體裝置200的對應長度或寬度，如圖3A所示。在一些實施例中，周邊裝置100可具有介於約12mm與約3mm之間的長度或寬度，而記憶體裝置200可具有介於約15mm與約5mm之間的長度或寬度。在一些實施例中，周邊裝置100可具有介於記憶體裝置200的對應長度或寬度的約30%與約100%之間的長度或寬度。在一些實施例中，周邊裝置100可具有介於約9mm2 與約144mm2 之間的面積，且記憶體裝置200可具有介於約25mm2 與約225mm2 之間的面積。這樣一來，可以各種佈置形式組合多種大小及形狀的裝置以形成記憶體結構300，這容許例如針對特定應用具有大的設計彈性。
參考圖3B，根據一些實施例，在周邊裝置100及記憶體裝置200之上形成介電材料310。在一些實施例中，介電材料310包括例如氧化矽等的氧化物，其可例如使用原矽酸四乙酯（TEOS）或另一種技術形成。介電材料310可使用例如化學氣相沉積（CVD）、高密度電漿化學氣相沉積（HDPCVD）等來形成。根據其他實施例，介電材料310由例如聚苯並惡唑（polybenzoxazole，PBO）、聚醯亞胺等聚合物形成。可執行平坦化製程以移除介電材料310的多餘部分，以便暴露出周邊裝置100，這可暴露出周邊裝置100的TSV 112。平坦化製程可包括研磨製程、化學機械研磨（CMP）製程等。
圖3C示出介電穿孔（Through-Dielectric Via，TDV）312的形成，TDV 312延伸穿過介電材料310並與記憶體裝置200形成電連接。可通過蝕穿介電材料310以形成通孔開口且然後用導電材料填充通孔開口來形成TDV 312。蝕刻可例如包括非等向性乾蝕刻製程。在一些實施例中，所述蝕刻暴露出接合墊208。在一些實施例中，可使用接合墊208做為蝕刻停止層來執行蝕刻。在一些實施例中，TDV 312由同質導電材料形成，所述同質導電材料可包括金屬或金屬合金，包括銅、鋁、鎢等。根據本發明的其他實施例，TDV 312包括複合結構，所述複合結構包括由鈦、氮化鈦、鉭、氮化鉭等形成的導電阻擋層以及所述阻擋層之上的含金屬材料。TDV 312的形成可包括將導電材料沉積到通孔開口中，且然後執行平坦化製程以移除介電材料310及周邊裝置100之上所沉積導電材料的多餘部分。在圖3C至圖3E中示出一個TDV 312，但在其他實施例中可存在多於一個TDV 312。
參考圖3D，在介電材料310之上形成金屬化圖案316以形成與TDV 312的電連接，且在周邊裝置100之上形成金屬化圖案316以形成與TSV 112的電連接。在一些實施例中，在形成金屬化圖案316之前，可在介電材料310及周邊裝置100之上形成隔離層313。隔離層313可為一層氧化物、氮化物等，且可被形成為防止金屬化圖案316的導電材料擴散到介電材料310或周邊裝置100中。金屬化圖案316可通過以下來形成：形成毯覆晶種層（未示出），形成並圖案化鍍覆罩幕（例如光阻）以露出金屬晶種層的與金屬化圖案316對應的部分，在鍍覆罩幕的開口中鍍覆導電材料，移除鍍覆罩幕，且蝕刻晶種層的先前由鍍覆罩幕覆蓋的部分。根據本發明的一些實施例，晶種層包括鈦層及鈦層之上的銅層。晶種層的形成可例如包括物理氣相沉積（PVD）製程或另一種合適的製程。在一些實施例中，所鍍覆材料包括銅或銅合金。鍍覆可例如包括電化學鍍覆製程或無電鍍覆製程。
仍參照圖3D，在介電材料310、周邊裝置100及金屬化圖案316之上形成絕緣層314。在一些實施例中，絕緣層314可包括一個或多個低介電常數介電層及/或非低介電常數介電層。例如，絕緣層314可包含例如氧化矽、氮化矽、碳化矽、氮氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻硼的磷矽酸鹽玻璃（BPSG）、其組合等絕緣材料，且可使用CVD、PVD、原子層沉積（ALD）、旋轉塗布製程、其組合等來形成。在其他實施例中，絕緣層314可包括一層或多層例如聚苯並惡唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合等的絕緣材料，且可使用旋轉塗布製程等來形成。在一些實施例中，例如使用CMP製程對絕緣層314進行平坦化。
參考圖3E，根據一些實施例，形成導電墊318及鈍化層320，從而形成記憶體結構300。在一些實施例中，在絕緣層314中形成開口以暴露出金屬化圖案316的區。絕緣層314中的開口可使用合適的技術來形成，例如，在絕緣層314之上形成經圖案化光阻層，然後使用經圖案化光阻層做為蝕刻罩幕來蝕刻絕緣層314。
在一些實施例中，可通過以下來形成導電墊318：首先在絕緣層314之上及絕緣層314中的開口內形成晶種層（未示出），且然後形成並圖案化鍍覆罩幕（例如光阻）以露出晶種層的與導電墊318對應的部分。可使用鍍覆製程在鍍覆罩幕的開口中形成導電墊318的導電材料，移除鍍覆罩幕，且通過蝕刻而移除金屬晶種層的先前被鍍覆罩幕覆蓋的部分。晶種層可包含銅、鈦、鎳、金、鈀等或其組合。
導電墊318可使用其他技術來形成。例如，可將導電墊318的導電材料沉積為毯覆層，且然後使用合適的微影及蝕刻製程進行圖案化以形成導電墊318。可通過電化學鍍覆製程、無電鍍覆製程、CVD、ALD、PVD等或其組合來形成導電墊318的導電材料。在一些實施例中，導電墊318的導電材料包括銅、鎢、鋁、銀、金等或其組合。在一些實施例中，一些導電墊318可為用於對記憶體結構300進行電測試的測試墊。
根據一些實施例，在形成導電墊318之後，在絕緣層314及導電墊318之上形成鈍化層320。鈍化層320可包括一個或多個低介電常數介電層及/或非低介電常數介電層。例如，鈍化層320可包含例如氧化矽、氮化矽、碳化矽、氮氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻硼的磷矽酸鹽玻璃（BPSG）、其組合等絕緣材料，且可使用CVD、PVD、ALD、旋轉塗布製程、其組合等來形成。在其他實施例中，鈍化層320可包括一層或多層例如聚苯並惡唑（PBO）、聚醯亞胺（PI）、苯並環丁烯（BCB）、其組合等的絕緣材料，且可使用旋轉塗布製程等來形成。在一些實施例中，如圖3E所示，可在鈍化層320中蝕刻開口以暴露出導電墊318。在其他實施例中，使用例如CMP製程對鈍化層320進行平坦化以暴露出導電墊318。
如圖3A至圖3F所示，通過在兩個不同的基底上形成記憶體裝置200及其相關聯的周邊裝置100並將其接合在一起以形成記憶體結構300，周邊裝置100的電路系統可更靠近記憶體裝置200的元件放置。這樣一來，可減小繞線距離，且可改善記憶體結構300的一些操作特性，例如延遲時間。在一些實施例中，可在單個基底202上形成多個記憶體裝置200，且在其上形成多個記憶體結構300。然後，可使用例如合適的鋸切製程或其他切割製程將所述多個記憶體結構300單體化成單獨的記憶體結構300。
圖4A至圖4H是根據一些實施例在用於形成記憶體堆疊450（參見圖4H）的製程期間的中間步驟的剖視圖。在圖4A至圖4H中，堆疊多個記憶體結構（例如，記憶體結構400），並在其間形成電連接（例如，重佈線結構422或導電柱438，參見圖4D至圖4H），以形成記憶體堆疊450。應瞭解，記憶體結構及/或電連接的類型、數目、配置或佈置可不同於本發明的各圖中所示的那些，且所有這些變化等均涵蓋在本發明的範圍內。在一些實施例中，記憶體堆疊450是高頻寬記憶體（HBM）堆疊，但應瞭解，實施例可應用於其他三維積體電路（three-dimensional integrated circuit，3DIC）封裝件、記憶體封裝件、晶圓上晶片（chip-on-wafer，CoW）封裝件等。
在圖4A中，提供載體基底402，並在載體基底402上形成釋放層404。載體基底402可為玻璃載體基底、陶瓷載體基底等。載體基底402可為晶圓、面板等，使得多個封裝件可同時形成在載體基底402上。釋放層404可由聚合物系材料形成，所述聚合物系材料可與載體基底402一起從將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層404是在受熱時會失去其黏合性質的環氧樹脂系熱釋放材料，例如光/熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，釋放層404可為紫外（ultra-violet，UV）膠，其在被暴露於UV光時會失去其黏合性質。釋放層404可做為液體進行施配並進行固化，可為被積層到載體基底402上的積層體膜（laminate film），或可為類似形式。釋放層404的頂表面可為平整的（leveled），且可具有高平面度（degree of planarity）。
在釋放層404上可形成可選的介電層408。介電層408的底表面可與釋放層404的頂表面接觸。在一些實施例中，介電層408由例如聚苯並惡唑、聚醯亞胺、苯並環丁烯（BCB）等聚合物形成。在其他實施例中，介電層408由以下形成：例如氮化矽等氮化物；例如氧化矽等氧化物、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻硼的磷矽酸鹽玻璃（BPSG）等；或者類似物。介電層408可通過任何可接受的沉積製程（例如旋轉塗布、CVD、積層等或者其組合）形成。
在圖4B中，通過黏合劑418將記憶體結構400黏附到介電層408。在圖4B至圖4H所示的實施例中，所示的記憶體結構400與先前在圖3E與圖3F中闡述的記憶體結構300相似，只不過每一記憶體結構400包括兩個周邊裝置100，所述兩個周邊裝置100可為每一記憶體結構400內不同類型的周邊裝置。每一記憶體結構400中的周邊裝置100之一還包括完全延伸穿過其的TSV 112。圖4B至圖4H所示的記憶體結構400是說明性實例，且其他實施例可包括與所示記憶體結構不同的記憶體結構。另外，為了清楚起見，圖4B至圖4H所示的記憶體結構400的一些特徵已被省略或簡化。在一些實施例中，可將比所示更多或更少的記憶體結構400黏附到電介質408。記憶體結構400可例如是記憶體堆疊450的第一層記憶體結構400（參見圖4H）。
黏合劑418形成在記憶體結構400的背側上，並將記憶體結構400黏附到載體基底402，例如黏附到介電層408。黏合劑418可為任何合適的黏合劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）等。黏合劑418可被施加到記憶體結構400的背側，或者可被施加在載體基底402之上。例如，黏合劑418可在分離單獨的記憶體結構400的單體化製程之前施加到記憶體結構400的背側。
在圖4C中，在各種元件上及周圍形成包封體442。在形成之後，包封體442包封記憶體結構400。包封體442可為模塑化合物、環氧樹脂等。包封體442可通過壓縮模塑（compression molding）、轉移模塑（transfer molding）等施加，且可形成在載體基底402之上，以掩埋或覆蓋記憶體結構400。包封體442更形成在記憶體結構400之間的間隙區中。包封體442可以液體或半液體形式施加，且然後進行固化。
仍參照圖4C，對包封體442執行平坦化製程。在一些實施例中，平坦化製程可移除每一記憶體結構400的鈍化層320的部分，以暴露出每一記憶體結構400的導電墊318，如圖4C所示。在一些實施例中，平坦化製程不暴露出導電墊318，且執行合適的微影及蝕刻製程以在鈍化層320中形成暴露出導電墊318的開口。在平坦化製程之後，導電墊318的、鈍化層320的及包封體442的頂表面可為共面的。平坦化製程可例如是化學機械研磨（CMP）、研磨製程等。在一些實施例中，例如，若導電墊318已被暴露出，則可省略平坦化。
在圖4D中，在包封體442及記憶體結構400之上形成重佈線結構422。重佈線結構422包括介電層424及428以及金屬化圖案426。金屬化圖案也可被稱為重佈線層或重佈線。重佈線結構422被示為具有單一金屬化圖案的實例。可在重佈線結構422中或其他重佈線結構（例如圖4G至圖4H所示的重佈線結構422中的任一者或本發明中所提及的其他重佈線結構）中形成更多或更少的介電層及金屬化圖案。若將形成更少的介電層及金屬化圖案，則可省略以下論述的步驟及製程。若將形成更多的介電層及金屬化圖案，則可重複以下論述的步驟及製程。
在圖4D中，在包封體442及記憶體結構400上沉積介電層424。在一些實施例中，介電層424由例如PBO、聚醯亞胺、BCB等感光性材料形成，所述感光性材料可使用微影罩幕進行圖案化。介電層424可通過旋轉塗布、積層、CVD等或其組合來形成。然後對介電層424進行圖案化。所述圖案化會形成將導電墊318的部分暴露出的開口。圖案化可通過可接受的製程進行，例如當介電層424為感光性材料時通過將介電層424暴露於光，或者通過使用例如非等向性蝕刻製程進行蝕刻。若介電層424為感光性材料，則可在曝光之後將介電層424顯影。
然後形成金屬化圖案426。金屬化圖案426包括在介電層424的主表面上並沿著所述主表面延伸的線部分（也稱為導電線）。金屬化圖案426更包括延伸穿過介電層424的通孔部分（也稱為導電通孔），以將記憶體結構400實體及電耦合到隨後形成的結構。做為形成金屬化圖案426的實例，在介電層424之上及延伸穿過介電層424的開口中形成晶種層。在一些實施例中，晶種層是金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及鈦層之上的銅層。晶種層可使用例如PVD等形成。然後在晶種層上形成並圖案化光阻。光阻可通過旋轉塗布等形成，且可暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案426。所述圖案化會形成穿過光阻的開口以暴露出晶種層。然後在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。導電材料可通過鍍覆（例如電鍍或無電鍍覆等）形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。導電材料與晶種層的下伏部分的組合形成金屬化圖案426。移除光阻及晶種層的上面未形成導電材料的部分。光阻可例如使用氧電漿等通過可接受的灰化或剝除製程移除。一旦光阻被移除，便例如通過使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）移除晶種層的被暴露出的部分。
在圖4E中，根據一些實施例，形成導電柱438。導電柱438電連接到重佈線結構422，且因此可電連接到記憶體結構400。可首先對重佈線結構422的最頂部介電層（例如，介電層428）進行圖案化，以形成開口，開口暴露出重佈線結構422的最頂部金屬化圖案（例如，金屬化圖案426）的部分。可使用可接受的製程來執行圖案化，例如當介電層428為感光性材料時通過將介電層428暴露於光，或者通過使用例如非等向性蝕刻進行蝕刻。
做為形成導電柱438的實例，可在重佈線結構422之上（例如，在介電層428上及金屬化圖案426的被暴露出的部分上）形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及鈦層之上的銅層。晶種層可使用例如PVD等形成。然後可在晶種層上形成並圖案化光阻。光阻可通過旋轉塗布等形成，且可暴露於光以進行圖案化。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。導電材料可通過鍍覆（例如電鍍或無電鍍覆等）形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻及晶種層的上面未形成導電材料的部分。可例如使用氧電漿等通過可接受的灰化或剝除製程移除光阻。一旦光阻被移除，便例如通過使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）移除晶種層的被暴露出的部分。晶種層的剩餘部分及導電材料形成導電柱438。在圖4E中示出四個導電柱438，但在其他實施例中可形成更多或更少的導電柱438。在一些情形中，導電柱438可被認為是穿孔，例如絕緣層穿孔（through-insulation via，TIV）。
在圖4F中，根據一些實施例，將附加記憶體結構400（在圖4F中被標記且有時被闡述為記憶體結構400’）貼合到重佈線結構422。附加記憶體結構400’可例如是記憶體堆疊450（參見圖4H）的第二層記憶體結構400。圖4F所示的附加記憶體結構400’可與先前貼合的記憶體結構400相似或不同。在一些實施例中，如圖4F至圖4H所示，附加記憶體結構400’或隨後貼合的記憶體結構可與先前貼合的記憶體結構400分隔開不同的距離（例如，更大的距離）。附加記憶體結構400’可以與先前貼合的記憶體結構400相似的方式被貼合。例如，可使用可與先前在圖4B中闡述的黏合劑418相似的黏合劑418將附加記憶體結構400’貼合到重佈線結構422。在貼合記憶體結構400’之後，在記憶體結構400’及導電柱438上以及周圍形成包封體442。包封體442可與先前在圖4C中闡述的包封體442相似。
在圖4G中，在包封體442、記憶體結構400及導電柱438之上形成第二重佈線結構422（在圖4G中被標記且有時被闡述為重佈線結構422’）。第二重佈線結構422’包括介電層424及428以及金屬化圖案426，且可與在圖4D中闡述的重佈線結構422相似。第二重佈線結構422’可以與在圖4D中闡述的重佈線結構422相似的方式形成，且這些細節在此不再予以贅述。在一些實施例中，在形成第二重佈線結構422’之前，對包封體442進行平坦化，以暴露出導電墊318及導電柱438。然後可形成第二重佈線結構422’，以電連接到導電墊318及導電柱438。
圖4H示出根據一些實施例形成附加層的記憶體結構400、重佈線結構422及導電柱438，以形成記憶體堆疊450。在圖4H中，在圖4G所示第二重佈線結構422’之上形成兩個附加層的記憶體結構400。這樣一來，記憶體堆疊450可被認為是堆疊式記憶體結構。每一附加層的記憶體結構400形成有相關聯的重佈線結構422及相關聯的導電柱438。如圖4H所示，導電柱438可交錯，使得一層的導電柱438相對於相鄰層的導電柱438橫向偏移。在其他實施例中，記憶體堆疊450可具有更少或更多層的記憶體結構400以及相關聯的重佈線結構及/或導電柱438。附加記憶體結構400、重佈線結構422及導電柱438可與先前在圖4B至圖4G中闡述的那些相似。附加記憶體結構400、重佈線結構422及導電柱438可以與先前在圖4B至圖4G中闡述的那些相似的方式形成，且形成細節在此不再予以贅述。
仍參照圖4H，形成用於外部連接到最頂部重佈線結構422的凸塊下金屬（under bump metallurgy，UBM）446。UBM 446具有在最頂部介電層428的主表面上並沿著所述主表面延伸的凸塊部分，且具有延伸穿過介電層428的通孔部分，以實體及電耦合最頂部重佈線結構422的金屬化圖案426。因此，UBM 446電耦合到記憶體堆疊450的多個重佈線結構422及記憶體結構400。在一些情形中，使用將周邊裝置100接合到記憶體裝置200的記憶體結構400可容許記憶體結構400之間及每一記憶體結構400內具有更短的電連接，這可改善在操作期間記憶體堆疊450的回應速度。UBM 446可由與金屬化圖案426相同的材料形成。在一些實施例中，UBM 446的大小與金屬化圖案426的大小不同。
仍參照圖4H，在UBM 446上形成導電連接件448。導電連接件448可為球柵陣列（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件448可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合等導電材料。在一些實施例中，通過利用蒸鍍（evaporation）、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）等最初形成焊料層來形成導電連接件448。一旦已在結構上形成焊料層，便可執行回焊（reflow）以便將所述材料成形為所需凸塊形狀。在另一實施例中，導電連接件448包括通過濺鍍（sputtering）、印刷、電鍍、無電鍍覆、CVD等而形成的金屬柱（例如銅柱）。所述金屬柱可為無焊料的且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層（metal cap layer）。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且可通過鍍覆製程來形成。在一些實施例中，可形成不電連接到最頂部重佈線結構422的虛設UBM 446及虛設導電連接件448（圖4H中未示出），以在後續製程步驟期間提供穩定性。
如圖4H所示，可執行剝離（de-bond）以使載體基底402從介電層408脫離（或“剝離”）。根據一些實施例，剝離包括將例如鐳射或UV光等的光投射在釋放層404上，使得釋放層404在光的熱量下分解，且載體基底402可被移除。在一些實施例中，多個記憶體堆疊450可形成在載體基底402上，且然後被單體化以形成單獨的記憶體堆疊450。
圖5A至圖5E是根據一些實施例在用於形成記憶體封裝件500（參見圖5E）的製程期間的中間步驟的剖視圖。在圖5A至圖5E中，將記憶體堆疊（例如，記憶體堆疊450）貼合到邏輯裝置520以形成記憶體封裝件500。在一些實施例中，記憶體封裝件500包括高頻寬記憶體（HBM）堆疊，但應瞭解，實施例可應用於其他三維積體電路（3DIC）封裝件、記憶體封裝件、晶圓上晶片（CoW）封裝件等。
在圖5A中，提供載體基底502，且在載體基底502上形成釋放層504。載體基底502可為與先前針對載體基底402（參見圖4A）闡述的基底相似的基底。釋放層504可為與先前針對釋放層404（參見圖4A）闡述的層相似的層。
根據一些實施例，將邏輯裝置520放置在釋放層504上，且可使用DAF等（未示出）將邏輯裝置520貼合到釋放層504。邏輯裝置520可例如是邏輯晶粒或包括多個邏輯裝置520的邏輯晶圓。根據其他實施例，邏輯裝置520是另一種類型的裝置或晶圓，例如輸入-輸出晶圓、中介層晶圓等。邏輯裝置520可例如包括中央處理器（Central Processing Unit，CPU）晶粒、圖形處理器（Graphic Processing Unit，GPU）晶粒、應用處理器（Application Processor，AP）晶粒、混合邏輯晶粒、I/O晶粒、與這些示例性晶粒中的一者或多者相似操作的電路系統、其組合等。邏輯裝置520包括基底510、內連結構506及穿孔526。
基底510可為塊狀半導體基底、SOI基底、多層式半導體基底等。基底510的半導體材料可為：矽、鍺、包含矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體；包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半導體；或者其組合。也可使用其他基底，例如多層式或梯度基底。基底510可為經摻雜的或未摻雜的。裝置508可形成在基底510的表面處。裝置508可包括主動裝置（例如，電晶體、二極體等）及/或被動裝置（例如，電容器、電阻器等）。
穿孔526被形成為從基底510的表面延伸到基底510中。當基底510是矽基底時，穿孔526有時也被稱為基底穿孔或矽穿孔（TSV）。穿孔526可通過例如蝕刻、銑削、雷射技術、其組合等在基底510中形成凹槽來形成。可例如通過CVD、原子層沉積（ALD）、物理氣相沉積（PVD）、熱氧化、其組合等在基底510的前側之上及開口中沉積薄阻擋層528。阻擋層528可由氧化物、氮化物或氮氧化物（例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、氧化矽、其組合等）形成。可在薄阻擋層之上及開口中沉積導電材料，從而形成穿孔526。導電材料可通過電化學鍍覆製程、CVD、ALD、PVD、其組合等形成。導電材料的實例是銅、鎢、鋁、銀、金及其組合等。可使用例如CMP製程從基底510的前側移除多餘的導電材料及阻擋層528。因此，穿孔526可包含導電材料，在所述導電材料與基底510之間具有薄阻擋層528。
內連結構506形成在基底510的表面之上，且用於將基底510的裝置508（若有的話）及/或穿孔526電連接在一起及/或電連接到外部裝置。內連結構506可形成在基底510的與裝置508相同的側上。內連結構506可包括一個或多個介電層及介電層中的相應金屬化圖案。所述金屬化圖案可包括用以將任何裝置及/或穿孔526內連在一起及/或內連到外部裝置的通孔及/或跡線。介電層可由氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料（例如PSG、BPSG、摻氟的矽酸鹽玻璃（fluorine-doped silicate glass，FSG）、碳氧化矽、旋塗玻璃（Spin-On-Glass）、旋塗聚合物（Spin-On-Polymer）、碳化矽材料、其化合物、其複合物、其組合等）形成。介電層可通過任何合適的方法（例如旋轉塗布、CVD、PECVD、HDP-CVD等）沉積。金屬化圖案可例如通過以下形成在介電層中：使用微影技術在介電層上沉積並圖案化光阻材料，以暴露出介電層的將變為金屬化圖案的部分。可使用蝕刻製程（例如非等向性乾蝕刻製程）在介電層中形成與介電層的被暴露出的部分對應的凹槽及/或開口。可給所述凹槽及/或開口襯砌擴散阻擋層並填充導電材料。擴散阻擋層可由一層或多層的氮化鉭、鉭、氮化鈦、鈦、鈷鎢、其組合等形成，且可通過ALD等沉積。導電材料可由銅、鋁、鎢、銀、其組合等形成，且可通過CVD、PVD等沉積。可例如通過使用CMP製程來移除介電層上的任何過量的擴散阻擋層及/或導電材料。
在圖5B中，執行平坦化製程以薄化邏輯裝置520的基底510並暴露出穿孔526。平坦化製程可例如是研磨製程或CMP製程。
參考圖5C，根據一些實施例，將記憶體堆疊貼合到邏輯裝置520。在圖5C至圖5E中，所示的記憶體堆疊是如圖4A至圖4H中所闡述的記憶體堆疊450，但在其他實施例中可使用其他記憶體堆疊，例如以下在圖6至圖8中闡述的記憶體堆疊等。記憶體堆疊450的導電連接件448連接到邏輯裝置520的穿孔526，因此在記憶體堆疊450與邏輯裝置520之間形成實體及電連接。在將導電連接件448放置在穿孔526上之後，可執行回焊製程以將導電連接件448的材料接合到穿孔526。在一些實施例中，在貼合導電連接件448之前，可在穿孔526上形成焊料凸塊等。
在圖5D中，根據一些實施例，在記憶體堆疊450上形成底部填充材料514及模塑材料516。底部填充材料514被施配在記憶體堆疊450與邏輯裝置520之間，使得底部填充材料514環繞導電連接件448。底部填充材料514可為任何可接受的材料，例如聚合物、環氧樹脂、模塑底部填充劑等。在一些實施例中，可使用毛細管流動製程（capillary flow process）來施配底部填充材料514。然後，在記憶體堆疊450之上形成模塑材料516。模塑材料516可為包封體、模塑化合物、環氧樹脂等，且可使用壓縮模塑、轉移模塑等來施加。模塑材料516可形成在記憶體堆疊450之上，使得記憶體堆疊450及底部填充材料514被掩埋或覆蓋。隨後可使模塑材料516固化。在一些實施例中，可執行平坦化製程（例如，研磨或CMP製程）以從記憶體堆疊450之上移除多餘的模塑材料516。在一些實施例中，平坦化製程可暴露出介電層108，或者可移除記憶體堆疊450的介電層108。
在圖5E中，根據一些實施例，將載體基底502剝離，且形成外部連接件524，從而形成記憶體封裝件500。如圖5E所示，可執行剝離以使載體基底502從邏輯裝置520脫離（或“剝離”）。根據一些實施例，剝離包括將例如鐳射或UV光等的光投射在釋放層504上，使得釋放層504在光的熱量下分解，且載體基底502可被移除。
仍參照圖5E，可形成用於與邏輯裝置520的內連結構506外部連接的UBM 522。UBM 522具有在內連結構506的主表面上並沿著所述主表面延伸的凸塊部分，且可具有延伸穿過內連結構506的通孔部分。在UBM 522上形成外部連接件524。外部連接件524可為BGA連接件、焊料球、金屬柱、C4凸塊、微凸塊、ENEPIG形成的凸塊等。外部連接件524可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或者其組合等的導電材料。在一些實施例中，通過利用蒸鍍、電鍍、印刷、焊料轉移、植球等最初形成焊料層來形成外部連接件524。一旦已在結構上形成焊料層，便可執行回焊，以將材料成形為所需凸塊形狀。在另一實施例中，外部連接件524包括通過濺鍍、印刷、電鍍、無電鍍覆、CVD等而形成的金屬柱（例如銅柱）。金屬柱可為無焊料的，且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且可通過鍍覆製程形成。
圖6至圖8示出根據一些實施例的記憶體封裝件600、700及800。記憶體封裝件600、700及800與圖5E所示的記憶體封裝件500相似，只不過記憶體封裝件600、700及800中分別包括的記憶體結構610、710及810具有不同的特徵。圖6至圖8所示的記憶體結構610、710及810旨在做為說明性實例，且示出的特徵的變化或組合及/或未示出的其他特徵旨涵蓋於本發明的範圍內。與先前闡述的記憶體結構300及400相似，記憶體結構610、710及810中的每一者包括將周邊裝置100接合到記憶體裝置200，且因此具有一些相似的優點，例如延遲時間減少及高速操作改善。本發明中闡述的任何記憶體結構可以任何合適的配置或組合用於本發明中闡述的任何記憶體堆疊或記憶體封裝件中。
參考圖6，所示的記憶體封裝件600包括具有記憶體結構610的記憶體堆疊650。記憶體結構610與先前闡述的記憶體結構300及400相似，只不過每一記憶體結構610包括與記憶體裝置200大小相同的周邊裝置100。記憶體結構610可通過例如在第一晶圓上形成周邊裝置100並在第二晶圓上形成記憶體裝置200且然後使用晶圓間混合接合（wafer-to-wafer hybrid bonding）等將周邊裝置100接合到記憶體裝置200來形成。這樣一來，可消除與介電材料310（參見圖3B）的形成相關聯的製程步驟。這可減少處理步驟的數目及記憶體結構610的製程成本。
參考圖7，所示的記憶體封裝件700包括具有記憶體結構710的記憶體堆疊750。記憶體結構710與先前闡述的記憶體結構300及400相似，只不過每一記憶體結構710包括比記憶體裝置200大的周邊裝置100。記憶體結構710可以與在圖3A至圖3F中闡述的方式相似的方式形成，只不過介電材料310可環繞較小的記憶體裝置200形成。換句話說，相對於記憶體結構300，周邊裝置100與記憶體裝置200的位置相反。在一些實施例中，周邊裝置100可具有介於約15mm與約5mm之間的長度或寬度，且記憶體裝置200可具有介於約12mm與約3mm之間的長度或寬度。在一些實施例中，周邊裝置或處理器裝置100的長度或寬度介於記憶體裝置200的對應長度或寬度的約300%與約100%之間。在一些實施例中，周邊裝置或處理器裝置100的面積介於約25mm2與約225mm2之間，且記憶體裝置200的面積介於約9mm2與約144mm2之間。這樣一來，本文闡述的製程及記憶體封裝件可與具有不同尺寸或大小的周邊裝置100或記憶體裝置200一起使用。
參考圖8，所示的記憶體封裝件800包括具有記憶體結構810的記憶體堆疊850。記憶體結構810與先前闡述的記憶體結構300及400相似，只不過每一記憶體結構810除了周邊裝置100之外還包括接合到記憶體裝置200的裝置820。裝置820可為與周邊裝置100不同的周邊裝置或者不同類型的裝置。例如，裝置820可為積體被動裝置（integrated passive device，IPD）、電壓調節器、電容器、記憶體裝置、邏輯裝置等、或者包括主動及/或被動元件的任何合適的裝置。裝置820可例如包括深溝槽電容器、金屬-絕緣體-金屬電容器、電感器、電阻器等或其組合。可在記憶體結構內包括類型相似或不同的多於一個周邊裝置100或裝置820。這樣一來，記憶體封裝件可包括可使用不同技術形成的不同類型的裝置。
參考圖9，示出根據一些實施例的記憶體封裝件900。記憶體封裝件900與圖5E所示的記憶體封裝件500相似，只不過所述記憶體封裝件除了邏輯裝置520之外還包括貼合到內連結構506的裝置920。裝置920可為附加邏輯裝置（與邏輯裝置520相似或不同）、IPD、I/O裝置等、或者包括主動及/或被動元件的任何合適的裝置。裝置920可例如包括深溝槽電容器、金屬-絕緣體-金屬電容器、電感器、電阻器等或其組合。在記憶體封裝件（例如記憶體封裝件900）內可包括相似或不同類型的多於一個裝置920。在一些實施例中，可例如通過將邏輯裝置520及裝置920貼合到載體基底（未示出）並通過模塑材料912進行包封來形成記憶體封裝件900。可對模塑材料912進行平坦化（例如通過CMP製程），並在邏輯裝置520及裝置920的前側之上形成內連結構506，如先前在圖5A中所述。可執行另一平坦化製程以暴露出穿孔526，然後可在邏輯裝置520及裝置920的背側之上形成第二內連結構906。第二內連結構906可以與內連結構506相似的方式形成，或者可使用不同的技術形成。內連結構506及/或第二內連結構906可電連接到裝置920。在一些實施例中，可省略第二內連結構906。然後可以與在圖5C中闡述的方式相似的方式來貼合記憶體堆疊450。這樣一來，可將多個裝置及不同的裝置併入到記憶體封裝件中。在一些情形中，如所闡述的那樣併入多個裝置可減小裝置之間的電繞線距離，這可減少記憶體封裝件的延遲時間並改善記憶體封裝件的高速操作。
圖10A至圖10D是根據一些實施例在用於形成記憶體封裝件1000（參見圖10D）的製程期間的中間步驟的剖視圖。在圖10A至圖10D中，將邏輯裝置1020及1030貼合到記憶體堆疊1050以形成記憶體封裝件1000。在一些實施例中，記憶體封裝件500包括高頻寬記憶體（HBM）堆疊，但應瞭解，實施例可應用於其他三維積體電路（3DIC）封裝件、記憶體封裝件、晶圓上晶片（CoW）封裝件等。
參考圖10A，示出根據一些實施例的記憶體堆疊1050。記憶體堆疊1050與圖4H所示的記憶體堆疊450相似，只不過UBM 446及導電連接件448未形成在最頂部重佈線結構422上，且載體基底402未被剝離。記憶體堆疊1050可以與在圖4A至圖4H中針對記憶體堆疊450闡述的製程相似的製程來形成。
在圖10B中，根據一些實施例，形成導電柱1038。導電柱1038電連接到記憶體堆疊1050的最頂部重佈線結構422，且因此可電連接到記憶體堆疊1050內的記憶體結構。首先可對重佈線結構422的最頂部介電層（例如，介電層428）進行圖案化，以形成將重佈線結構422的最頂部金屬化圖案（例如，金屬化圖案426）的部分暴露出的開口。圖案化可使用可接受的製程來執行，例如當介電層428為感光性材料時通過將介電層428暴露於光，或者通過使用例如非等向性蝕刻進行蝕刻。
做為形成導電柱1038的實例，可在最頂部重佈線結構422之上（例如，在介電層428上及金屬化圖案426的被暴露出的部分上）形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及鈦層之上的銅層。晶種層可使用例如PVD等形成。然後可在晶種層上形成並圖案化光阻。光阻可通過旋轉塗布等形成，且可暴露於光以進行圖案化。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。導電材料可通過鍍覆（例如電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻及晶種層的上面未形成導電材料的部分。可例如使用氧電漿等通過可接受的灰化或剝除製程移除光阻。一旦光阻被移除，便例如通過使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）移除晶種層的被暴露出的部分。晶種層的剩餘部分及導電材料形成導電柱1038。在圖10B中示出四個導電柱1038，但在其他實施例中可形成更多或更少的導電柱1038。在一些情形中，導電柱1038可被認為是穿孔，例如絕緣層穿孔（TIV）。
在圖10C中，根據一些實施例，將邏輯裝置1020及1030貼合到記憶體堆疊1050（例如，貼合到最頂部重佈線結構422）。邏輯裝置1020及/或1030可為與以上關於邏輯裝置520（參見圖5A）闡述的裝置相似的裝置，或者可為與以上關於裝置920（參見圖9）闡述的裝置相似的裝置。邏輯裝置1020可與邏輯裝置1030相似或不同，且在其他實施例中可貼合多於兩個邏輯裝置。根據一些實施例，可使用DAF等（未示出）將邏輯裝置1020及1030貼合到記憶體堆疊1050。在一些實施例中，如圖10C所示，邏輯裝置1020或1030不包括穿孔。在其他實施例中，與圖5A所示的邏輯裝置520相似，邏輯裝置1020或1030可包括穿孔。
在貼合邏輯裝置1020及1030之後，在邏輯裝置1020及1030以及導電柱1038之上及周圍形成包封體1042。包封體1042可與例如先前在圖4C中闡述的包封體442相似。在形成包封體1042之後，可執行平坦化製程（例如，CMP製程）以移除多餘的包封體1042。在一些實施例中，平坦化製程可暴露出導電柱1038，且可暴露出邏輯裝置1020及1030的接觸墊或其他導電特徵（未示出）。
參考圖10D，根據一些實施例，在邏輯裝置1020及1030之上形成內連結構1006，且在內連結構1006上形成外部連接件1024，以形成記憶體封裝件1000。內連結構1006形成在邏輯裝置1020及1030、導電柱1038以及包封體1042之上，且用於將邏輯裝置1020及1030彼此電連接及/或電連接到記憶體堆疊1050（通過導電柱1038）。在一些實施例中，內連結構1006可與內連結構506（參見圖5A）相似且以相似的方式形成，或者內連結構1006可與重佈線結構422（參見圖4D）相似且以相似的方式形成。例如，內連結構1006可包括一個或多個介電層及介電層中的相應金屬化圖案，所述金屬化圖案可包括通孔及/或跡線。
仍參照圖10D，可形成用於外部連接到內連結構1006的UBM 1022。UBM 1022具有在內連結構1006的主表面上並沿著所述主表面延伸的凸塊部分，且可具有通孔部分。在UBM 1022上形成外部連接件1024。外部連接件1024可為BGA連接件、焊料球、金屬柱、C4凸塊、微凸塊、ENEPIG形成的凸塊等。外部連接件1024可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或者其組合等的導電材料。在一些實施例中，通過利用蒸鍍、電鍍、印刷、焊料轉移、植球等最初形成焊料層來形成外部連接件1024。一旦已在結構上形成焊料層，便可執行回焊，以將材料成形為所需凸塊形狀。在另一實施例中，外部連接件1024包括通過濺鍍、印刷、電鍍、無電鍍覆、CVD等而形成的金屬柱（例如銅柱）。金屬柱可為無焊料的，且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且可通過鍍覆製程形成。在形成外部連接件1024之後，可對記憶體封裝件1000進行單體化，及/或可使用先前所述的技術來剝離載體基底402。
如圖10A至圖10D所示，形成包括多個邏輯裝置1020及1030的記憶體封裝件1000。並非使用例如焊料凸塊將記憶體堆疊1050接合到邏輯裝置1020及1030，而是將邏輯裝置1020及1030貼合到記憶體堆疊1050。以此種方式形成記憶體封裝件可減少製程步驟的數目或製程成本。另外，可將不同邏輯裝置的功能組合在單一記憶體封裝件中，從而容許具有更大的設計彈性。
圖11A及圖11B示出根據一些實施例的封裝結構1100及1200。封裝結構1100及1200是併入有本發明中闡述的記憶體封裝件的封裝結構的說明性實例。例如，封裝結構1100併入有圖9所示的記憶體封裝件900，而封裝結構1200併入有圖10D所示的記憶體封裝件1000。在其他封裝結構中可使用其他記憶體封裝件，且封裝結構及/或記憶體封裝件可存在其他配置。
如圖11A及圖11B所示，封裝結構1100/1200的記憶體封裝件900/1000可貼合到中介層基底1110。一個或多個裝置晶粒1102也可貼合到中介層基底1110。裝置晶粒1102可包括邏輯晶粒，所述邏輯晶粒可為中央處理器（CPU）晶粒、微控制單元（Micro Control Unit，MCU）晶粒、輸入/輸出（I/O）晶粒、基頻（BaseBand，BB）晶粒、應用處理器（AP）晶粒等或者其組合。可環繞裝置晶粒1102及記憶體封裝件900/1000形成包封體1104。
視需要，可在裝置晶粒1102及記憶體封裝件900/1000之上形成散熱器1106。散熱器1106可由具有高導熱性的材料（例如鋼、不銹鋼、銅等或其組合）形成。散熱器1106保護封裝結構1100/1200，並形成從封裝結構1100/1200的各個元件傳導熱量的熱路徑。
中介層基底1110可由例如矽、鍺、玻璃等半導體材料製成。做為另一選擇，也可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、鎵砷磷化物、鎵銦磷化物及其組合等。另外，中介層基底1110可為SOI基底，其可包含一層半導體材料，例如磊晶矽、鍺、矽鍺、SOI或其組合。在一個替代實施例中，中介層基底1110是基於絕緣芯，例如玻璃纖維增強樹脂芯（fiber glass reinforced resin core）。
中介層基底1110可包括內連結構1114，裝置晶粒1102及記憶體封裝件900/1000可連接到內連結構1114。內連結構1114可包括金屬化層及通孔，且可包括金屬化層及通孔之上的接合墊。金屬化層可被設計成連接封裝結構1100/1200的各種裝置以形成功能性電路系統，且可為重佈線層。金屬化層可由交替的介電層（例如低介電常數介電材料）及導電材料層（例如銅）以及將導電材料層內連的通孔形成，且可通過任何合適的製程（例如沉積、鑲嵌、雙鑲嵌等）形成。
中介層基底1110可包括主動及/或被動裝置，在圖11A及圖11B中示出為裝置1112。如所屬領域中的普通技術人員將認識到，可使用各種各樣的裝置（例如電晶體、電容器、電阻器、其組合等）來滿足封裝結構1100/1200的結構性及功能性要求。例如，裝置1112中的一者或多者可為積體被動裝置（IPD）、電壓調節器晶圓等。裝置1112可包括深溝槽電容器、金屬-絕緣體-金屬電容器、電感器、電阻器、後段製程（BEOL）裝置、金屬線等或其組合。裝置1112可使用任何合適的方法形成。裝置1112可電連接到內連結構1114。在一些實施例中，中介層基底1110實質上不含主動及被動裝置。
在一些實施例中，中介層基底1110可包括穿孔1118，穿孔1118將內連結構1114電連接到中介層基底1110相對側上的導電特徵，例如附加內連結構、附加金屬化層等。可環繞穿孔1118及裝置1112形成包封體1116。封裝結構1100/1200可通過導電連接件1122貼合到外部元件1120，導電連接件1122可為焊料球等。在一些實施例中，導電連接件1122可通過穿孔1118電連接到內連結構1114。
在上述實施例中，根據本發明的一些實施例論述了一些製程及特徵，以形成三維（3D）封裝件。也可包括其他特徵及製程。例如，可包括測試結構，以説明對3D封裝或3DIC裝置進行驗證測試。測試結構可例如包括測試墊，所述測試墊在重佈線層中、在內連結構中形成或在容許對3D封裝或3DIC進行測試、容許使用探針及/或探針卡等的基底上形成。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包括對已知良好晶粒進行中間驗證的測試方法一起使用，以提高良率並降低成本。
本發明的實施例具有一些有利的特徵。通過在單獨的基底上形成記憶體裝置及周邊裝置並將其接合在一起以形成記憶體結構，可減小記憶體裝置的元件與相關聯周邊裝置的電路系統之間的繞線距離。通過減小繞線距離，可減少記憶體結構的延遲時間。這可改善使用記憶體結構形成的記憶體堆疊或記憶體封裝件的高速操作。另外，可使用不同的技術形成記憶體裝置及周邊裝置，且因此可針對特定應用來優化或調適每一類型的裝置的設計或製造技術，這可更改善記憶體結構的操作。記憶體結構可包括呈不同組合的多個周邊裝置或其他類型的裝置，以容許具有更彈性的設計。
根據本發明的一些實施例，一種方法包括：形成第一組記憶體結構及第二組記憶體結構，其中形成所述第一組記憶體結構及所述第二組記憶體結構中的每一記憶體結構包括在第一基底上形成包括記憶體元件的第一裝置、在第二基底上形成第二裝置、以及將所述第二裝置接合到所述第一裝置，以將所述第一裝置電耦合到所述第二裝置；形成記憶體結構堆疊，包括將所述第一組記憶體結構放置在載體上、在所述第一組記憶體結構上形成電連接到所述第一組記憶體結構的第一重佈線結構、在所述第一重佈線結構上形成電連接到所述第一重佈線結構的第一組穿孔、以及將所述第二組記憶體結構放置在所述第一重佈線結構上；以及將所述記憶體結構堆疊貼合到邏輯晶粒。在實施例中，將所述第一裝置接合到所述第二裝置包括混合接合製程。在實施例中，形成所述第一組記憶體結構及所述第二組記憶體結構中的每一記憶體結構更包括：在將所述第一裝置接合到所述第二裝置之後，在所述第一裝置上並環繞所述第二裝置形成介電材料；以及形成延伸穿過所述介電材料的至少一個介電穿孔，其中所述至少一個介電穿孔電連接到所述第一裝置。在實施例中，形成所述第一組記憶體結構及所述第二組記憶體結構中的每一記憶體結構更包括：在第三基底上形成第三裝置；以及將所述第三裝置接合到所述第一裝置，以將所述第三裝置電耦合到所述第一裝置。在實施例中，所述第三裝置包括積體被動裝置（IPD）。在實施例中，所述第一裝置具有與所述第二裝置相同的橫向尺寸。在實施例中，形成所述記憶體結構堆疊更包括：在所述第二組記憶體結構及所述第一組穿孔上形成電連接到所述第二組記憶體結構及所述第一組穿孔的第二重佈線結構；以及在所述第二重佈線結構上形成電連接到所述第二重佈線結構的第二組穿孔。在實施例中，所述第一裝置的所述記憶體元件包括DRAM元件。在實施例中，所述第一裝置是使用DRAM製程技術形成，且所述第二裝置是使用CMOS製程技術形成。
根據本發明的一些實施例，一種方法包括：形成堆疊式記憶體裝置，包括：將第一記憶體結構放置在載體基底上，所述第一記憶體結構包括接合到第一邏輯晶粒的第一記憶體晶粒，在所述第一記憶體結構上形成第一重佈線結構，其中所述第一重佈線結構電連接到所述第一記憶體結構，形成從所述第一重佈線結構延伸的第一金屬柱，其中所述第一金屬柱電連接到所述第一重佈線結構，將第二記憶體結構鄰近所述第一金屬柱放置在所述第一重佈線結構上，所述第二記憶體結構包括接合到第二邏輯晶粒的第二記憶體晶粒，在所述第二記憶體結構及所述第一金屬柱之上形成第二重佈線結構，其中所述第二重佈線結構電連接到所述第一金屬柱，以及在所述第二重佈線結構上形成外部連接件，其中所述外部連接件電連接到所述第二重佈線結構；以及將所述堆疊式記憶體裝置貼合到第三邏輯晶粒，其中所述堆疊式記憶體裝置的所述外部連接件電連接到所述第三邏輯晶粒。在實施例中，所述方法更包括形成所述第一記憶體結構，包括：將所述第一邏輯晶粒的前表面接合到所述第一記憶體晶粒的前表面；以及在所述第一記憶體晶粒的所述前表面上形成介電材料；形成延伸穿過所述介電材料的穿孔，其中所述穿孔電連接到所述第一記憶體晶粒。在實施例中，所述方法更包括形成所述第二記憶體結構，包括：將所述第二邏輯晶粒的前表面接合到所述第二記憶體晶粒的前表面；在所述第二邏輯晶粒的所述前表面上形成介電材料；以及形成延伸穿過所述介電材料的穿孔，其中所述穿孔電連接到所述第二邏輯晶粒。在實施例中，所述第三邏輯晶粒包括基底穿孔，且其中所述堆疊式記憶體裝置的所述外部連接件貼合到所述基底穿孔。在實施例中，形成堆疊式記憶體裝置更包括在所述第一金屬柱及所述第一記憶體結構之上並環繞所述第一金屬柱及所述第一記憶體結構形成包封體。在實施例中，所述方法更包括將第三記憶體結構放置在所述載體基底上。
根據本發明的一些實施例，一種封裝件包括貼合到邏輯裝置的記憶體堆疊，所述記憶體堆疊包括：多個第一記憶體結構；第一重佈線層，位於所述第一記憶體結構之上並電連接到所述多個第一記憶體結構；多個第二記憶體結構，位於所述第一重佈線層上；第二重佈線層，位於所述第二記憶體結構之上並電連接到所述第二記憶體結構；以及多個第一金屬柱，位於所述第一重佈線層上並鄰近所述多個第二記憶體結構，所述多個第一金屬柱電連接所述第一重佈線層與所述第二重佈線層；其中所述第一記憶體結構中的每一第一記憶體結構包括：記憶體晶粒，包括第一接觸墊；以及周邊電路系統晶粒，包括第二接觸墊，其中所述記憶體晶粒的所述第一接觸墊接合到所述周邊電路系統晶粒的所述第二接觸墊。在實施例中，所述記憶體晶粒是MRAM記憶體晶粒。在實施例中，所述周邊電路系統晶粒的橫向面積小於所述記憶體晶粒的橫向面積。在實施例中，所述第一記憶體結構中的每一第一記憶體結構更包括環繞所述周邊電路系統晶粒的介電材料及延伸穿過所述介電材料以與所述記憶體晶粒的第一接觸墊接觸的介電穿孔（TDV）。在實施例中，所述第一金屬柱及所述第二記憶體結構被模塑材料環繞並分隔開。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應瞭解，其可容易地使用本發明做為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不悖離本發明的精神及範圍，而可在不悖離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
100:周邊裝置/處理器裝置 102:半導體基底/基底 104、204、508、820、920、1112:裝置 106、206、316、426:金屬化圖案 108、208:接合墊 110、210、506、1006、1114:內連結構 112:穿孔/基底穿孔（TSV） 113:襯裡 200:記憶體裝置 202、510:基底 222:磁性隧道接面（MTJ） 250:底部接觸金屬/位元線 252:頂部金屬觸點 254:堆疊電容器 256:字元線 300、400、400’、610、710、810:記憶體結構 310:介電材料 312:介電穿孔（TDV） 313:隔離層 314:絕緣層 318:導電墊 320:鈍化層 402、502:載體基底 404、504:釋放層 408:介電層/電介質 418:黏合劑 422:重佈線結構 422’:重佈線結構/第二重佈線結構 424、428:介電層 438、1038:導電柱 442、1042、1104、1116:包封體 446、522、1022:凸塊下金屬（UBM） 448、1122:導電連接件 450、650、750、850、1050:記憶體堆疊 500、600、700、800、900、1000:記憶體封裝件 514:底部填充材料 516、912:模塑材料 520、1020、1030:邏輯裝置 524、1024:外部連接件 526、1118:穿孔 528:阻擋層 906:第二內連結構 1100、1200:封裝結構 1102:裝置晶粒 1106:散熱器 1110:中介層基底 1120:外部組件
接合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出根據一些實施例的記憶體結構的周邊裝置的剖視圖。 圖2A及圖2B示出根據一些實施例的記憶體結構的記憶體裝置的剖視圖。 圖3A至圖3F示出根據一些實施例在形成記憶體結構時的中間階段的剖視圖。 圖4A至圖4H是根據一些實施例在用於形成記憶體堆疊的製程期間的中間步驟的剖視圖。 圖5A至圖5E是根據一些實施例在用於形成記憶體封裝件的製程期間的中間步驟的剖視圖。 圖6至圖9示出根據一些實施例的記憶體封裝件的剖視圖。 圖10A至圖10D是根據一些實施例在用於形成記憶體封裝件的製程期間的中間步驟的剖視圖。 圖11A及圖11B示出根據一些實施例併入有記憶體封裝件的封裝結構。
100:周邊裝置/處理器裝置
200:記憶體裝置
318:導電墊
400:記憶體結構
408:介電層/電介質
418:黏合劑
422:重佈線結構
422’:重佈線結構/第二重佈線結構
424、428:介電層
426:金屬化圖案
438:導電柱
442:包封體
446:凸塊下金屬(UBM)
448:導電連接件
450:記憶體堆疊

Claims (1)

  1. 一種記憶體封裝件的形成方法，包括： 形成第一組記憶體結構及第二組記憶體結構，其中形成所述第一組記憶體結構及所述第二組記憶體結構中的每一記憶體結構包括： 在第一基底上形成包括記憶體元件的第一裝置； 在第二基底上形成第二裝置；以及 將所述第二裝置接合到所述第一裝置，以將所述第一裝置電耦合到所述第二裝置； 形成記憶體結構堆疊，包括： 將所述第一組記憶體結構放置在載體上； 在所述第一組記憶體結構上形成電連接到所述第一組記憶體結構的第一重佈線結構； 在所述第一重佈線結構上形成電連接到所述第一重佈線結構的第一組穿孔；以及 將所述第二組記憶體結構放置在所述第一重佈線結構上；以及 將所述記憶體結構堆疊貼合到邏輯晶粒。
TW109111681A 2020-01-17 2020-04-08 記憶體封裝件及其形成方法 TW202129913A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/745,718 2020-01-17
US16/745,718 US11282816B2 (en) 2020-01-17 2020-01-17 Memory packages and methods of forming same

Publications (1)

Publication Number Publication Date
TW202129913A true TW202129913A (zh) 2021-08-01

Family

ID=76809497

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109111681A TW202129913A (zh) 2020-01-17 2020-04-08 記憶體封裝件及其形成方法

Country Status (3)

Country Link
US (3) US11282816B2 (zh)
CN (1) CN113140475A (zh)
TW (1) TW202129913A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI833531B (zh) * 2022-03-02 2024-02-21 南亞科技股份有限公司 半導體記憶體

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
JP2020126921A (ja) * 2019-02-04 2020-08-20 株式会社村田製作所 高周波モジュールおよび通信装置
KR20220008093A (ko) * 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11444068B2 (en) * 2020-07-14 2022-09-13 Qualcomm Incorporated Three-dimensional (3D) integrated circuit device having a backside power delivery network
KR20220040537A (ko) * 2020-09-23 2022-03-31 삼성전자주식회사 반도체 패키지
KR20220058683A (ko) * 2020-10-29 2022-05-10 삼성전자주식회사 반도체 패키지
US11791326B2 (en) * 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip
US11721685B2 (en) * 2021-05-26 2023-08-08 Avago Technologies International Sales Pte. Limited Copper-bonded memory stacks with copper-bonded interconnection memory systems
US20230207525A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Ic die stacking with mixed hybrid and solder bonding

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685429B2 (en) * 2014-07-29 2017-06-20 Dyi-chung Hu Stacked package-on-package memory devices
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10522449B2 (en) * 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
KR102491103B1 (ko) * 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11387222B2 (en) * 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI833531B (zh) * 2022-03-02 2024-02-21 南亞科技股份有限公司 半導體記憶體

Also Published As

Publication number Publication date
US11855046B2 (en) 2023-12-26
US11282816B2 (en) 2022-03-22
US20240105682A1 (en) 2024-03-28
CN113140475A (zh) 2021-07-20
US20220208735A1 (en) 2022-06-30
US20210225809A1 (en) 2021-07-22

Similar Documents

Publication Publication Date Title
US11309223B2 (en) Method of forming semiconductor device package having dummy devices on a first die
TW202129913A (zh) 記憶體封裝件及其形成方法
TWI746306B (zh) 封裝結構及其形成方法
TWI741538B (zh) 半導體元件及其形成方法
CN112687670B (zh) 集成电路结构及其形成方法
TW202129849A (zh) 積體電路封裝及方法
TW202134713A (zh) 積體電路封裝及其形成方法
CN112687671A (zh) 集成电路结构及其形成方法
TW202117952A (zh) 半導體封裝件及製造方法
US20240021583A1 (en) Package and method of fabricating the same
CN113808959A (zh) 封装结构的制造方法
KR20220116096A (ko) 집적 회로 패키지 및 방법
US11810793B2 (en) Semiconductor packages and methods of forming same
TWI776646B (zh) 積體電路封裝體及其形成方法
TWI735353B (zh) 積體電路封裝及其製作方法
CN221041116U (zh) 集成电路封装
TWI838073B (zh) 積體電路封裝及其形成方法
TW202407951A (zh) 積體電路封裝及其製造方法
TW202339133A (zh) 封裝及其製造方法
CN117116873A (zh) 集成电路封装件及其形成方法