CN1658385A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1658385A
CN1658385A CN2005100093505A CN200510009350A CN1658385A CN 1658385 A CN1658385 A CN 1658385A CN 2005100093505 A CN2005100093505 A CN 2005100093505A CN 200510009350 A CN200510009350 A CN 200510009350A CN 1658385 A CN1658385 A CN 1658385A
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layer
semiconductor device
hole
barrier layer
wiring layer
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龟山工次郎
铃木彰
冈山芳央
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置及其制造方法，可在抑制蚀刻工序增加的同时，最大限度地抑制半导体装置的电气特性的劣化。本发明的半导体装置在半导体衬底(10)的表面形成层积第一阻挡层(12)和铝层而构成的焊盘电极层14。另外，在半导体衬底(10)的表面粘接支承衬底(16)。在半导体衬底(10)的背面、及从半导体衬底10的背面到第一阻挡层(12)的通孔(18)内形成第二阻挡层(19)。进而完全或不完全埋入通孔(18)内而形成再配线层(21)。在再配线层(21)上形成球状端子(22)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是涉及在半导体衬底上形成通孔而构成的半导体装置及其制造方法。
背景技术
目前，作为具有和半导体芯片的外形尺寸大致相同尺寸的芯片尺寸封装之一种，可知有BGA(Ball Grip Array)型半导体装置。该BGA型半导体装置中，在封装的一主面上格子状排列多个由焊锡等金属部件构成的球状端子，并将其与在封装的另一面上形成的半导体芯片电连接。
而且，在将该BGA型半导体装置装入电子设备时，通过将各球状端子压装在印刷线路板上的配线图案上，将半导体芯片和搭载在印刷线路板上的外部电路电连接。
这种BGA型半导体装置与具有向侧部突出的引脚的SOP(Small OutlinePackage)或QFP(Quad Flat Packagae)等其它类型的芯片尺寸封装相比，可设置多个球状端子，而且具有可小型化的优点。BGA型半导体装置具有作为例如搭载于手机上的数字相机的图像传感器芯片的用途。在该例中，在半导体芯片的一主面上或两主面上粘接例如由玻璃构成的支承衬底。另外，关联的技术文献可列举以下的专利文献1。
其次，参照附图说明在半导体芯片上粘接一张支承衬底而构成的现有例的GBA型半导体装置及其制造方法。
图5～图7是可应用于图像传感器芯片的现有例的BGA型半导体装置及其制造方法的剖面图。首先，如图5所示，在半导体衬底30上的表面上介由绝缘膜例如氧化膜31形成由铝层或铝合金层构成的焊盘电极层34。然后在含有焊盘电极层34的半导体衬底30的表面上介由树脂层35粘接由例如玻璃构成的支承衬底36。
其次，如图6所示，在与焊盘电极层34对应的半导体衬底30的背面形成具有开口部的抗蚀剂层37，以该抗蚀剂层为掩模对半导体衬底30进行干蚀刻，形成从半导体衬底30的背面到达焊盘电极层34的通孔38。在此，在利用所述蚀刻形成的通孔38底部的焊盘电极层34的一部分上形成在进行蚀刻时生成的铝氧化物50(例如Al2O3化合物)。
然后，如图7所示，在包括通孔30内的半导体衬底30的背面形成阻挡层39。进而在阻挡层39上形成镀敷用籽晶层40，并在该籽晶层40上进行镀敷处理，形成由例如铜(Cu)构成的再配线层41。进而在再配线层41上形成保护层(未图示)，并在保护层的规定位置设置开口，形成与再配线层41接触的球状端子42。
然后，图中未图示，切断半导体衬底及层积在半导体衬底上的所述各层，分离成各个半导体芯片。这样，形成焊盘电极层34和球状端子42电连接的BGA型半导体装置。
专利文献1：专利公表2002-512436号公报
但是，由于在通过所述蚀刻形成通孔38时，在其底部形成的铝氧化物50形成在焊盘电极层34的一部分上，故焊盘电极层34和再配线层41之间的电阻形成了高电阻。另外，由于铝氧化物50使焊盘电极层34相对于再配线层41的被覆性劣化，故容易使再配线层41产生断线等损害。因此，产生了半导体装置的特性劣化这样的问题。
对此，虽可考虑利用再次蚀刻等将该铝氧化物50除去，但这种情况下由于蚀刻工序增加，而产生了使制造工序烦杂化这样的问题。
因此，本发明提供一种半导体装置及其制造方法，其可不增加蚀刻工序，最大限度地抑制电气特性的劣化。
发明内容
本发明的半导体装置是鉴于所述问题而开发的，其特征在于，包括：焊盘电极层，其形成在半导体芯片表面，且层积第一阻挡层和铝层或铝合金层而形成；支承体，其粘接在半导体芯片的表面；通孔，其从半导体芯片的背面到达第一阻挡层；再配线层，其形成在包括通孔内的半导体芯片的背面，且与第一阻挡层连接。
本发明半导体装置的特征在于，在所述结构的基础上，再配线层完全或不完全埋入通孔内。
本发明半导体装置的特征在于，所述再配线层通过镀敷处理或喷溅处理形成。
本发明半导体装置的特征在于，在再配线层上形成有导电端子。
本发明半导体装置的特征在于，在包括通孔内的半导体芯片的背面和再配线层之间形成有第二阻挡层。
本发明半导体装置的制造方法的特征在于，其包括：准备具有层积第一阻挡层和铝层或铝合金层而构成的焊盘电极层的半导体衬底，并在半导体衬底的表面粘接支承体的工序；在半导体衬底上形成从半导体衬底的背面到第一阻挡层的通孔的工序；在包括通孔内的半导体衬底背面形成与第一阻挡层连接的再配线层的工序。
本发明半导体装置的制造方法的特征在于，在所述形成再配线层的工序中，再配线层完全或不完全埋入通孔内。
本发明半导体装置的制造方法的特征在于，在形成再配线层的工序中，所述再配线层通过镀敷处理或喷溅处理形成。
本发明半导体装置的制造方法的特征在于，在所述工序的基础上，具有在再配线层上形成导电端子的工序。
另外，本发明半导体装置的制造方法的特征在于，在所述工序的基础上，具有在包括通孔内的半导体衬底的背面和再配线层之间形成第二阻挡层的工序。
根据本发明的半导体装置及其制造方法，通过层积铝层或铝合金层和第一阻挡层，形成焊盘电极层。由此，可避免在通过蚀刻形成通孔时，如目前那样在位于通孔底部的焊盘电极层上形成铝氧化物的情况。因此，可焊盘电极层和再配线层之间不会形成高电阻，可最大限度地抑制再配线层上产生断线等损伤。其结果可最大限度地抑制由于所述通孔的形成而引起的半导体装置的电气特性劣化。另外，不需要用于除去铝氧化物的蚀刻工序。
附图说明
图1是说明本发明实施例的半导体装置制造方法的剖面图；
图2是说明本发明实施例的半导体装置制造方法的剖面图；
图3是说明本发明实施例的半导体装置制造方法的剖面图；
图4是说明本发明实施例的半导体装置及其制造方法的剖面图；
图5是说明现有的半导体装置及其制造方法的剖面图；
图6是说明现有的半导体装置及其制造方法的剖面图；
图7是说明现有的半导体装置及其制造方法的剖面图。
具体实施方式
其次，参照附图说明本实施例的半导体装置的结构。图4表示在本实施例的半导体装置中、存在后述的焊盘电极层的区域的剖面，表示分离成各个半导体芯片之前的状态。
如图4所示，在由Si构成的半导体衬底10(之后进行分离，分离成各半导体芯片)的表面上形成焊盘电极层14，该焊盘电极层14是介由绝缘膜例如氧化膜11在第一阻挡层12上层积铝层13(或铝合金层)而构成的。即，第一阻挡层12作为靠近半导体衬底10的层而形成。
另外，在半导体衬底10上形成有未图示的电路，焊盘电极层14与所述电路电连接。所述未图示的电路作为例如CCD(Charge Coupled Device)图像传感器而形成。此时，由于需要作为CCD图像(影像)基准点的光学暗区，故构成焊盘电极层14的铝层13优选使用由可遮蔽光(红外线)的纯铝构成，也可以是Al-Cu层。或优选使用除含有透过红外线的硅(Si)的合金(例如Al-Si，Al-Si-Cu等)之外的金属。
另外，第一阻挡层12优选例如氮化钛(TiN)层。或只要是高熔点金属层或其化合物层，则第一阻挡层12也可以由氮化钛层之外的金属构成，也可以采用钽(Ta)层、钛钨(TiW)层、氮化钽(TaN)层等。
然后，在半导体底10的表面上介由树脂层15(作为粘接剂起作用)粘接由可透过例如规定波长带的光的玻璃构成的支承衬底16。在半导体衬底10中、存在焊盘电极层14的区域，形成从半导体衬底10的背面到达焊盘电极层14的第一阻挡层12的通孔18。然后，在包括该通孔18内的半导体衬底10的背面上介由为绝缘从通孔18露出的半导体衬底10侧壁而形成的绝缘层形成第二阻挡层19将其覆盖。该第二阻挡层19优选使用例如氮化钛层。或第二阻挡层19也可以与第一阻挡层相同，由氮化钛层之外的金属构成。
然后，在第二阻挡层19上形成镀敷用籽晶层20和通过镀敷处理成膜的再配线层21。进而在再配线层21上形成保护层(未图示)，在保护层的规定位置设置开口，形成与再配线21接触的球状端子22。即，该球状端子22介由再配线层21、籽晶层22、第二阻挡层19与焊盘电极层14电连接。
其次，参照附图说明上述本实施例的半导体装置的制造方法。图1～图4是显示本实施例的半导体装置制造方法的剖面图。图1～图4表示焊盘电极层14存在的区域的剖面，表示分离成各个半导体芯片之前的状态。
首先，如图1所示，在形成未图示的电路的半导体衬底10(之后分离，形成各半导体芯片)的表面上介由绝缘层、例如氧化膜11形成在第一阻挡层12上层积铝层13或铝合金层而构成的焊盘电极层14。即，第一阻挡层12作为靠近半导体芯片10侧的层而形成。
在此，在所述未图示的电路为例如CCD图像传感器时，构成焊盘电极层14的铝层13最好由纯铝构成。而且，铝层13的厚度优选可遮蔽光(红外线)的厚度(例如2μm)。另外，第一阻挡层12优选例如氮化钛(TiN)层，在本实施例中使用250℃设定温度的喷溅装置喷溅形成氮化钛(TiN)层。或如前所述，第一阻挡层12如使用高熔点金属或其化合物，则也可以使用除氮化钛之外的金属构成。
然后，在半导体衬底10的表面上介由树脂层15(作为粘接剂起作用)粘接例如由玻璃构成的支承衬底16。
其次，如图2所示，在半导体衬底10的背面上形成在焊盘电极层14存在的位置的一部分上开口的抗蚀剂层17。然后，以抗蚀剂层17为掩模，对半导体衬底10进行蚀刻，形成从半导体衬底10的背面到达焊盘电极层14的第一阻挡层12的通孔18。此时的蚀刻在半导体衬底10由硅(Si)构成时，优选使用包括例如SF6、O2或C2F4、C4F8或CHF3等CF系气体的蚀刻气体通过干蚀刻进行。
在此，由于位于通孔18底部的焊盘电极层14的面构成第一阻挡层12，故所述蚀刻不波及到铝层13。因此，不会形成显示现有例的半导体装置的图6中可看到的铝氧化物50(例如Al2O3化合物)等氧化物。
其次，在除去抗蚀剂层17后，如图3所示，在包括通孔18内的半导体衬底10的背面上覆盖它们形成由氧化膜等构成的绝缘层，在除去第一阻挡层12上的绝缘层之后，在整个面上形成第二阻挡层19。该第二阻挡层19优选例如氮化钛层，在本实施例中，在200℃以下的CVD装置内利用CVD法形成氮化钛层。或如前所述，第二阻挡层19如使用高熔点金属或其化合物，则也可以使用氮化钛层之外的金属构成。另外，在第二阻挡层19形成前或形成后，也可以在半导体衬底10或第二阻挡层19上形成用于缓和向球状端子22施加的力的未图示的缓冲部件。在此，由于在蚀刻除去第一阻挡层12上的绝缘膜(例如氧化膜)时，铝层13不会从第一阻挡层12露出，故不形成铝氧化物。
其次，如图4所示，在第二阻挡层19上的整个面上形成再配线层21。此时，首先，在第二阻挡层19上的整个面上通过电镀形成例如由铜(Cu)构成的镀敷用籽晶层20，然后，通过对该籽晶层20进行无电解镀敷，形成例如由铜(Cu)构成的再配线层21。在此，再配线层21不完全埋入通孔18内。或再配线层21也可以完全埋入通孔18内而形成。
另外，在再配线层21上形成保护层(未图示)，通过在保护层的规定位置设置开口后采用网印法印刷焊锡并使其回流，在所述开口上形成球状端子22。然后，通过沿切割线路切断半导体衬底10及层积在其上的各层，完成各个半导体芯片，即本实施例的半导体装置，这一点未图示。
如上所述，根据本发明的半导体装置及其制造方法，在半导体衬底10的表面形成焊盘电极层14，焊盘电极层14是在第一阻挡层12(例如由氮化钛层构成)上层积铝层13或铝合金层而构成的。
由此，在通过蚀刻形成通孔18时，由于第一阻挡层12的存在可避免在位于通孔18底部的焊盘电极层14上形成铝氧化物。因此，可最大限度地避免在焊盘电极层14和再配线层21之间形成高电阻。另外，可最大限度地抑制再配线层21上产生断线等损伤。其结果可最大限度地抑制所述通孔18的形成而引起的半导体装置特性的劣化。另外，由于不必除去铝氧化物50，故不必增加蚀刻工序。
另外，在本实施例中，在包括通孔18的半导体衬底10的背面形成第二阻挡层19，但本发明不限于此。即，在本发明中，也可以在包括通孔18的半导体衬底10的背面不形成第二阻挡层19，而介由所述绝缘层形成再配线层21。
在本实施例中，通过镀敷处理形成再配线层21，但本发明不限于此。即，在本发明中，也可以不形成镀敷用籽晶层20，而通过镀敷处理之外的方法形成再配线层21，例如也可以喷溅例如铝(Al)等金属而形成。
本发明适用于形成有球状端子22的半导体装置中，但本发明不限于此，即，只要是形成有贯通半导体衬底的通孔，则本发明也适用于未形成球状端子的半导体装置。例如也适用于LGA(Land Grid Array)型半导体装置。
换句话说，在本发明中，由于在形成通孔18侧的铝层13上形成第一阻挡层12，故可抑制进行通孔开口时的蚀刻处理时因超量蚀刻而蚀刻铝层13的表面的现象。因此，可不必考虑超量蚀刻消除的量而增加铝层13的膜厚。

Claims (16)

1、一种半导体装置，其特征在于，包括：焊盘电极层，其在半导体芯片表面形成，且层积第一阻挡层和铝层或铝合金层而形成；支承体，其粘接在所述半导体芯片的表面；通孔，其从所述半导体芯片的背面到达所述第一阻挡层；再配线层，其形成在包括所述通孔内的所述半导体芯片的背面，且与所述第一阻挡层连接。
2、如权利要求1所述的半导体装置，其特征在于，所述再配线层完全埋入所述通孔内而形成。
3、如权利要求1所述的半导体装置，其特征在于，所述再配线层形成为不完全埋入所述通孔内。
4、如权利要求1、2、3中任意一项所述的半导体装置，其特征在于，所述再配线层利用镀敷处理或喷溅处理形成。
5、如权利要求1、2、3、4中任意一项所述的半导体装置，其特征在于，在所述再配线层上形成有导电端子。
6、如权利要求1、2、3、4、5中任意一项所述的半导体装置，其特征在于，所述第一阻挡层包括氮化钛层、钛钨层、氮化钽层、高熔点金属层及其化合物层中的任意一种。
7、如权利要求1、2、3、4、5、6中任意一项所述的半导体装置，其特征在于，在包括所述通孔内的所述半导体芯片的背面和所述再配线层之间形成有第二阻挡层。
8、如权利要求7所述的半导体装置，其特征在于，所述第二阻挡层包括氮化钛层、钛钨层、氮化钽层、高熔点金属层及其化合物层中的任意一种。
9、一种半导体装置的制造方法，其特征在于，包括：准备具有层积第一阻挡层和铝层或铝合金层而构成的焊盘电极层的半导体衬底，并在所述半导体衬底的表面粘接支承体的工序；在所述半导体衬底上形成从该半导体衬底的背面到所述第一阻挡层的通孔的工序；在包括所述通孔内的所述半导体衬底背面形成与所述第一阻挡层连接的再配线层的工序。
10、如权利要求9所述的半导体装置的制造方法，其特征在于，在形成所述再配线层的工序中，所述再配线层完全埋入所述通孔内而形成。
11、如权利要求9所述的半导体装置的制造方法，其特征在于，在形成所述再配线层的工序中，所述再配线层不完全埋入所述通孔内。
12、如权利要求9、10、11中任意一项所述的半导体装置的制造方法，其特征在于，在形成所述再配线层的工序中，所述再配线层利用镀敷处理或喷溅处理形成。
13、如权利要求9、10、11、12中任意一项所述的半导体装置的制造方法，其特征在于，包括在所述再配线层上形成导电端子的工序。
14、如权利要求9、10、11、12、13中任意一项所述的半导体装置的制造方法，其特征在于，所述第一阻挡层包括氮化钛层、钛钨层、氮化钽层、高熔点金属层及其化合物层中的任意一种。
15、如权利要求9、10、11、12、13、14中任意一项所述的半导体装置的制造方法，其特征在于，还具有在包括所述通孔内的所述半导体的背面和所述再配线层之间形成第二阻挡层的工序。
16、如权利要求15所述的半导体装置的制造方法，其特征在于，第二阻挡层包括氮化钛层、钛钨层、氮化钽层、高熔点金属层及其化合物层中的任意一种。
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