CN1779960A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
一种具有贯通电极的半导体装置及其制造方法,谋求半导体装置的可靠性及成品率的提高。在半导体衬底(10)的表面上介由第一绝缘膜(11)形成第一焊盘电极层(12)。然后,在它们的上层形成具有将第一焊盘电极层(12)局部露出的第一通孔(101)的第二绝缘膜(13)。然后,在第一通孔(101)内形成塞(14),在第二绝缘膜(13)上形成与该塞(14)连接的第二焊盘电极层(15)。然后,形成与第二通孔(102)底部的焊盘电极(12)连接的贯通电极(20)及第二配线层(21)。再形成保护层(22)、导电端子(23)。最后,通过进行切割,将半导体衬底(10)切断分离成半导体芯片(10)。
Description
技术领域
本发明涉及半导体装置及其制造方法,特别是涉及具有贯通电极的半导体装置及其制造方法。
背景技术
近年来,作为三维安装技术,或作为新的封装技术,CSP(芯片尺寸封装Chip Size Package)正在受到人们的关注。CSP是指,具有与半导体芯片的外形尺寸大致相同尺寸的外形尺寸的小型封装。
目前,作为CSP之一种,已知有具有贯通电极的BGA型半导体装置。该BGA型半导体装置具有贯通半导体衬底而与焊盘电极连接的贯通电极。另外,该半导体装置在其背面上格子状配置有多个由焊锡等金属部件构成的球状导电端子。
而且,在将该半导体装置组装到电子设备时,将各导电端子与电路衬底(例如印刷线路板)上的配线图案连接。这种BGA型半导体装置与具有向侧部突出的引脚的SOP(Small Outline Package)或QFP(Quad Flat Package)等其它CSP型半导体装置相比,具有可设置多个导电端子,而且,可将其小型化这样的优点。
下面概略说明现有例的具有贯通电极的BGA型半导体装置的制造方法。首先,在半导体衬底表面介由第一绝缘膜形成焊盘电极。然后,通过蚀刻该半导体衬底,形成从半导体衬底背面到达焊盘电极的通孔。然后,在包括通孔内的半导体衬底的背面上形成在该通孔底部露出焊盘电极的第二绝缘膜。
另外,在通孔内的第二绝缘膜上形成与在该底部露出的焊盘电极电连接的贯通电极。同时,在半导体衬底背面的第二绝缘膜上形成与上述贯通电极连接的配线层。然后,在包括上述配线层上的半导体衬底的背面上形成保护层,将上述保护层的一部分开口,露出上述配线层的一部分。另外,也可以在该配线层上形成导电端子。然后,通过切割将半导体衬底切断分离成多个半导体芯片。
另外,关联技术文献可列举以下专利文献。
专利文献1:特开2003-309221号公报
下面,参照附图说明上述现有例的半导体装置制造方法的一部分工序。图19是表示现有例的半导体装置的制造方法的剖面图。
如图19所示,在所谓的前工序中,在形成有未图示的电子器件的半导体衬底50的表面介由第一绝缘膜51形成有第一焊盘电极层52。另外,在第一焊盘电极层52上形成有第二焊盘电极层55。在第二焊盘电极层55的一部分上、及第一绝缘膜51上形成有具有露出第二焊盘电极层55的开口部53W的第二绝缘膜53。
在此,在未图示的电子器件等的电路测试中,通过半导体装置表面的开口部53W,使探针70接触在上述的第二焊盘电极层55上。但是,在将探针70与第二焊盘电极层55接触时,在探针70与第二焊盘电极层55接触时,在第二焊盘电极层55上会产生划伤等损伤,该损伤甚至会影响到第一焊盘电极层。例如,产生了从第二焊盘电极层55到达第一焊盘电极层52这样的划伤等损伤。
因此,在之后的工序中,在通过例如干式蚀刻、湿式蚀刻或等离子蚀刻等形成从半导体衬底50的背面到达第一焊盘电极层52上的第一绝缘膜51的通孔时,该蚀刻会集中在第一焊盘电极层52上产生的上述损伤,导致第一焊盘电极52或第二焊盘电极55的破损。
另外,在含有由于上述损伤产生了破损的第一焊盘电极层52上的通孔内形成了由例如铜(Cu)构成的未图示的贯通电极后,存在在该贯通电极和第一焊盘电极层52之间产生连接不良的情况。即,产生了具有贯通电极的半导体装置的可靠性降低的问题。结果使具有贯通电极的半导体装置的可靠性及成品率降低。
发明内容
因此,本发明提供一种具有贯通电极的半导体装置及其制造方法,谋求该半导体装置的可靠性及成品率的提高。
本发明的半导体装置及其制造方法是鉴于上述课题而构成的,其具有以下特征。即,本发明的半导体装置具有:半导体芯片;在半导体芯片的表面上介由第一绝缘膜形成的第一焊盘电极层;形成于第一焊盘电极层上的第二绝缘膜;形成于在第二绝缘膜上开口的第一通孔内的金属塞;形成于第二绝缘膜上,介由金属塞与第一焊盘电极层电连接的第二焊盘电极层;从半导体芯片的背面到达第一焊盘电极层的第二通孔;形成于第二通孔内,且通过该第二通孔与第一焊盘电极层电连接的贯通电极。
另外,本发明的半导体装置在上述结构的基础上,具有:第一保护层,其形成于第二焊盘电极层的一部分上及第二绝缘膜上,且具有使该第二焊盘电极层露出的开口部;配线层,其与贯通电极电连接,延伸到半导体芯片的背面上;第二保护层,其形成于含有配线层的半导体芯片上,使该配线层的一部分上露出。另外,本发明的半导体装置在上述结构的基础上,还可以在配线层的一部分上具有导电端子。
本发明提供一种半导体装置的制造方法,其特征在于,具有:在半导体衬底的表面上介由第一绝缘膜形成第一焊盘电极层的工序;在第一焊盘电极层上形成第二绝缘膜的工序;在第二绝缘膜上形成将第一焊盘电极层露出的第一通孔的工序;在第一通孔内形成金属塞的工序;在第二绝缘膜上形成介由金属塞与第一焊盘电极层电连接的第二焊盘电极层的工序;形成从半导体衬底背面到达第一焊盘电极层的第二通孔的工序;形成通过第二通孔与第一焊盘电极层电连接的贯通电极的工序;将半导体衬底切断分离成多个半导体芯片的工序。
本发明半导体装置的制造方法在上述工序的基础上,具有:在包含第二焊盘电极层上的第二绝缘膜上形成具有将第二焊盘电极层露出的开口部的第一保护层的工序;形成与贯通电极电连接并延伸到半导体衬底的背面上的配线层的工序;在包含配线层的半导体衬底上将该配线层的一部分上露出而形成第二保护膜的工序。另外,本发明的制造方法在上述工序的基础上,还可具有在配线层的一部分上形成导电端子的工序。
本发明提供一种半导体装置的制造方法,其特征在于,具有:在电连接多个焊盘电极层的半导体衬底上,形成从其背面到达多个焊盘电极层中靠近该半导体衬底表面的焊盘电极层的通孔的工序;形成通过通孔与靠近半导体衬底表面的焊盘电极层电连接的贯通电极的工序;将半导体衬底切断分离成多个半导体芯片的工序。
另外,本发明的半导体装置的制造方法在上述工序的基础上,具有在半导体衬底的表面侧形成使多个焊盘电极层中远离该半导体衬底表面的焊盘电极层露出的开口部的工序。
根据本发明,通过利用形成于第二绝缘膜上的第一通孔内的金属塞将第一焊盘电极层和第二焊盘电极层连接,其中,第二绝缘膜是被第一焊盘电极层和第二焊盘电极层夹着的绝缘膜。因此,即使在测试电路时等的探针接触第二焊盘电极层时,在该第二焊盘电极层上产生了划伤等损伤的情况下,第二绝缘膜或金属塞也可以起到保护层或缓冲层的功能,使该损伤难于影响第一焊盘电极层。即,可最大限度地抑止在第一焊盘电极层上产生上述损伤,使该第一焊盘电极层破损的情况。
另外,由于第二绝缘膜的存在,从而可对第一及第二焊盘电极层的残留应力进行所谓的应力控制。即,在半导体衬底上形成通孔时,在之前已蓄积于第一及第二焊盘电极层上的残留应力要朝向通孔的空间方向释放时,由于第二绝缘膜的存在而提高了第一及第二焊盘电极层的粘接性,由此,可最大限度地抑止第一及第二焊盘电极层被压向通孔的空间而弯曲变形的动向。
由于可最大限度地抑止第一焊盘电极层的破损或变形,故与在通孔底部与该第一焊盘电极层连接的贯通电极的连接不良被抑止,贯通电极和第一焊盘电极层的连接的可靠性提高。
这样,可分用为将第一焊盘电极层与贯通电极连接之用,及第二焊盘电极层与探针连接之用,而不使这些焊盘电极层的功能降低。结果可提高具有贯通电极的半导体装置的可靠性及成品率。
附图说明
图1是说明本发明实施例的半导体装置的制造方法的剖面图;
图2是说明本发明实施例的半导体装置的制造方法的剖面图;
图3是说明本发明实施例的半导体装置的制造方法的剖面图;
图4是说明本发明实施例的半导体装置的制造方法的剖面图;
图5是说明本发明实施例的半导体装置的制造方法的剖面图;
图6是说明本发明实施例的半导体装置的制造方法的剖面图;
图7是说明本发明实施例的半导体装置的制造方法的剖面图;
图8是说明本发明实施例的半导体装置的制造方法的剖面图;
图9是说明本发明实施例的半导体装置的制造方法的剖面图;
图10是说明本发明实施例的半导体装置的制造方法的剖面图;
图11是说明本发明实施例的半导体装置的制造方法的剖面图;
图12是说明本发明实施例的半导体装置的制造方法的剖面图;
图13是说明本发明实施例的半导体装置的制造方法的剖面图;
图14是说明本发明实施例的半导体装置的制造方法的剖面图;
图15是说明本发明实施例的半导体装置的制造方法的剖面图;
图16是说明本发明实施例的半导体装置的制造方法的剖面图;
图17是说明本发明实施例的半导体装置的剖面图;
图18是说明本发明实施例的半导体装置的剖面图;
图19是表示现有例的半导体装置的制造方法的剖面图。
具体实施方式
下面,参照附图说明本发明实施例的半导体装置的制造方法。图1~图16是表示本实施例的半导体装置的制造方法的剖面图。另外,图1~图16表示在半导体衬底中未图示的切割线的附近。
首先,如图1所示,准备在表面形成有电子器件的半导体衬底10。在此,未图示的电子器件是例如CCD(Charge Coupled Device)或红外线传感器等光接受元件、或发光元件。或,未图示的电子器件也可以为上述光接收元件或发光元件以外的电子器件。另外,半导体衬底10由例如硅衬底构成,但也可以为其它材质的衬底。另外,半导体衬底10优选具有约130μm的膜厚。
其次,在含有未图示的电子器件的半导体衬底10的表面上形成第一绝缘膜11作为层间绝缘膜。第一绝缘膜11例如由P-TEOS膜或BPSG膜等构成。另外,第一绝缘膜11优选利用CVD法形成,具有约0.8μm的膜厚。
其次,在半导体衬底10表面的第一绝缘膜11上形成与未图示的电子器件连接的作为外部连接用电极的第一焊盘电极层12。第一绝缘膜12例如由铝(Al)构成。优选形成有约1μm~2μm的膜厚。
其次,如图2所示,在半导体衬底10的表面上,即,第一焊盘电极层12上及第一绝缘膜11上形成第二绝缘膜13,使其覆盖该第一焊盘电极层12。第二绝缘膜13例如由氧化硅膜(SiO2膜)或氮化硅膜(SiN)构成,通过例如CVD法形成。另外,第二绝缘膜13优选形成约0.2μm~1μm的膜厚。
其次,如图3所示,在第二绝缘膜13上的规定区域选择性地形成第一抗蚀层41。形成第一抗蚀层41的上述第二绝缘膜13上的规定区域是指,除在后述的第一焊盘电极层12的一部分上局部形成的第一通孔的形成区域以外的区域。
其次,以第一抗蚀层41为掩模,优选通过干式蚀刻选择性地蚀刻第二绝缘膜13,形成将第二绝缘膜13局部开口,使第一焊盘电极层12露出的第一通孔101。在第一通孔101的底部露出第一焊盘电极层12。
在此,第一通孔101优选以规定的间隔形成于第一焊盘电极层52的两端部或其附近上。或,第一通孔101只要是在第一焊盘电极层12的一部分上,则也可以形成在上述以外的位置。另外,第一通孔101优选形成具有约0.5μm的直径。在完成上述蚀刻后,除去第一抗蚀层41。
其次,如图4所示,在上述第一通孔101内形成由金属构成的塞14。在此,塞14到达与第二绝缘膜13的表面为相同面的面上,埋入第一通孔内而形成。塞14优选是由钨(W)或钨合金构成的金属塞。或,塞14也可以由上述以外的金属构成。例如,塞14也可以为高温铝(Al)。
另外,塞14的形成方法没有特别限制,也可以为例如如下所示的镶嵌(ダマシン)法。即,虽然图中未图示,但在包含第一通孔101内的第二绝缘膜13的整个面上形成例如由钨(W)构成的金属层后,通过所谓的CMP(Chemical Mechanical Polishing)将该金属层研磨至使第二绝缘膜13的表面露出。由此,形成具有上述结构的塞14。或,塞14也可以利用除上述以外的方法形成。
其次,如图5所示,在包含塞14上的第二绝缘膜13的整个面上形成第二焊盘电极层15。在此,第二焊盘电极层15介由第一通孔101的塞14与第一焊盘电极层12电及机械地连接。另外,第二焊盘电极层15例如由铝(Al)构成,优选形成具有约0.3μm~2μm的膜厚。
其次,如图6所示,在第二焊盘电极层15上的规定区域选择性地形成第二抗蚀层42。形成第二抗蚀层42的第二焊盘电极15上的规定区域是包含全部第一通孔101的开口部的区域。在本实施例中,作为其一例,在与第一焊盘电极层12的形成区域重叠的区域形成有第二抗蚀层42。
其次,以第二抗蚀层42为掩模,优选通过干式蚀刻选择性地蚀刻第二焊盘电极层15。通过进行该蚀刻,对第二焊盘电极层15进行构图,除去不需要的部分。在完成上述蚀刻后,除去第二抗蚀层42。
其次,如图7所示,覆盖第二焊盘电极层15,而在第二焊盘电极层15及第二绝缘膜13上形成第一保护层16。第一保护层16作为所谓的钝化膜起作用,优选由例如氧化硅膜(SiO2膜)或氮化硅膜(SiN)构成。
其次,如图8所示,在第一保护膜16上的规定区域选择性地形成第三抗蚀层43。形成第三抗蚀层43的第一保护层16上的规定区域是未形成后述的开口部16W的区域,即,第二焊盘电极15的一部分上及第二焊盘电极15的形成区域以外的区域。
其次,以第三抗蚀层43为掩模,优选通过干式蚀刻蚀刻第一保护层,形成露出第二焊盘电极层15的开口部16W。在完成上述蚀刻后,除去第三抗蚀层43。通过该开口部16W,第二焊盘电极层15也作为进行半导体装置的电路测试等时用于接触未图示的探针的电极使用。
如上所述,第一焊盘电极层12和第二焊盘电极层15通过形成于被它们夹着的第二绝缘膜13上的第一通孔101内的塞14连接。这样,由于将第一焊盘电极层12和第二焊盘电极层15分开,故在电路测试时等的探针接触第二焊盘电极层15时,即使在该第二焊盘电极层15上产生了划伤等损伤的情况下,第二绝缘膜13或塞14也可以起到保护层或缓冲层的功能,该损伤难于影响到第一焊盘电极层12。即,可最大限度地抑止在第一焊盘电极层12上产生上述损伤。
另外,在本实施例的说明中,对现有结构层积有两个焊盘电极层的结构,以介由绝缘膜将各焊盘电极层分开的结构进行了说明,但将现有结构中焊盘电极层为一个的结构分开成两个焊盘电极层,将它们同样分开配置的技术也包含于本发明中。
其次,如图9所示,在半导体衬底10的背面上选择性地形成第四抗蚀层44。即,第四抗蚀层44如下形成,即形成在半导体衬底10的背面上,在对应第一焊盘电极层12的位置具有开口部。
其次,以该第四抗蚀层44为掩模,优选通过干式蚀刻法蚀刻半导体衬底10。此时,例如蚀刻气体使用含有SF6、O2、或C4F8等的气体。而且,在使用SF6、O2作为蚀刻气体时,其蚀刻条件例如优选,其功率约为1.5KW,气体流量为300/30sccm,压力为25Pa。
这样,通过进行上述蚀刻,形成在第一焊盘电极层12上从半导体衬底10的背面贯通到其表面的第二通孔102。在第二通孔102的底部,第一绝缘膜11露出。
在此,在进行上述蚀刻时,没有在第一焊盘电极层12上产生电路测试时等探针接触而造成的损伤。因此,如现有例那样,因使用于干式蚀刻或湿式蚀刻的蚀刻气体或蚀刻溶液侵入第一焊盘电极层12的损伤部位而使第一焊盘电极层12破损的情况,可最大限度地被抑止。
另外,在形成第二通孔102前的上述电路测试时等,在未图示的探针接触时,即使第二焊盘电极层15变形,该变形也会由第二绝缘膜13或塞14缓和,而难于对第一焊盘电极层12造成影响。即,可最大限度地抑止第一焊盘电极层12被压向通孔的空间而弯曲变形。
其次,如图10所示,以第四抗蚀层44为掩模,优选利用干式蚀刻选择性地除去在第二通孔102底部露出的第一绝缘膜11的一部分。由此,第一焊盘电极层12的一部分在第二通孔102的底部露出。在完成上述蚀刻后,除去第四抗蚀层44。
其次,如图11所示,在包括第二通孔102内的半导体衬底10的背面上形成第三绝缘膜18。第三绝缘膜18例如由氧化硅膜(SiO2膜)或氮化硅膜(SiN)构成,通过例如CVD法形成。另外,第三绝缘膜18优选形成具有约1μm~2μm的膜厚。
其次,如图12所示,优选通过各向异性干式蚀刻从半导体衬底10的背面侧进行第三绝缘膜18的蚀刻。在此,第二通孔102底部的第三绝缘膜18对应该第二通孔102的深度,比半导体衬底10背面上的第三绝缘膜18薄地形成。因此,通过进行上述蚀刻,在第二通孔102的底部,除去第三绝缘膜18,将第一焊盘电极层12的一部分露出,但在半导体衬底10背面上及第二通孔102的侧壁留存第三绝缘膜18。
其次,如图13所示,在第二通孔102内及半导体衬底10背面的第三绝缘膜18上形成势垒金属层19。势垒金属层19例如由钨化钛(TiW)层、氮化钛(TiN)层、或氮化钽(TaN)层等金属层构成。
势垒金属层19例如通过喷溅法、CVD法、无电解镀敷法、或其它成膜方法形成。在该势垒金属层19上形成未图示的籽晶层。该籽晶层构成用于镀敷形成后述的配线形成层20A的电极,例如由铜(Cu)等金属构成。
另外,在利用氮化硅膜(SiN膜)形成第二通孔102侧壁的第三绝缘膜18时,由于该氮化硅膜(SiN膜)相对于铜扩散构成势垒,故也可以省略势垒金属层19。
其次,形成配线形成层20A,使其覆盖形成于半导体衬底10背面上的势垒金属层19及籽晶层。在此,上述配线形成层20A是例如通过电解镀敷法由例如铜(Cu)构成的金属层。
然后,如图14所示,在上述配线形成层20A的规定区域形成第五抗蚀层45。然后,以上述第五抗蚀层45为掩模,对上述配线形成层20A进行构图,形成贯通电极20、及与该贯通电极20连续并电连接的配线层21。将镀膜的厚度调整为将贯通电极20不完全埋入第二通孔102内这样的厚度。或,贯通电极20也可以完全埋入第二通孔102内而形成。另外,形成上述第五抗蚀层45的上述规定的区域是除第二通孔102的形成区域以外的区域,而且,是不形成具有后述的规定图案的配线层21的半导体衬底10背面上的区域。
在此,贯通电极20介由籽晶层及势垒金属层19与在第二通孔102底部露出的焊盘电极12电连接。另外,与贯通电极20连续的配线层21介由籽晶层及势垒金属层19在半导体衬底10的背面上以规定的图案形成。然后,在除去上述第五抗蚀层45后,以上述配线层21及籽晶层为掩模,构图除去上述势垒金属层19。
另外,上述的贯通电极20和配线层21也可以分别通过不同的工序形成。另外,贯通电极20及配线层21的形成也可以不通过使用上述那样的铜(Cu)的电解镀敷法,而由其它金属及成膜方法形成。例如,贯通电极20及配线层21也可以由铝(Al)或铝合金等构成,通过例如喷溅法形成。此时,在包括第二通孔102的半导体衬底10的背面上形成未图示的势垒金属层后,利用喷溅法在该势垒金属层上形成由上述金属构成的贯通电极及配线层。而且,只要在除第二通孔102的形成区域外的该配线层上的规定区域形成未图示的抗蚀层,以该抗蚀层为掩模,构图配线层即可。或,也可以通过CVD法形成贯通电极20及配线层21。
其次,如图15所示,在包括第二通孔102内的半导体衬底10的背面上,即势垒籽晶层19上、贯通电极20上及配线层21上形成将它们覆盖的保护层22。保护层22例如由抗蚀材料等构成。在第二保护层22中对应配线层21的位置设置开口部。而且,在该开口部露出的配线层21上形成例如由焊锡等金属构成的球状导电端子23。
其次,如图16所示,沿未图示的切割线切割该半导体衬底10。由此,完成由具有贯通电极20的半导体芯片10A构成的多个半导体装置。
如上所述,根据本实施例的半导体装置及其制造方法,即使在电路测试时等探针接触第二焊盘电极层15时,在该第二焊盘电极层15上产生划伤等损伤的情况下,第二绝缘膜13或塞14也可以起到保护层或缓冲层的功能,该损伤难于对第一焊盘电极层12造成影响。即,可最大限度地抑止在第一焊盘电极层12上产生由上述损伤而造成的破损。
另外,即使在上述探针接触时,第二焊盘电极层15朝向半导体芯片10A(半导体衬底10)的背面方向弯曲而变形的情况下,上述变形也会由第二绝缘膜13或塞14缓和,难于对第一焊盘电极层12构成影响。即,可最大限度地抑止第一焊盘电极层12被压向通孔的空间而弯曲变形。
另外,由于第一焊盘电极层12和第二焊盘电极层15分别与第二绝缘膜13连接,故第二焊盘电极层15的变形被最大限度地抑止。因此,与在第二通孔102的底部和该第一焊盘电极层12连接的贯通电极20的连接不良被抑止,贯通电极20和第一焊盘电极层12的连接可靠性提高。
这样,可分别用作将第一焊盘电极层12与贯通电极20连接的连接用,及将第二焊盘电极层15与探针连接的连接用,而不使这些焊盘电极层的功能降低。其结果可提高具有贯通电极的半导体装置的可靠性及成品率。
另外,在上述的实施例中,在开口部16W露出的第二焊盘电极层15构成进行半导体装置的电路测试等时用于连接未图示的探针的电极,但本发明不限于此。例如,本发明也可以在在开口部16W露出的第二焊盘电极层15上形成未图示的导电端子。在该情况下,也可以在形成有该导电端子的半导体装置的表面上进一步层积其它半导体装置,确立两者的电连接。
另外,上述的实施例不受导电端子23的形成限制。即,只要可将贯通电极20及配线层21、和未图示的电路衬底电连接,则未必需要形成导电端子23。例如,在半导体装置是LGA(Land Grip Array)型半导体装置的情况下,就不必在从保护层局部露出的配线层21的一部分上形成导电端子23。
上述的实施例不受配线层21的形成限制。即,在将贯通电极20完全埋入第二通孔102内的情况下,未必需要形成配线层21。例如,该贯通电极20也可以与未图示的电路衬底直接连接,而不介由配线层21及导电端子23。或,贯通电极20也可以在在第二通孔102的开口部露出的该贯通电极20上具有导电端子23,介由该导电端子23而不介由配线层21,与未图示的电路衬底连接。
另外,在上述的实施例中,在形成于第一焊盘电极层12和第二焊盘电极层15之间的第二绝缘膜13上以规定的间隔形成有三个以上的塞14,但本发明不限于此,也可以如以下所示的图17或图18那样形成。图17及图18是表示本实施例的半导体装置的剖面图。
即,如图17所示,本发明的半导体装置也可以在第二绝缘膜13上形成使第一焊盘电极层12和第二焊盘电极层15的一侧端部接触的一个塞14A。或,如图18所示,本发明的半导体装置也可以在第二绝缘膜13上形成使第一焊盘电极层12和第二焊盘电极层15的两端部接触的两个塞14B。在此,上述塞14A、14B都形成为不与探针的接触频率高的第一及第二焊盘电极层12、15的中央或中央附近的区域重叠。
因此,在探针的接触频率高的上述区域,与第二绝缘膜13相接的第一焊盘电极层12及第二焊盘电极层15的面积大,可更可靠地抑止第二焊盘电极层12的损伤或变形影响第一焊盘电极层12的情况。另外,由于两焊盘电极层间的粘接性增大,故焊盘电极层的变形被抑止。
Claims (8)
1、一种半导体装置,其特征在于,具有:半导体芯片;在所述半导体芯片的表面上介由第一绝缘膜形成的第一焊盘电极层;形成于所述第一焊盘电极层上的第二绝缘膜;形成于在所述第二绝缘膜上开口的第一通孔内的金属塞;形成于所述第二绝缘膜上,介由所述金属塞与所述第一焊盘电极层电连接的第二焊盘电极层;从所述半导体芯片的背面到达所述第一焊盘电极层的第二通孔;形成于所述第二通孔内,且通过该第二通孔与所述第一焊盘电极层电连接的贯通电极。
2、如权利要求1所述的半导体装置,其特征在于,具有:第一保护层,其形成于所述第二焊盘电极层的一部分上及所述第二绝缘膜上,且具有将该第二焊盘电极层露出的开口部;配线层,其与所述贯通电极电连接,在所述半导体芯片的背面上延伸;第二保护层,其形成于含有所述配线层的所述半导体芯片上,使该配线层的一部分上露出。
3、如权利要求2所述的半导体装置,其特征在于,在所述配线层的一部分上具有导电端子。
4、一种半导体装置的制造方法,其特征在于,具有:在半导体衬底的表面上介由第一绝缘膜形成第一焊盘电极层的工序;在所述第一焊盘电极层上形成第二绝缘膜的工序;在所述第二绝缘膜上形成使第一焊盘电极层露出的第一通孔的工序;在所述第一通孔内形成金属塞的工序;在所述第二绝缘膜上形成介由所述金属塞与所述第一焊盘电极层电连接的第二焊盘电极层的工序;形成从所述半导体衬底背面到达所述第一焊盘电极层的第二通孔的工序;形成通过所述第二通孔与所述第一焊盘电极层电连接的贯通电极的工序;将所述半导体衬底切断分离成多个半导体芯片的工序。
5、如权利要求4所述的半导体装置的制造方法,其特征在于,具有:在包含所述第二焊盘电极层上的所述第二绝缘膜上形成具有将所述第二焊盘电极层露出的开口部的第一保护层的工序;形成与所述贯通电极电连接,延伸到所述半导体衬底的背面上的配线层的工序;在包含所述配线层的所述半导体衬底上,使该配线层的一部分上露出而形成第二保护层的工序。
6、如权利要求5所述的半导体装置的制造方法,其特征在于,具有在所述配线层的一部分上形成导电端子的工序。
7、一种半导体装置的制造方法,其特征在于,具有:在电连接了多个焊盘电极层的半导体衬底上,形成从所述半导体衬底的背面到达所述多个焊盘电极层中靠近该半导体衬底表面的焊盘电极层的通孔的工序;形成通过所述通孔与靠近所述半导体衬底表面的焊盘电极层电连接的贯通电极的工序;将所述半导体衬底切断分离成多个半导体芯片的工序。
8、如权利要求7所述的半导体装置的制造方法,其特征在于,具有在半导体衬底的表面侧形成使在所述多个焊盘电极层中远离该半导体衬底表面的焊盘电极层露出的开口部的工序。
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- 2005-10-27 KR KR1020050101623A patent/KR100682434B1/ko not_active IP Right Cessation
- 2005-10-28 EP EP05023591A patent/EP1653510A3/en not_active Withdrawn
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Cited By (2)
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CN101562162B (zh) * | 2009-05-12 | 2013-01-09 | 南通华科知识产权服务有限公司 | 一种平板显示装置焊盘结构 |
CN102800651A (zh) * | 2011-05-24 | 2012-11-28 | 索尼公司 | 半导体装置和半导体装置的制造方法 |
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KR100682434B1 (ko) | 2007-02-15 |
JP2006128352A (ja) | 2006-05-18 |
EP1653510A3 (en) | 2009-09-02 |
CN100428455C (zh) | 2008-10-22 |
TW200629444A (en) | 2006-08-16 |
US20060108691A1 (en) | 2006-05-25 |
TWI276187B (en) | 2007-03-11 |
KR20060052241A (ko) | 2006-05-19 |
EP1653510A2 (en) | 2006-05-03 |
US7646100B2 (en) | 2010-01-12 |
JP4873517B2 (ja) | 2012-02-08 |
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