CN101355044A - 系统级封装及其制造方法 - Google Patents

系统级封装及其制造方法 Download PDF

Info

Publication number
CN101355044A
CN101355044A CNA2008101332367A CN200810133236A CN101355044A CN 101355044 A CN101355044 A CN 101355044A CN A2008101332367 A CNA2008101332367 A CN A2008101332367A CN 200810133236 A CN200810133236 A CN 200810133236A CN 101355044 A CN101355044 A CN 101355044A
Authority
CN
China
Prior art keywords
film
via conductors
semiconductor substrate
liner
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2008101332367A
Other languages
English (en)
Inventor
郑悟进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Publication of CN101355044A publication Critical patent/CN101355044A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种系统器件封装包括半导体衬底，形成于半导体衬底上的金属线，形成于包括金属线的半导体衬底上方的钝化膜，其中钝化膜包括第一和第二开口，形成于钝化膜上方并覆盖第一和第二开口通过第一开口用于连接金属线的衬垫，延伸通过衬垫、钝化膜和半导体衬底以使得直接接触衬垫的通孔导体。通孔导体包括第一暴露的末端，该末端从衬垫处突出且用作第一突起，以及第二暴露的末端，该末端从所述半导体衬底处突出且用作第二突起。结果，可能减少工艺和生产花费的总数并从而提高生产效率。

Description

系统级封装及其制造方法
本申请基于35U.S.C 119要求第10-2007-0073544号(于2007年7月23日递交)韩国专利申请的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及一种制造半导体器件封装的方法，更特别地，涉及一种系统级封装，在该系统级封装中多个半导体芯片在层压结构中相互连接，本发明还涉及一种制造该系统级封装的方法。
背景技术
随着朝向移动的、小型化的以及多功能的电子器件的趋势，具有在单个封装中实现的各种芯片的三维(3D)系统级封装(SIPs)已经引起了极大的关注和兴趣。便携式设备可具有一种结构，在该结构中诸如存储器的半导体器件被分别以封装的形式嵌入(form ofpackages)并相互连接。另一方面，系统级封装技术的使用使得所有的器件可被嵌入到单个封装中，并因此在减小功耗的同时实现产品最小化和各种功能。SIP技术被广泛地应用于存储器，逻辑器件，传感器以及转换器(交换器，convertors)等。在系统级封装结构中，使用穿过半导体芯片的通孔导体(via conductors)来层压的多个半导体芯片相互电连接，而半导体芯片被电连接至印刷电路板(在下文中称为“PCBs”)。
然而，通孔导体在这种系统级封装中的使用会不利地包括复杂的制造工艺。例如，除了在半导体芯片上和/或上方形成通孔导体的工艺外，制造系统级封装的方法进一步需要用于形成将通孔导体与衬垫相连的导体的工艺以及用于形成将半导体芯片电连接至排列在衬垫或PCB上的其他半导体芯片的突起(bumps)的工艺。这些不同的工艺步骤不利地的使得全部制造工艺变得复杂。此外，当使用很难蚀刻的金属材料诸如铜(Cu)来形成突起时，还需要化学机械抛光(在下文中，称为“CMP”)以图样化该铜层，从而进一步使得整个制造工艺变得复杂。
发明内容
本发明具体实施方式涉及一种制造诸如系统级封装的半导体器件封装的方法，以使得多个半导体芯片在层压结构中可以相互连接。
本发明具体实施方式涉及一种系统级封装及其制造方法，该系统级封装可包括多个层压在一起的半导体芯片，由此通过同时形成通孔导体和突起可简化制造工艺。
本发明具体实施方式涉及一种制造系统级封装的方法，该方法至少包括以下步骤中的一步：在设置有金属线的半导体衬底上和/或上方形成钝化膜(passivation film)；图样化该钝化膜以形成第一和第二开口；形成衬垫以使得该衬垫覆盖第一和第二开口并穿过第一开口与金属线连接；在该设置有衬垫的钝化膜上和/或上方形成光刻胶；在与第二开口重叠的区域中形成深沟道以使得该深沟道穿过光刻胶和衬垫并延伸到半导体衬底中预定的深度；形成在深沟道内部的通孔导体以使得该通孔导体与衬垫侧接触(in side-contact)；去除光刻胶以突出通孔导体的一端作为第一突起；然后将第一突起电连接至另一个半导体芯片或印刷电路板。
本发明具体实施方式涉及一种具有在其中层压多个半导体芯片的结构的系统级封装，其中至少一个半导体芯片包括至少以下之一：钝化膜，形成于设置有金属线的半导体衬底上和/或上方，该钝化膜设置有第一和第二开口；衬垫，设置在该钝化膜上和/或上方，该衬垫适用于覆盖第一和第二开口并同样被设定用于穿过第一开口连接金属线；通孔导体，设置在与第二开口重叠的区域中，在该区域中通孔导体穿过衬垫和半导体衬底并与衬垫侧接触；以及第一突起，与通孔导体整合，该第一突起从衬垫处突出。
附图说明
示例的图1到图12根据本发明具体实施方式按顺序示出了制造系统级封装的方法。
具体实施方式
本发明的其他方面、特征和优点从下述结合附图的具体实施方式的详细描述中将更清楚地理解。
如示例图1到示例图12所示，一种根据本发明具体实施方式的用于制造系统级封装的方法包括：在第一半导体芯片50上和/或上方形成衬垫30，形成通孔导体42以使得通孔导体42与第一和第二突起42A和42B整合并穿过从衬垫30到半导体衬底10的结构，以及在层压结构中连接第一半导体芯片50到第二半导体芯片60和PCB70。根据本发明具体实施方式，尽管使用铜(Cu)作为具有低电阻的金属可以形成通孔导体42，但本发明具体实施方式不限于此。
如示例图1所示，在半导体衬底10上和/或上方可以形成适合半导体芯片的下部结构。该下部结构包括多条金属线和多个金属膜。示例图1示意性地示出一个实例，下部结构包括在半导体衬底10上和/或上方形成的多条下金属线12和上金属线18。形成多个接点16以分别电连接上金属线18至下金属线12，同时穿过在上金属线18和下金属线12之间形成的第一绝缘膜14。形成在其中嵌入上金属线18的第二绝缘膜21。在铜(Cu)被用来做上金属线18的情况下，可以图样化绝缘膜21以形成沟道，上金属线18将形成在该沟道处，沉积铜以使得铜嵌入沟道中并覆盖绝缘膜21的表面，然后通过CMP蚀刻铜直到暴露该绝缘膜21，从而形成具有与绝缘膜21的最上表面共面的最上表面的上金属线18。然后在嵌入绝缘膜21的上金属线18上和/或上方可以形成具有双层结构的第一和第二钝化膜20和22。通过沉积诸如SiNx的氮化物，可以形成具有厚度大约
Figure A20081013323600091
到
Figure A20081013323600092
的第一钝化膜20。通过沉积如原硅酸四乙酯(tetra ethyl ortho silicate(TEOS))的具有低介电常数的氧化物绝缘体可以形成具有厚度大约到
Figure A20081013323600094
的第二钝化膜22。
如示例图2所示，然后通过光刻法和蚀刻工艺可以图样化第一和第二钝化膜20和22以形成第一和第二开口24和26。第一开口24暴露将要电连接至在随后工艺中形成的衬垫的上金属线18。第二开口26提供在随后工艺中形成通孔导体的区域。
如示例图3所示，然后在设置有开口24和26的第二钝化膜22上和/或上方可以顺序地形成阻挡金属28和衬垫金属30。例如，在形成铝(Al)衬垫的情况下，在第二钝化膜22上和/或上方可以沉积铝阻挡金属28和铝衬垫金属30。
如示例图4所示，然后通过光刻法和蚀刻工艺可以图样化衬垫金属30和阻挡金属28以形成覆盖第一和第二开口24和26的衬垫32。层压有阻挡金属28和衬垫金属30的衬垫32可以穿过第一开口24电连接至上金属线18。
如示例图5所示，然后在设置有衬垫32的第二钝化膜22上和/或上方可以涂覆光刻胶34。例如，光刻胶34可以被涂覆达到大约2μm到10μm的厚度，且可以从具有大约90∶1的高选择率的光刻胶中选择。
如示例图6所示，通过光刻法工艺可以图样化光刻胶34以形成沟道36来打开随后形成通孔导体的区域。穿过光刻胶34的沟道36与示例图2中所示的第一和第二钝化膜20和22的第二开口26重叠。
如示例图7所示，深沟道36穿过光刻胶34、衬垫32、绝缘膜14和21、钝化膜20和22且延伸至半导体衬底10中的预定的深度。使用快速蚀刻设备可以形成深沟道36以使得深沟道36穿过衬垫32和绝缘膜14和21，且延伸至半导体衬底10中的预定的深度，但没有完全穿过半导体衬底10。例如，深沟道36可以具有大约10μm到30μm的宽度和大约40μm到100μm的深度。深沟道36可以穿过衬垫32以使得暴露衬垫32的侧表面(即，倾斜的和垂直的侧表面)。
如示例图8和9所示，然后在深沟道36的侧壁上和/或上方可以形成阻挡金属40。然后可以在深沟道36中嵌入诸如铜的金属材料以形成通孔导体42。然后可以实施铜退热工艺。在有机绝缘体被用来作半导体衬底10或绝缘膜14的情况下，可以形成阻挡金属40以防止铜扩散到有机绝缘膜14中。阻挡金属40可以是诸如Ti、TiN、TiSiN、Ta和TaN中至少一种金属。籽晶金属可以在阻挡金属40上形成且然后经历使用电镀或化学电镀的铜镀以形成完全填充深沟道36的铜通孔导体42。然后为了稳定性铜通孔导体42可以经历20到120分钟温度在150℃到250℃的退火。通孔导体42可以穿过阻挡金属40连接到衬垫32的侧表面(即，倾斜的和垂直的侧面)。换句话说，通孔导体42可以与衬垫32侧接触。可以形成通孔导体42以使得其具有大约10μm到20μm的长度。
如示例图10所示，蚀刻光刻胶34以使得通孔导体42的上部从衬垫32突出到外部。衬垫32向上的通孔导体42的突起用作可以电连接至另一个半导体芯片或PCB的第一突起42A。
如示例图11所示，然后半导体衬底10的后表面可以经历磨削(grinding)和蚀刻以使得通孔导体42的下部从衬底10突出到外部。半导体衬底10的后表面可以经历使用更高的硅蚀刻率的蚀刻法向后磨削(back grinding)直到通孔导体42暴露。由于通孔导体42的蚀刻率低于半导体衬底10的蚀刻率，从底部突出通孔导体42的下部。从半导体衬底10向下突出的通孔导体42从而可以用作可以电连接至另一个半导体芯片或PCB的第二突起42B。半导体衬底10的向后磨削致使阻挡金属40出现在将被蚀刻的通孔导体42的下部中，使通孔导体42的后表面能够暴露。从而，穿过半导体芯片50的通孔导体42可以同时完整地形成具有突起结构的第一和第二突起42A和42B，通孔导体42穿过衬垫32并与衬垫32侧接触。因此，很可能消除包括用于形成导体将衬垫连接至通孔导体的工艺、用于形成突起的工艺以及铜CMP工艺的其它工艺的必要性，从而减少工艺总数。
在当半导体芯片50出现作为最外层的情况下，没必要电连接半导体衬底10的后表面至另一个芯片，换句话说，不需要第二突起42B，可以省略用于向后磨削如示例图11中所示的半导体衬底10的工艺。
如示例图12所示，在层压结构中可以实施连接工艺以连接示例图11所示半导体芯片50至另一个半导体芯片60和PCB70。例如，可以实施连接工艺以使得从半导体衬底10突出的第二突起42B电连接至另一个半导体芯片60，该第二突起42B与半导体芯片50的通孔导体42整合。此外，可以实施连接工艺以使得从衬底32突出的第一突起42A电连接至PCB 70，该第一突起42A与半导体芯片50的通孔导体42整合。
从上所述清楚的知道，根据半导体器件封装及其制造方法，与衬垫侧接触且从而直接连接的通孔导体同时完整地形成有突起。结果，很可能减少工艺和生产花费的总数且从而提高生产效率。
尽管本文中描述了多个具体实施方式，但是应该理解，本领域技术人员可以想到多种其他修改和具体实施方式，他们都将落入本公开的原则的精神和范围内。更特别地，在本公开、附图、以及所附权利要求的范围内，可以在主题结合排列的排列方式和/或组成部分方面进行各种修改和改变。除了组成部分和/或排列方面的修改和改变以外，可选的使用对本领域技术人员来说是显而易见的选择。

Claims (20)

1.一种方法，包括：
在设置有金属线的半导体衬底上方形成钝化膜；
图样化所述钝化膜以形成第一和第二开口；以及
在所述第一和第二开口上方形成衬垫并通过所述第一开口连接至所述金属线；
在包括所述衬垫的所述钝化膜上方形成光刻胶；以及
在空间上相应地所述第二开口的区域中形成深沟道且延伸穿过所述光刻胶和所述衬垫以及钝化膜到所述半导体衬底中达到预定的深度；以及
在所述深沟道中形成通孔导体，以使得所述通孔导体直接接触所述衬垫；以及
通过去除所述光刻胶以使得所述通孔导体的一个末端突出至所述外部形成第一突起；以及
电连接所述第一突起至第二半导体芯片和印刷电路板中的至少一个。
2.根据权利要求1所述的方法，其中，形成所述钝化膜包括：
在所述半导体衬底上方形成氮化膜作为第一钝化膜；以及
在所述氮化膜上方形成氧化膜作为第二钝化膜。
3.根据权利要求2所述的方法，其中所述氮化膜包括氮化硅(SiNx)膜，所述氧化膜包括原硅酸四乙酯(TEOS)膜。
4.根据权利要求3所述的方法，其中形成厚度范围在
Figure A2008101332360003C1
到
Figure A2008101332360003C2
的所述氮化硅膜，以及形成厚度范围在
Figure A2008101332360003C3
到
Figure A2008101332360003C4
的所述TEOS膜。
5.根据权利要求1所述的方法，其中形成厚度范围在2μm到10μm的所述光刻胶。
6.根据权利要求5所述的方法，其中所述光刻胶具有90∶1的蚀刻选择率。
7.根据权利要求1所述的方法，其中形成具有宽度范围在10μm到30μm且深度大约在40μm-100μm的所述深沟道。
8.根据权利要求1所述的方法，进一步包括，在形成所述深沟道之后，但在形成所述通孔导体之前：
在所述深沟道的侧壁上顺序地形成阻挡金属，以及在所述深沟道中形成籽晶金属；以及
使所述籽晶金属经历电镀工艺以从而形成通孔导体；以及
使所述通孔导体经历退火工艺。
9.根据权利要求8所述的方法，其中所述通孔导体包括铜材料。
10.根据权利要求9所述的方法，其中使用电镀和化学电镀中的至少一种形成所述通孔导体。
11.根据权利要求8所述的方法，其中所述阻挡金属包括Ti、TiN、TiSiN、Ta和TaN中的至少一种。
12.根据权利要求8所述的方法，其中形成厚度范围在10μm到20μm的所述通孔导体。
13.根据权利要求8所述的方法，其中在150℃到250℃实施持续20到120分钟的所述退火工艺。
14.根据权利要求1所述的方法，进一步包括，在形成所述第一突起后：
通过蚀刻所述半导体衬底的所述后表面以突出所述通孔导体的另一末端形成第二突起。
15.一种设备包括：
半导体衬底；
金属线，形成于所述半导体衬底；
钝化膜，形成于包括所述金属线的所述半导体衬底上方，其中所述钝化膜包括第一和第二开口；
衬垫，形成于所述钝化膜上方并覆盖所述第一和第二开口用于穿过所述第一开口连接所述金属线；
通孔导体，延伸通过所述衬垫、所述钝化膜以及所述半导体衬底以使得所述通孔导体直接接触所述衬垫，
其中所述通孔导体包括第一暴露末端，所述末端从所述衬垫处突起且用作第一突起。
16.根据权利要求15所述的设备，其中所述通孔导体包括第二暴露末端，所述末端从所述半导体衬底处突起且用作第二突起。
17.根据权利要求15所述的设备，其中所述钝化膜包括多层的结构。
18.根据权利要求17所述的设备，其中所述多层的结构包括：
氮化膜，形成于所述半导体衬底上方作为第一钝化膜；以及
氧化膜，形成于所述氮化膜上方作为第二钝化膜。
19.根据权利要求18所述的设备，其中所述氮化膜包括形成的厚度范围在
Figure A2008101332360005C1
到
Figure A2008101332360005C2
的氮化硅(SiNx)膜。
20.根据权利要求18所述的设备，其中所述氧化膜包括形成的厚度范围在到
Figure A2008101332360005C4
的原硅酸四乙酯(TEOS)膜。
CNA2008101332367A 2007-07-23 2008-07-22 系统级封装及其制造方法 Pending CN101355044A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070073544A KR100889553B1 (ko) 2007-07-23 2007-07-23 시스템 인 패키지 및 그 제조 방법
KR1020070073544 2007-07-23

Publications (1)

Publication Number Publication Date
CN101355044A true CN101355044A (zh) 2009-01-28

Family

ID=40176106

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2008101332367A Pending CN101355044A (zh) 2007-07-23 2008-07-22 系统级封装及其制造方法

Country Status (6)

Country Link
US (1) US20090026614A1 (zh)
JP (1) JP2009027174A (zh)
KR (1) KR100889553B1 (zh)
CN (1) CN101355044A (zh)
DE (1) DE102008032510A1 (zh)
TW (1) TW200905756A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101539864B (zh) * 2009-02-10 2011-11-23 北京交通大学 自适应的保障可信客户虚拟域正常启动的方法
CN104752404A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 用于封装测试的半导体结构及其形成方法
CN106449575A (zh) * 2015-08-07 2017-02-22 晶宏半导体股份有限公司 半导体装置的凸块结构
CN107039377A (zh) * 2017-06-16 2017-08-11 京东方科技集团股份有限公司 一种显示面板、其制作方法及显示装置

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932608B2 (en) * 2009-02-24 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via formed with a post passivation interconnect structure
KR101918609B1 (ko) 2012-01-11 2018-11-14 삼성전자 주식회사 집적회로 소자
US9806013B2 (en) 2013-08-28 2017-10-31 Institute Of Technical Education Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device
MA36343B1 (fr) * 2013-10-14 2016-04-29 Nemotek Technologies Procédé de métallisation en cuivre destiné à la fabrication d'un circuit intégré en utilisant la technologie wafer level packaging 3d
US9281284B2 (en) * 2014-06-20 2016-03-08 Freescale Semiconductor Inc. System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
US9768066B2 (en) * 2014-06-26 2017-09-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming conductive vias by direct via reveal with organic passivation
KR102222485B1 (ko) * 2014-09-18 2021-03-04 에스케이하이닉스 주식회사 관통 전극을 갖는 반도체 소자, 이를 구비하는 반도체 패키지 및 반도체 소자의 제조방법
KR101688081B1 (ko) * 2016-02-05 2016-12-20 앰코 테크놀로지 코리아 주식회사 Ｅｔｓ 구조
US10418311B2 (en) 2017-03-28 2019-09-17 Micron Technology, Inc. Method of forming vias using silicon on insulator substrate
US10510631B2 (en) * 2017-09-18 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fan out package structure and method of manufacturing the same
JP7353748B2 (ja) * 2018-11-29 2023-10-02 キヤノン株式会社 半導体装置の製造方法および半導体装置
DE102020128994A1 (de) * 2020-05-27 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-Package und Verfahren zur Herstellung desselben
US11621214B2 (en) 2020-05-27 2023-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method for manufacturing the same
US11631631B2 (en) * 2021-05-28 2023-04-18 Advanced Semiconductor Engineering, Inc. Semiconductor device including via structure for vertical electrical connection
US11784111B2 (en) 2021-05-28 2023-10-10 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310547A (ja) * 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP3245076B2 (ja) * 1995-12-06 2002-01-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 浅い分離溝を平坦化する方法
JP4222525B2 (ja) * 1996-07-12 2009-02-12 川崎マイクロエレクトロニクス株式会社 半導体装置、その製造方法及び反射型液晶表示装置
WO2001088972A1 (en) * 2000-05-15 2001-11-22 Asm Microchemistry Oy Process for producing integrated circuits
JP4329235B2 (ja) * 2000-06-27 2009-09-09 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2002198327A (ja) * 2000-12-27 2002-07-12 Sharp Corp 半導体装置の製造方法
US20030119308A1 (en) * 2001-12-20 2003-06-26 Geefay Frank S. Sloped via contacts
JP3866978B2 (ja) * 2002-01-08 2007-01-10 富士通株式会社 半導体装置の製造方法
US20050179120A1 (en) * 2003-12-16 2005-08-18 Koji Yamaguchi Process for producing semiconductor device, semiconductor device, circuit board and electronic equipment
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
KR20050115143A (ko) * 2004-06-03 2005-12-07 매그나칩 반도체 유한회사 반도체 소자의 인덕터 제조방법
KR100548578B1 (ko) * 2004-07-20 2006-02-02 주식회사 하이닉스반도체 시스템 인 패키지의 비아패턴 형성방법
JP2006100698A (ja) * 2004-09-30 2006-04-13 Toshiba Corp 半導体装置の製造方法
JP4393343B2 (ja) * 2004-10-22 2010-01-06 株式会社東芝 半導体装置の製造方法
JP4063277B2 (ja) * 2004-12-21 2008-03-19 セイコーエプソン株式会社 半導体装置の製造方法
JP4349278B2 (ja) * 2004-12-24 2009-10-21 セイコーエプソン株式会社 半導体装置の製造方法
DE102005033254B4 (de) * 2005-07-15 2008-03-27 Qimonda Ag Verfahren zur Herstellung eines Chip-Trägersubstrats aus Silizium mit durchgehenden Kontakten
KR100621438B1 (ko) * 2005-08-31 2006-09-08 삼성전자주식회사 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
KR20070073544A (ko) 2006-01-04 2007-07-10 김명원 침대가 자동으로 좌우 반복 이동이 되어지는 유아용흔들침대
KR100752198B1 (ko) * 2006-09-13 2007-08-27 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100824635B1 (ko) * 2006-09-13 2008-04-24 동부일렉트로닉스 주식회사 시스템 인 패키지를 이용한 인덕터 제조 방법
US7456432B2 (en) * 2006-11-20 2008-11-25 Tpo Displays Corp. System having electrostatic discharge protection structure and method for manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101539864B (zh) * 2009-02-10 2011-11-23 北京交通大学 自适应的保障可信客户虚拟域正常启动的方法
CN104752404A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 用于封装测试的半导体结构及其形成方法
CN104752404B (zh) * 2013-12-27 2019-01-25 中芯国际集成电路制造(上海)有限公司 用于封装测试的半导体结构及其形成方法
CN106449575A (zh) * 2015-08-07 2017-02-22 晶宏半导体股份有限公司 半导体装置的凸块结构
CN106449575B (zh) * 2015-08-07 2020-07-24 晶宏半导体股份有限公司 半导体装置的凸块结构
CN107039377A (zh) * 2017-06-16 2017-08-11 京东方科技集团股份有限公司 一种显示面板、其制作方法及显示装置
US11099615B2 (en) 2017-06-16 2021-08-24 Boe Technology Group Co., Ltd. Display panel, manufacturing method thereof and display device

Also Published As

Publication number Publication date
TW200905756A (en) 2009-02-01
US20090026614A1 (en) 2009-01-29
JP2009027174A (ja) 2009-02-05
DE102008032510A1 (de) 2009-02-05
KR20090010442A (ko) 2009-01-30
KR100889553B1 (ko) 2009-03-23

Similar Documents

Publication Publication Date Title
CN101355044A (zh) 系统级封装及其制造方法
CN101771010B (zh) 集成电路结构
US8039962B2 (en) Semiconductor chip, method of fabricating the same and stack package having the same
KR101692434B1 (ko) 반도체 소자 및 그 제조 방법
US9449875B2 (en) Wafer backside interconnect structure connected to TSVs
US7964959B2 (en) Semiconductor chip, method of fabricating the same and stacked package having the same
TWI544597B (zh) 積體電路元件以及半導體製程
CN101924096B (zh) 硅通孔结构及其形成工艺
CN102456650B (zh) 半导体基板的导电结构以及其制造方法
CN102867777B (zh) 在半导体衬底中形成接地硅通孔
US8552554B2 (en) Heat dissipation structure for electronic device and fabrication method thereof
US7863747B2 (en) Semiconductor chip, method of fabricating the same and semiconductor chip stack package
JP2010045371A (ja) 導電性保護膜を有する貫通電極構造体及びその形成方法
KR20120000748A (ko) 반도체 소자 및 그 제조 방법
TWI768208B (zh) 半導體晶片及其製造方法
KR20100100629A (ko) 3차원 ＳＩＰ(Ｓｙｓｔｅｍ―ｉｎ―Ｐａｃｋａｇｅ) 구조물
US20080061443A1 (en) Method of manufacturing semiconductor device
US6803304B2 (en) Methods for producing electrode and semiconductor device
KR100777926B1 (ko) 반도체 소자 및 그 제조방법
US8278755B2 (en) Heat dissipation structure for electronic device and fabrication method thereof
US11315904B2 (en) Semiconductor assembly and method of manufacturing the same
KR20150116137A (ko) 자기정렬된 보호막으로 캡핑된 관통전극을 갖는 반도체 소자 및 그 제조방법
CN101635275A (zh) 半导体器件、半导体芯片及它们的制造方法和叠层封装
KR100718451B1 (ko) 반도체 장치의 금속 배선 및 그 제조 방법
CN117727721A (zh) 基于晶片的模制倒装芯片式可路由ic封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20090128