CN1677659A - 穿通电极、设有穿通电极的隔片及其制造方法 - Google Patents

穿通电极、设有穿通电极的隔片及其制造方法 Download PDF

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Publication number
CN1677659A
CN1677659A CNA2005100625051A CN200510062505A CN1677659A CN 1677659 A CN1677659 A CN 1677659A CN A2005100625051 A CNA2005100625051 A CN A2005100625051A CN 200510062505 A CN200510062505 A CN 200510062505A CN 1677659 A CN1677659 A CN 1677659A
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film
projection
electrode
silicon substrate
hole
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CN100468712C (zh
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小室雅宏
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Renesas Electronics Corp
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NEC Corp
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Abstract

提供一种穿通电极，该穿通电极提供优异的性能和可以通过简单工艺制造。在包括硅衬底的硅隔片中，设置与硅衬底的表面和贯穿硅衬底的穿通孔侧壁接触的绝缘厚膜。穿通栓塞的上表面被再处理为低于硅衬底和绝缘厚膜之间的界面的水平面，由此限定高度间隙。然后形成第一凸块，第一凸块连接到穿通栓塞的再处理表面，以及具有比绝缘厚膜的上表面处的穿通栓塞更大的直径。

Description

穿通电极、设有穿通电极的隔片及其制造方法
本申请基于日本专利申请号2004-099681。在此将其内容引入作为参考。
技术领域
本发明涉及穿通电极、设有穿通电极的隔片及其制造方法。
背景技术
近年来，为了实现更高集成度的半导体芯片，最近有力地进行半导体芯片如LSI的三维实施方案的研发。这些尝试包括在半导体衬底上设置穿通电极。在H.Yonemura等的″Time-Modulated Cu-PlatingTechnique for Fabricating High-Aspect-Ratio Viasfor Three-dimensionalStacked LSI System″2002.Proceedings of the International InterconnectTechnology Conference，pp.75 to 77(H.Yonemura等.)中公开了穿通电极的例子。该文献公开了由Cu栓塞构成的穿通电极，Cu栓塞形成为贯穿硅衬底，Cu栓塞的上表面上具有形成的凸块。提供这种穿通电极允许，当三维地层叠多个半导体芯片衬底时，通过不需要执行引线键合的短距离在衬底和外部元件之间实现电连接。
发明内容
但是，由于本发明人对引用的技术进行回顾，现在发现充分保证金属膜和构成穿通电极的凸块之间的粘附力仍然具有改进的余地。此外，发现在穿通电极的制造工序中还有进一步简化的空间。
根据本发明，提供一种穿通电极，包括设有穿通孔的硅衬底；形成在硅衬底表面上的绝缘保护膜，具有与穿通孔连接的开口；通过将导电材料嵌入穿通孔中形成的穿通栓塞；以及连接到穿通栓塞的凸块；其中凸块被连接到穿通孔内的穿通栓塞，以及位于穿通孔外的部分凸块具有比位于穿通孔内的部分凸块的更大直径。在这种结构中，在衬底的表面上凸块可以被连接到穿通栓塞。
在由此构成的穿通电极中，凸块连接到贯穿硅衬底的穿通孔内的穿通栓塞。这意味着在硅衬底上形成凹陷部分，以及处于凹陷部分中的穿通栓塞和凸块连接。此外，凸块在穿通孔外具有更大的直径。由此，因为锚定效应凸块和穿通栓塞紧密地粘结。而且，充分地保证凸块和穿通栓塞之间的电气接触，导致其间的接触电阻减小。此外，由于设置了绝缘保护膜，因此在形成穿通电极的表面上凸块可以不与硅衬底直接接触。
在本发明中，导电材料可以由金属材料制成。这些进一步保证穿通电极的导电性。
在根据本发明的穿通电极中，凸块的较大直径部分可以与绝缘保护膜接触。这种结构可以使凸块与硅衬底接触。这增强电极的必需性能的可靠性。
根据本发明的穿通电极还可以包括覆盖穿通栓塞的侧壁而形成的侧壁绝缘膜。这种结构允许抑制沿穿通电极的侧边周边在硅衬底中产生寄生电容。这进一步增加穿通电极的可靠性。
在根据本发明的穿通电极中，可以连续地和整体地形成侧壁绝缘膜和绝缘保护膜。这种结构允许通过简单工艺制造该结构。
在此的术语“连续地和整体地形成”意味着形成连续的和统一的结构。优选，该结构由不形成结点部分的一个部分构成。形成连续的和统一的结构允许防止侧壁绝缘膜和绝缘保护膜互相分开或分离。由此，这种结构进一步保证绝缘性能和进一步增加电极的可靠性。
在根据本发明的穿通电极中，穿通栓塞可以包括覆盖穿通孔内部侧壁的阻挡膜，以及金属膜被阻挡膜围绕覆盖。在本发明中，阻挡膜用作绝缘膜，防止包含于金属膜中的金属成分扩散到穿通栓塞的外部。这种结构有效地防止金属膜中的金属成分扩散到半导体衬底中。
根据本发明，提供一种制造穿通电极的方法，包括在硅衬底的一个表面上形成孔；形成覆盖孔的表面和内壁的绝缘膜；形成填充孔的导电薄膜；在导电薄膜上执行抛光或深刻蚀，以便除去在用于曝光绝缘膜的孔外形成的部分导电薄膜，以及再处理导电薄膜的表面为比其表面更靠内的硅衬底平面，用于形成导电栓塞和凹陷部分；在导电栓塞的再处理表面上生长金属膜，以由此填充凹陷部分，以及进一步形成凸块，凸块在孔外具有比位于孔内的部分凸块更大的直径；以及抛光用于曝光导电栓塞的硅衬底的其它表面，由此形成穿通电极。
由此布置的制造方法包括再处理导电薄膜的表面到比所述硅衬底的表面更靠内的高度，由此形成凹陷部分，亦即。硅衬底的表面上的再处理部分，由此在该表面上形成高度间隙。因此，这种凹陷的部分保证导电栓塞和凸块的连接。此外，这种方法消除了，当形成凸块时，在硅衬底表面上形成绝缘膜和在确定的位置在其上形成开口的需要。由此，穿通简单的工艺可以稳定地制造提供优异性能的穿通电极，且因此制造成本被减小。
在本发明中，绝缘膜可以形成为厚膜。这种结构进一步保证穿通电极和硅衬底之间的绝缘，以及防止硅衬底中产生寄生电容。
在根据本发明的制造方法中，形成凸块可以包括在导电栓塞的再处理表面上有选择地生长金属膜。利用这种工艺，通过锚定效应可以进一步获得在凸块和穿通栓塞之间有效地具有粘附力的凸块结构。
在根据本发明的制造方法中，形成凸块可以包括在导电栓塞的表面上和凹陷部分的侧壁上形成阻挡金属膜，以及利用阻挡金属膜作为基体生长金属膜。这种方法进一步保证导电栓塞和凸块之间的电气接触。此外，金属膜可以从导电栓塞的表面和凹陷部分的侧表面更确定地生长。由此，可以增加制造凸块的稳定性。
根据本发明的制造方法可以包括在形成导电栓塞之后，从与一个表面相对的其另一表面有选择地除去部分硅衬底，由此曝光导电栓塞的表面；以及在导电栓塞的曝光表面上生长其它金属膜，由此在后表面上形成凸块。
另外，根据本发明的制造方法可以包括，在形成穿通电极之后，在导电栓塞的曝光表面上生长其它金属膜。由此在后表面上形成凸块。
在本发明中，由于孔的内壁覆有绝缘膜，因此可以形成后表面上的凸块，而不附加地形成用于在后表面上形成凸块的其它绝缘膜，亦即硅绝缘体的其它表面。这些允许简化制造工序，且因此更容易地便于穿通电极的制造。这里，在本发明中，从形成凸块的金属膜和在后表面上形成其它凸块的金属膜可以由相同的材料或不同的材料构成。
在根据本发明的制造方法中，形成绝缘膜可以包括在硅衬底的一个表面上形成硅氧化物膜。这种方法进一步保证硅衬底表面的绝缘和保护。此外，这种方法进一步保证抑制沿穿通孔的侧周边在硅衬底中产生寄生电容。
根据本发明的制造方法可以包括，在形成绝缘膜之后和形成导电薄膜之前，在设有孔的硅衬底的一个表面上形成阻挡膜。这种方法允许有效地抑制导电薄膜中的导电材料扩散到硅衬底中。
根据本发明，提供一种包括穿通电极的硅隔片。
根据本发明，提供一种制造硅隔片的方法，包括通过制造穿通电极的上述方法形成穿通电极。
根据本发明的硅隔片包括如上所述形成的穿通电极。由此，导电栓塞和凸块互相紧密地锚定，以及充分地保证硅衬底的截面方向中的导电路径。因此，在将被三维地层叠的多个半导体器件之间可以有利地设置这种隔片，用于保证那些器件之间的电连接。
如上所述，本发明提供一种穿通电极，该穿通电极提供优异的性能和可以通过简单的工艺来制造，其中通过将导电材料嵌入穿通孔中形成的穿通栓塞贯穿硅衬底以及凸块与穿通孔内的穿通栓塞连接，以及凸块在穿通孔外具有更大直径的部分。
附图说明
从下面结合附图的详细说明将使本发明的上述及其他目的、优点和特点更明显，其中：
图1示出了根据本发明的实施例的硅隔片结构的示意性剖面图；
图2A至2C是用于说明图1的硅隔片的制造工序的示意性剖面图；
图3D至3F是用于说明图1的硅隔片的制造工序的示意性剖面图；
图4G和4H是用于说明图1的硅隔片的制造工序的示意性剖面图；
图5I是用于说明图1的硅隔片的制造工序的示意性剖面图；
图6A和6B示出了穿通电极结构的示意性平面图和剖面图；
图7示出了根据实施例包括硅隔片的半导体器件结构的示意性剖面图；
图8示出了根据比较例子的硅隔片结构的示意性剖面图；
图9A至9C是用于说明根据比较例子的硅隔片的制造工序的示意性剖面图；
图10D至10F是用于说明根据比较例子的硅隔片的制造工序的示意性剖面图；以及
图11G和11H是用于说明根据比较例子的硅隔片的制造工序的示意性剖面图。
具体实施方式
现在将参考说明性实施例描述本发明。所属领域的技术人员将认识到使用本发明的教导可以完成许多选择性实施例，以及发明不局限于用于说明性目的而说明的实施例。
首先，将描述设有根据本发明的穿通电极的隔片。该隔片被布置在三维地层叠的半导体器件之间，用于保证电连接，半导体器件形成在衬底上。
图7示出了其上层叠多个芯片的半导体器件结构的示意性剖面图。图7所示的半导体器件60包括MPU/ASIC芯片71、大容量系统存储芯片72和在基础衬底61上依次层叠的128MNOR快闪存储芯片73，以及衬底61和芯片71通过键合引线67连接，衬底61和芯片73通过键合引线65连接。
通常要求基础衬底的第二层上的半导体芯片的尺寸比基础衬底的第一层上的尺寸更小，以便保证用于布置连接用的键合引线的空间，这对待层叠的半导体芯片的容量和性能自然地产生限制。
但是，如图7所示，即使当第二层芯片72大于第一层芯片71时，其间插入隔片11和通过穿通电极5由此连接电极在第一层芯片71和第二层芯片72之间产生空间，由此允许布置用于连接的键合引线67。
根据本发明的设有穿通电极的隔片可以有利地引入这种半导体器件。在下面，将参考附图描述包括穿通电极的隔片的实施例。这里，就所有附图而言，共同采用的组件将给出相同的数字，以及视情况而定将省略其描述。此外，为了实施例的描述，构成穿通电极的穿通栓塞的再处理表面的隔片表面将称为上面(表面)，以及相对的表面称为下表面(后表面)。
图1示出了根据该实施例的硅隔片结构的示意性剖面图。图1所示的硅隔片100包括从上表面至其下表面贯穿硅衬底101的穿通电极102，硅衬底101是半导体衬底。尽管图1示出了其中一个硅衬底101包括两个穿通电极102的结构，但是穿通电极102的数目或其位置不被具体地限制，而是根据将引入硅隔片100的半导体器件的结构而决定。
在硅衬底101的上表面上和贯穿硅衬底101的穿通孔的内侧表面上，设置与硅衬底101接触的绝缘厚膜103。在贯穿硅衬底101的穿通孔内部，依次填充绝缘厚膜103、SiN膜105和穿通栓塞107。由此，穿通栓塞107的侧壁通过SiN膜105覆有绝缘厚膜103，由此与硅衬底101隔开。
用于构成绝缘厚膜103的材料将从稳定的阻止在之后将描述的穿通电极102的制造工序中执行的处理的材料当中选出。此外，绝缘厚膜103的优选材料是能抑制在硅衬底101中产生寄生电容的选择材料。例如，优选采用SiO2膜等。同样，优选决定绝缘厚膜103的厚度为保持穿通电极102的制造工序的稳定性和允许抑制寄生电容的产生。当采用SiO2膜作为绝缘厚膜103时，其厚度可以是例如300nm至5μm。用300μm以上的厚度，可以有效地防止制造工序过程中穿通电极102的劣化。由此，可以安全地防止通过硅衬底101和第一凸块111或第二凸块115的接触引起漏电流的出现。用5μm以下的厚度，硅隔片100和穿通电极102可以形成为更小和更薄。
穿通电极102包括穿通栓塞107、底部凸块金属膜109、第一凸块111、第二凸块115和SiN膜105。穿通栓塞107用作嵌入形成在硅衬底101中的穿通孔内部的导电材料。穿通栓塞107的材料可以是金属如铜。通过底部凸块金属膜109形成与穿通栓塞107的上表面接触的第一凸块111。
SiN膜105用作穿通栓塞107的侧壁上覆盖的阻挡膜，用于防止穿通栓塞107中的金属成分扩散到绝缘厚膜103和硅衬底101中。阻挡膜可以由除SiN之外的材料形成，只要它是绝缘材料。这里，SiN膜105比绝缘厚膜103更薄。SiN膜105的厚度可以是例如，10nm以上。这种厚度保证阻挡膜的固有性能。
穿通栓塞107的上表面与硅衬底101和绝缘厚膜103之间的界面相比位于穿通孔内的更内水平面，由此在那些表面之间形成高度间隙113。穿通栓塞107的再处理空间填有部分第一凸块111。由此穿通栓塞107从硅衬底101和绝缘厚膜103之间的界面在再处理表面，亦即，在凹陷部分与第一凸块111接触。第一凸块111以屋檐(eaves)状形状在穿通孔外向外展开，形成近似T形的截面。换句话说，位于穿通孔外的第一凸块111的直径大于位于穿通孔内的第一凸块111的直径。第一凸块111可以由金属如Au构成。
第二凸块115布置为与穿通栓塞107的下表面接触。第二凸块115形成在绝缘厚膜103和硅衬底101之间的接触面内。由此，第二凸块115可靠地与硅衬底101保持电连接。第二凸块115可以由金属如Ni构成。第二凸块115可以在其表面上设有金属涂层如Au。
现在将描述制造硅隔片100的方法。图2A至2C，3D至3F，4G，4H和图51示出了硅隔片100的制造工序的示意性剖面图。
首先，光刻胶被涂敷到硅衬底101的表面，执行光刻以形成抗蚀剂图形，其中在对应于穿通栓塞107的位置形成开口。然后利用抗蚀剂图形作为掩模执行刻蚀，以除去部分硅衬底101，由此形成开口117(图2A)。
在除去光刻胶之后，在包括开口117(图2B)的硅衬底101的上表面上到处形成绝缘厚膜103。绝缘厚膜103可以是通过CVD技术淀积的SiO2膜。然后在硅衬底101的上表面上到处形成将用作阻挡膜的SiN膜105，硅衬底101上通过等离子体CVD技术设置例如50nm厚度的绝缘厚膜103(图2C)。
此后，在SiN膜105上形成籽晶Cu膜(在附图中未示出)。然后进行电解镀以用Cu膜完全地填充开口117，以及执行退火，以生长Cu晶粒。此时，完成Cu膜119的形成(图3D)。
上述工序之后进行CMP(化学机械抛光)工序，通过该工序从硅衬底101的上表面除去Cu膜119和SiN膜105。这里，选择CMP工序的条件，以便Cu膜119的上表面下降到比硅衬底101和绝缘厚膜103(图3E)之间的接触面更低的水平面。具体地，适当地选择浆料，以便由于发生Cu膜119的氧化，化学抛光优于绝缘厚膜103的机械抛光。
由此，优先抛光Cu膜119，同时留下硅衬底101上未除去的绝缘厚膜103，由此在Cu膜119的上表面和硅衬底101和绝缘厚膜103之间的界面之间形成高度间隙113(凹陷)。以此方式，通过压低Cu膜119，在部分开口117中限定凹陷部分131，以便其上表面低子绝缘厚膜103的上表面。因此，凹陷部分131的底部部分对应于再处理表面，亦即凹陷表面。用于金属抛光的浆料可以采用作为这种抛光浆料。
然后，遍及衬底101涂敷将用作底部凸块金属膜109的TiW膜和抗蚀剂膜121，以及执行光刻，以形成开口123，由此曝光底部凸块金属膜109(图3F)。开口123位于穿通栓塞107以及沿穿通栓塞107的侧壁布置的SiN膜105和绝缘厚膜103上。
现在执行电解镀，以基于底部凸块金属膜109的曝光部分有选择地生长Au膜。Au膜生长为填充凹陷部分131和在凹陷部分131外的扩充其直径，由此形成与绝缘厚膜103接触的第一凸块111。抗蚀剂膜121被除去。然后，利用第一凸块111作为掩模执行湿法刻蚀，以由此除去除形成在第一凸块111的形成区域中的部分外的底部凸块金属膜109(图4G)。
然后通过粘合剂120和剥落层122将其上提供了第一凸块111的硅衬底101的表面粘附到支撑元件125(图4H)。粘合剂120可以是UV固化的材料或热固性材料。对于剥落层122，具有与粘合剂120不同吸收波长的材料，当通过这种吸收波长的光照射时发泡的材料。同时，支撑元件125可以由抵抗之后将描述的硅衬底101的减薄工序如后表面研磨过程中在其处施加的热、化学、外力等的材料构成。这种材料的例子包括石英和玻璃如PyrexTM，可以采用玻璃之外的材料，包括塑料如丙烯酸树脂。
此后，硅衬底101的后表面被研磨(图5I)。机械地执行后表面研磨。研磨之后硅衬底101的可以设置为例如50至200μm，取决于其中将引入硅隔片100的半导体器件的层叠结构。
然后执行非电解镀，以在穿通栓塞107的曝光部分上生长Ni膜。这里，调整Ni膜的生长条件，以致Ni膜形成在比穿通栓塞107的侧壁上设置的绝缘厚膜103和硅衬底101之间的接触面更靠内的区域中。然后在其表面上用金镀Ni膜。在此阶段，在穿通栓塞107的其他表面上形成第二凸块115。
在从硅衬底101剥落支撑元件125时，支撑元件125被除去，以及获得如图1所示的硅隔片100。
现在将描述图1所示的硅隔片100的有益效果。
在硅隔片100中，硅衬底101的穿通孔中填充的穿通栓塞107的表面位于比硅衬底101和绝缘厚膜103之间的界面更低的穿通孔中，以及在穿通栓塞107的上表面和第一凸块111和绝缘厚膜103之间的接触面之间限定高度间隙113。此外，部分第一凸块111被嵌入穿通孔内部。第一凸块111在穿通孔外具有比穿通孔内的直径更大的直径，形成屋檐状投影形状。
凸块111的这种结构，连接到穿通孔内的穿通栓塞107以及在穿通孔外的直径比穿通孔内的直径更大，导致增强和稳固凸块111和穿通栓塞107之间的粘附力的锚定效应。此外，穿通栓塞107和第一凸块111之间的足够大的接触面积在其间提供足够的导电性和使接触电阻最小化。这种结构也提供制造工序的稳定性。此外。因为绝缘厚膜103的存在，可以有效地防止缺陷，如来自硅衬底101的表面上的凸块111的漏电流的出现，硅衬底101的表面上是第一凸块111侧边的表面。
此外，通过相对于Cu膜119适当地选择CMP条件可以获得高度间隙113。这些显著地简化制造工序，以及提供制造工序的稳定性。
此外，沿穿通栓塞107的侧周边在穿通栓塞107和硅衬底101之间形成的绝缘厚膜103比SiN膜105更厚。由此，有效地减小硅衬底101中产生的寄生电容。当绝缘厚膜103具有300nm以上的厚度时这种效果变得更突出。
此外，在CMP工序之后，仍然剩下用于保护硅衬底101的表面和支撑第一凸块111的绝缘厚膜103，以便与第一凸块111的较大直径部分接触。最初形成较厚的绝缘厚膜103，且即使在CMP工序之后也保持足够的厚度。因此，可以有效地保证第一凸块111和硅衬底101之间的绝缘。当绝缘厚膜103具有300nm以上的厚度时，这种效果变得更突出。
此外，如图3E所示，在形成穿通栓塞107之后和形成第一凸块111之前，获得一个结构，其中除穿通栓塞107的上表面之外硅衬底101的表面被绝缘，在硅衬底101的表面上不形成绝缘膜，或在对应于穿通栓塞107的上表面的位置处在绝缘膜上利用用于限定开口的光刻胶形成抗蚀剂图形。由此，获得可以简化第一凸块111的制造工序和可以减小相关制造成本的结构。
此外，在硅隔片中，由于覆盖穿通栓塞107侧壁而形成的绝缘厚膜103是充分绝缘的厚膜，因此第二凸块115不超过沿穿通栓塞107的侧周边设置的绝缘厚膜103的宽度。由此，可以有效地保证硅衬底101的后表面和第二凸块115之间的绝缘，在硅衬底101的后表面上不附加地设置用于其间绝缘的绝缘膜。因此，获得可以缩短用于形成第二凸块115的制造工序的结构。
此外，在硅隔片100中，如图2B所示，连续地和整体地形成设置在硅衬底101的表面上的绝缘厚膜103和覆盖穿通孔侧壁的绝缘厚膜103。因此，利用简单的工序可以获得该结构。在分开地形成这些绝缘厚膜103的情况下，厚膜可以在硅衬底101的表面和穿通孔的侧壁之间的边界区附近分开。但是，形成两个绝缘厚膜103作为连续的和整体的薄膜允许防止这种分开，且因此增强制造工序过程中的稳定性。
如上所述，硅隔片100包括硅衬底101的表面上以及穿通孔的侧壁上的绝缘厚膜103。由此，不必形成用于使硅衬底101与第一凸块111和第二凸块115绝缘的绝缘膜。因此，该结构没有用于形成绝缘膜的附加工序以及具有制造结构的简单性。此外。高度间隙113的存在增强穿通栓塞107和第一凸块111之间的粘附力。由此增加穿通电极的性能。
现在，将进一步描述图1所示的硅隔片100中设置的穿通电极102的结构，与上述H.Yonemura等中公开的半导体器件中的常规穿通电极形成对比。图6A和6B示出了穿通电极的结构的示意性剖面图。图6A示出了根据该实施例的穿通电极的结构，而图6B示出了常规穿通电极的结构。
参考图6B，在常规穿通电极中穿通栓塞207的上表面与衬底的上表面(图6B中的虚线)对准，它是穿通栓塞207和第一凸块211相互接触的表面。另一方面，参考图6A，在根据该实施例的穿通电极中，穿通栓塞107的上表面位于比硅衬底101和绝缘厚膜103之间的界面更低的位置，绝缘厚膜103用作用于硅衬底101的保护膜(图6A中的虚线)以及高度间隙113被限定。此外，部分第一凸块111被嵌入穿通栓塞107上的凹陷部分，由此与穿通栓塞107接触。由于第一凸块111与厚膜的上表面和穿通栓塞107的上表面接触，因此第一凸块111和穿通栓塞107互相紧密地粘附，由此与图6B中所示结构相比更保证其间的电气接触。
此外，图6A的结构包括沿穿通栓塞107的侧周边的厚膜，图6B的结构不具有厚膜。因此，与常规穿通电极相比根据该实施例的穿通电极可以更有效地减小寄生电容。
此外，参考图6B，在凸块211具有比穿通栓塞207更大直径的情况下，在衬底和凸块211之间形成绝缘层变为必需的附加工序。由此，通过比图6B的结构所需要的工序数目更少的工序可以制造图6A的结构。因此，根据该实施例的穿通电极的结构允许简化制造工序且因此减小相关制造成本。此外，尽管图6A和6B中未示出，但是与常规穿通电极的情况相比，也可以通过更少的工序数目形成根据该实施例的穿通电极的第二凸块115。
尽管参考附图基于实施例描述了本发明，但是应当理解上述仅仅是本发明的一个例子，本发明可以采用各种其他结构。
例如，相对于硅衬底101的表面垂直地形成根据图1的硅隔片100中的高度间隙113，而高度间隙113的形状未被具体地决定，而是可以另外设计，包括从硅衬底101的内部到硅衬底101的外部扩充的形状。此外，尽管平行于根据图1的硅衬底101的表面取向穿通栓塞107的再处理表面。但是穿通栓塞107的再处理表面可以是凹形的曲面。例如，通过.表面凹陷效果可以获得这种形状，以在穿通栓塞107的上表面上形成凹形的凹陷。
此外，底部凸块金属膜109可以由除TiW以外的难熔金属如Ti、Ta构成。例如，例举了Ti、TiN、WN、Ta、TaN等。此外，也可以采用包括TaN和Ta层的含Ta的阻挡金属。阻挡金属膜可以由溅射、CVD等形成。
此外，尽管在图6A中，描述了圆柱形穿通电极102作为例子，但是根据该实施例的穿通电极102的形状不局限于圆柱体，而是可以是其它形状，只要该形状允许形成高度间隙113，如上表面与下表面具有基本相同面积的椭圆柱或矩形柱。另外，穿通电极102可以是不具有尖顶部的截锥体、平截椭圆柱或斜截棱锥。柱体形状可以包括在一个方向延伸的条状。
此外，尽管上述描述表示其中在硅隔片100中形成穿通电极102的结构作为例子，但是穿通电极102可以应用于除硅隔片100以外的各种其他半导体芯片衬底。
(例子)
作为例子，根据参考图2A至2C，3D至3F，4G至4H和5I描述的工序制造图1所示的硅隔片100。这里，形成300nm厚度的SiO2膜作为绝缘厚膜103。SiN薄膜105形成有50nm的厚度。穿通栓塞107由Cu膜形成。此外，通过研磨硅衬底101的后表面硅衬底101被减薄至200μm。获得的包括穿通电极102的硅隔片100具有制造工序的高度稳定性和优异的成品率。
(比较例子)
作为比较例子，通过常规工序制造包括穿通电极的硅隔片。图8示出了比较例子中制造的硅隔片结构的示意性剖面图。此外，图9A至9C，10D至10F和11G至11H是用于说明图8所示的硅隔片200的制造工序的示意性剖面图。在下面，将描述根据比较例子的硅隔片的制造工序，关注与上述例子的差异。
首先，通过光刻技术在硅衬底201的表面形成抗蚀剂图形，以及在硅衬底201上利用抗蚀剂图形作为掩模执行刻蚀，由此形成开口(附图中未示出)。然后除去抗蚀剂图形，以及在其上设置了开口的硅衬底201的表面上到处都依次形成绝缘膜203和SiN膜205。形成10nm厚度的SiO2膜作为绝缘膜203。还形成10nm厚度的SiN膜205。
此后，形成填充开口的Cu膜219(图9A)。然后用CMP除去硅衬底201上的Cu膜219、SiN膜205和绝缘膜203。在此阶段，调整CMP条件，以便硅衬底201的表面被曝光和对准穿通栓塞207的表面(图9B)。
在硅衬底201的表面上形成300nm厚度的绝缘膜204作为覆盖膜。然后，在绝缘膜204上形成抗蚀剂图形，以及在位于穿通栓塞207上的绝缘膜204上有选择地执行刻蚀，由此形成开口231(图9C)。
然后通过参考图3F至5I描述的工序形成连接到穿通栓塞207的第一凸块211，第一凸块211的侧边上的表面通过粘合剂(附图中未示出)和剥落层(附图中未示出)被固定到支撑元件225(图10D)。
上述工序之后，硅衬底201的后表面被研磨，以便曝光穿通栓塞207的下表面。然后执行后表面上的硅深刻蚀，由此形成Cu柱210(图10E)，接着在后表面到处都形成绝缘膜206作为覆盖膜。至于绝缘膜206，形成100nm厚度的SiN膜(图10F)。此后，执行CMP，以有选择地除去穿通栓塞207的后表面上的绝缘膜206，由此曝光穿通栓塞207(图11G)。类似于该例子，执行非电解镀，以在穿通栓塞207的曝光表面上生长Ni膜，由此围绕穿通栓塞207形成第二凸块215(图11H)。然后在Ni膜的表面上形成Au镀膜，此后除去支撑元件225，以及最后获得图8所示的硅隔片200。
由于与例子不同，比较例子不包括绝缘厚膜103，因此根据比较例子的硅隔片200需要形成绝缘膜204和用于使穿通栓塞207与第一凸块211和第二凸块215绝缘的绝缘膜206的附加工序，在绝缘膜204上执行选择性蚀刻和有选择地除去绝缘膜206导致制造的工序数目增加。
很显然本发明不局限于上述实施例，在不脱离发明的范围和精神的条件下可以进行改进和改变。

Claims (13)

1.一种穿通电极，包括：
设有穿通孔的硅衬底；
在所述硅衬底表面上形成的绝缘保护膜，具有与所述穿通孔连接的开口；
通过将导电材料嵌入所述穿通孔中形成的穿通栓塞；以及
连接到所述穿通栓塞的凸块；
其中所述凸块连接到所述穿通孔内的所述穿通栓塞，以及位于所述穿通孔外的部分所述凸块具有比位于所述穿通孔内的部分所述凸块更大的直径。
2.根据权利要求1的穿通电极，其中所述凸块的较大直径部分与所述绝缘保护膜接触。
3.根据权利要求1的穿通电极，还包括覆盖所述穿通栓塞侧壁而形成的侧壁绝缘膜。
4.根据权利要求3的穿通电极，其中连续地和整体地形成所述侧壁绝缘膜和所述绝缘保护膜。
5.根据权利要求1的穿通电极，其中所述穿通栓塞包括覆盖所述穿通孔内的侧壁的阻挡膜，以及被所述阻挡膜围绕覆盖的金属膜。
6.一种硅隔片，包括设有根据权利要求1的所述穿通电极的硅衬底。
7.一种制造穿通电极的方法，包括：
在硅衬底的一个表面上形成孔；
形成覆盖所述所述表面和所述孔的内壁的绝缘膜；
形成填充所述孔的导电薄膜；
在所述导电薄膜上执行抛光或深刻蚀，以便除去用于曝光所述绝缘膜的所述孔外形成的部分所述导电薄膜，以及再处理所述导电薄膜的表面到比所述硅衬底的表面更靠内的高度，用于形成导电栓塞和凹陷部分；
在所述导电栓塞的再处理表面上生长金属膜，以由此填充所述凹陷部分和进一步形成凸块，凸块在所述孔外具有比位于所述孔内的部分所述凸块更大的直径；以及
抛光用于曝光所述导电栓塞的所述硅衬底的另一表面，由此形成穿通电极。
8.根据权利要求7的方法，其中所述形成所述凸块包括在所述导电栓塞的表面上和所述凹陷部分的侧壁上形成阻挡金属膜，以及利用所述阻挡金属膜作为基体生长所述金属膜。
9.根据权利要求7的方法，包括，在形成所述导电栓塞的所述步骤之后：
从与所述一个表面相对的其所述另一表面有选择地除去部分所述的硅衬底，以由此曝光所述导电栓塞的表面；以及
在所述导电栓塞的曝光表面上生长其它金属膜，由此在后表面上形成凸块。
10.根据权利要求7的方法，包括，在所述形成所述穿通电极之后：
在所述导电栓塞的曝光表面上生长其它金属膜，以由此在后表面上形成凸块。
11.根据权利要求7的方法，其中所述形成所述绝缘膜包括在所述硅衬底的所述一个表面上形成硅氧化物膜。
12.根据权利要求7的方法，包括，在所述形成所述绝缘膜之后和在所述形成所述导电薄膜之前，在设有所述孔的所述硅衬底的所述一个表面上形成阻挡膜。
13.一种制造硅隔片的方法，包括通过根据权利要求7的所述方法形成穿通电极。
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