CN104285280A - 横越多个导电柱的平坦化的半导体构造和方法 - Google Patents

横越多个导电柱的平坦化的半导体构造和方法 Download PDF

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CN104285280A
CN104285280A CN201380013561.9A CN201380013561A CN104285280A CN 104285280 A CN104285280 A CN 104285280A CN 201380013561 A CN201380013561 A CN 201380013561A CN 104285280 A CN104285280 A CN 104285280A
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post
lining
sidewall surfaces
planarized
packing material
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CN104285280B (zh
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杰斯皮德·S·甘德席
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Micron Technology Inc
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Micron Technology Inc
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Abstract

一些实施例包含一种平坦化方法。横越半导体衬底且沿着从所述衬底向上延伸的柱而形成衬层。在所述衬层上和所述柱之间形成有机填充材料。形成横越所述柱和横越所述衬层和所述填充材料中的一或两者而延伸的平坦化表面。一些实施例包含一种半导体构造，其含有半导体裸片。导电柱延伸穿过所述裸片。所述柱具有位于所述裸片的背侧表面上方的上表面，且具有在所述背侧表面与所述上表面之间延伸的侧壁表面。衬层横越所述裸片的所述背侧表面且沿着所述柱的所述侧壁表面。导电盖位于所述柱的所述上表面上，且具有沿着与所述柱的所述侧壁表面邻近的所述衬层的边缘。

Description

横越多个导电柱的平坦化的半导体构造和方法
技术领域
本发明涉及横越多个导电柱的平坦化的半导体结构和方法。
背景技术
集成电路装置(例如存储器裸片)的商业生产可涉及在单半导体晶片或其它主体半导体衬底上制造大量相同电路图案。半导体制造者不断追求的目标为增大在给定尺寸的半导体衬底上制造的半导体装置的密度以实现半导体装置的产率提高和其性能增强。
用于增大半导体组合件中的半导体装置的密度的一种方法为产生完全地延伸穿过半导体裸片且具体来说从所述裸片的作用表面延伸到所述裸片的相对背侧表面的通孔(即，穿通孔)。所述通孔可填充有导电材料以形成提供从所述裸片的作用表面到所述裸片的背侧表面的电性路径的穿过衬底的互连件。所述穿过衬底的互连件可电性耦合到沿着所述裸片的背侧且延伸到所述裸片外部的电路组件的电性接触件。在一些应用中，可将所述裸片并入到一个三维多芯片模块(3-D MCM)中，且所述裸片外部的电路组件可由另一半导体裸片和/或载体衬底组成。
已揭示用于形成半导体衬底中的穿过衬底的互连件的各种方法。例如，美国专利第7,855,140号、第7,626,269号和第6,943,106号描述可用于形成穿过衬底的互连件的实例性方法。
在穿过衬底的互连件的制造期间，会遇到各种问题。例如，穿过衬底的互连件的导电柱可在处理阶段于半导体裸片的背侧表面上方延伸，且可期望平坦化所述柱以形成横越所述柱和裸片而延伸的平坦化表面。然而，所述柱内的铜可能在平坦化期间形成胶渣；和/或所述柱可能在平坦化期间倾斜或断裂。可期望开发形成穿过衬底的互连件的新方法，其缓解、防止和/或克服常规处理中遇到的问题。可进一步期望开发新的穿过衬底的互连架构。
附图说明
图1到7是实例性实施例方法的各种处理阶段处的构造的一部分的图解横截面图。
图1A是图1的构造的俯视图；其中图1的视图沿着图1A的线1-1。
图7A是图7的构造的俯视图；其中图7的视图沿着图7A的线7-7。
图8到12是实例性实施例方法的各种处理阶段处的构造的一部分的图解横截面图。
图12A是图12的构造的俯视图；其中图12的视图沿着图12A的线12-12。
图13到15是实例性实施例方法的各种处理阶段处的构造的一部分的图解横截面图。
图13A是图13的构造的俯视图；其中图13的视图沿着图13A的线13-13。
具体实施方式
在一些实施例中，本发明包含用于形成横越多个导电柱的平坦化表面的方法。所述柱可对应于穿过衬底的互连件，且在一些实施例中可包括铜。
参考图1到15而描述实例性实施例。
参考图1和1A，图中展示包括延伸到半导体基底12中的多个导电柱20到22的半导体构造10。在一些实施例中，基底12可对应于半导体裸片。所述裸片具有背侧14和前侧16。集成电路(图中未展示)可与前侧相关联，且提供虚线17以图解地说明所述裸片内的电路的大致边界。所述集成电路可包括存储器(例如NAND、DRAM等等)、逻辑等等。虽然所述集成电路可主要与前侧相关联，但在一些实施例中也可存在与背侧相关联的集成电路。
背侧具有表面15。柱20到22具有位于背侧表面15上方的顶表面和从所述顶表面延伸到背侧表面15的侧壁表面。例如，图中展示包括顶表面25和包括从顶表面25延伸到基底12的背侧表面15的侧壁表面23的导电柱20。
基底也将具有前侧表面，且在一些实施例中，柱20到22可完全穿过裸片，使得所述柱具有沿着裸片的前侧表面的表面。图1中未说明所述前侧表面。裸片的所述前侧表面可在图1和1A的处理阶段处接合到载体晶片(图中未展示)以有助于运输裸片通过处理设备。
基底12可包括单晶硅，且可被称为半导体衬底或半导体衬底的一部分。术语“半导电衬底”、“半导体构造”和“半导体衬底”意指包括半导电材料(其包含(但不限于)主体半导电材料)的任何构造，例如半导电晶片(单独地或位于包括其它材料的组合件中)和半导电材料层(单独地或位于包括其它材料的组合件中)。术语“衬底”意指任何支撑结构，其包含(但不限于)上述半导电衬底。
导电柱20到22可包括任何适合导电组合物或组合物的组合。在一些实施例中，所述柱可包括形成于穿衬底通孔(TSV)内的一或多个导电组合物。在一些实施例中，所述柱可包括铜。
在图1和1A的所展示实施例中，形成在基底12的背侧表面15上方具有变动距离的柱。暴露柱尺寸的所述不均匀性可例如源自于用于制造柱的处理和/或发生在柱的表面的研磨期间或之后的总厚度变动(TTV)。在一些实施例中，暴露柱尺寸的变动可大于1微米、大于10微米等等。
参考图2，形成横越表面15且沿着柱20到22的侧壁和顶表面的衬层26。衬层26可包括任何适合组合物或组合物的组合。虽然图中展示的衬层为单一同质组合物，但在一些实施例中，衬层可包括两个或两个以上离散材料。例如，衬层可包括氮化硅上的二氧化硅。在一些实施例中，衬层26由无机材料组成。在一些实施例中，衬层包括铜障壁材料，例如包括钌或氧化钌、基本上由钌或氧化钌组成或由钌或氧化钌组成的材料。所述铜障壁材料可与包括铜的柱一起使用，且可缓解或防止原本可从含铜的柱发生的铜扩散。可单独地或与二氧化硅和氮化硅中的一或两者组合地利用含钌材料。相应地，在一些实例性实施例中，衬层26包括二氧化硅、氮化硅和钌中的一或多者、基本上由二氧化硅、氮化硅和钌中的一或多者组成或由二氧化硅、氮化硅和钌中的一或多者组成。
可通过例如包含原子层沉积(ALD)、化学气相沉积(CVD)和物理气相沉积(PVD)的任何适合方法而形成衬层26。
形成具有任何适合厚度的衬层，且将在一些实施例中形成具有小于或等于500纳米的厚度的衬层。
在一些实施例中，可期望在低温处(即，在小于或等于约200℃的温度处)形成衬层26以避免负面影响与基底12相关联的电路。在所述实施例中，衬层可包括在小于或等于约200℃的温度处沉积的氮化硅、基本上由在小于或等于约200℃的温度处沉积的氮化硅组成或由在小于或等于约200℃的温度处沉积的氮化硅组成。
参考图3，填充材料28形成于衬层26上和柱20到22之间。在所展示实施例中，填充材料提供于柱之间的区域内，但未提供于柱的上方。在其它实施例(例如图8所展示的实施例)中，可提供达到至少覆盖柱的若干者的厚度的填充材料。
填充材料可包括任何适合组合物或组合物的组合，且在一些实施例中可包括一或多个有机(即，含碳)组合物。例如，在一些实施例中，填充材料28可包括光致抗蚀剂、基本上由光致抗蚀剂组成或由光致抗蚀剂组成。
可提供达到任何适合厚度的填充材料。在一些实施例中，可提供达到从约500纳米到约4微米范围内的厚度的填充材料。在一些实施例中，填充材料和衬层的组合厚度可在从约500纳米到约5微米的范围内。
参考图4，构造10经受平坦化以形成平坦化表面29。可利用例如(例如)化学机械抛光(CMP)等任何适合方法来完成所述平坦化。在所展示实施例中，所述平坦化移除填充材料28(图3)，且形成横越衬层26和柱20到22而延伸的平坦化表面29。在其它实施例(例如(例如)以下参考图9而描述的实施例)中，平坦化表面可延伸横越填充材料和柱。
参考图5，横越平坦化表面29形成导电材料30，且于所述导电材料上形成图案化掩蔽材料31。在一些实施例中，所述导电材料可包括铜，且可用作用于铜的随后电解生长的晶种材料(例如，材料30可包括钛和铜的混合物、基本上由钛和铜的混合物组成或由钛和铜的混合物组成)。在一些实施例中，图案化掩蔽材料31可包括经光刻图案化的光致抗蚀剂。
图案化掩蔽材料具有于其内延伸穿过以分别暴露柱20至22上方的区域的开口32至34。
参考图6，导电材料36和38形成于开口32到34内。在一些实施例中，材料36可包括生长于导电材料30上的铜、基本上由生长于导电材料30上的铜组成或由生长于导电材料30上的铜组成；且材料38包括镍或钯。虽然在所展示实施例中两个材料36和38形成于开口32到34内，但在其它实施例中单一导电材料可形成于所述开口内或两个以上材料可形成于所述开口内。例如，在一些实施例中，镍和钯两者可形成于含铜材料36上。材料36和38可最终并入到凸块下金属(UBM)中，且因此，在一些实施例中，材料36和38可包括适合于用在UBM中的常规组合物。
材料36和38一起形成分别位于开口32到34内的堆叠40到42。在所展示实施例中，掩蔽材料31的介入区域使所述堆叠彼此间隔开。
参考图7和7A，移除掩蔽材料31(图6)，且随后，在材料30的蚀刻期间将堆叠40到42用作为硬掩模。图7和7A的构造可被视为包括多个导电盖44到46，其包括与堆叠40到42的材料36和38组合的材料30。盖44到46与柱20到22一一对应，且可最终对应于用于将焊料球或其它布线组件(图中未展示)与柱电性耦合的UBM。
盖44到46可具有任何适合形状，且图7A展示其中盖呈圆形的实施例。
参考图8到12而描述用于形成横越多个导电柱延伸的平坦化表面的另一实例性实施例方法。
参考图8，图中展示类似于以上参考图3而描述的处理阶段的处理阶段处的构造10a。图8的构造与图3的构造的略微不同点在于：图中展示填充材料28覆盖柱21。提供所述差异以说明：在各种实施例中，填充材料28的深度可变动。在一些实施例中，可提供达到与图3的处理阶段处所说明深度相同的图8的处理阶段处的深度的填充材料28，或反之亦然。
参考图9，形成横越构造10a的平坦化表面49。可利用例如CMP来形成所述平坦化表面。所述平坦化表面延伸横越柱20到22和填充材料28。在所展示实施例中，所述平坦化表面也延伸横越与柱20到22的侧壁邻近的衬层26的部分。
参考图10，相对于衬层26和柱20到22而选择性移除填充材料28(图9)。在一些实施例中，填充材料包括有机组合物(例如光致抗蚀剂)，且利用氧化条件(例如以等离子存在的O2)来相对于衬层26和柱20到22的无机组合物而选择性移除填充材料。柱20到22的顶部区域包括平坦化表面49。
参考图11，形成横越衬层26和柱20到22的导电材料30，图案化掩蔽材料31形成于材料30上，且导电材料36和38形成于延伸穿过掩蔽材料31的开口32到34内。
参考图12和12A，图中展示类似于图7和7A的处理阶段的处理阶段处的构造10a。已移除掩蔽材料31(图11)，且将材料30、36和38并入到多个导电盖44a到46a中。在一些实施例中，形成直接紧贴衬层26和柱的上表面的材料30(如图所展示)，且材料36对应于电解地生长于材料30上的含铜材料。
在图12和12A的所展示实施例中，柱20到22具有对应于平坦化表面49的平坦化上表面，且具有从所述平坦化上表面延伸到基底12的背侧表面15的侧壁表面。例如，柱20具有所说明的侧壁表面23。在所展示实施例中，导电材料30直接紧贴柱的上表面，且因此，盖44a到46a直接紧贴柱的平坦化上表面。盖44a到46a具有沿着柱的侧壁表面向下延伸的区域。例如，图中展示具有沿着柱20的侧壁表面23延伸的区域50的盖44a。沿着侧壁的盖的区域可被称为“边缘”，且在所展示实施例中，衬层26将所述区域与柱的侧壁表面分离。
盖44a到46a可具有任何适合形状，且图12A展示其中盖呈圆形的实施例。
参考图13到15而描述用于形成横越多个导电柱延伸的平坦化表面的另一实例性实施例方法。
参考图13和13A，图中展示图10的处理阶段后的处理阶段处的构造10b。图案化电性绝缘材料60形成于衬层26上。所述图案化电性绝缘材料包括薄区域63和厚区域65。所述薄区域可被视为界定围绕柱的平坦化上表面49延伸的插入区域62。
材料60可包括任何适合组合物或组合物的组合，且可例如包括聚酰亚胺、基本上由聚酰亚胺组成或由聚酰亚胺组成。在一些实施例中，衬层26包括通过低温工艺形成的氮化硅。所述氮化硅可具有于其内延伸或延伸穿过其的针孔。在所述实施例中，材料60可用于闭塞所述针孔，使得随后形成的盖(具体来说，以下参考图15而描述的盖44b到46b)的导电材料不直接接触基底12的半导体材料。
可利用任何适合方法来图案化材料60。在一些实施例中，可利用产生光致抗蚀剂掩模(图中未展示)内的阶梯式区域的光刻工艺来在大片材料60上形成所述掩模(例如，“泄漏”标线可用于图案化所述掩模)，且接着，可用一或多个适当蚀刻来将图案从所述光致抗蚀剂掩模转移到材料60。这可在材料60内形成阶梯式区域，其中所述阶梯式区域的薄部分对应于区域63且所述阶梯式区域的厚部分对应于区域65。接着，可移除所述光致抗蚀剂掩模以留下图13和13A的构造。
透过材料60而暴露柱20到22的上表面。在一些实施例中，可在形成大片材料60之后且在形成材料60内的阶梯式区域之前进行蚀刻和/或平坦化以暴露柱20到22的上表面。
参考图14，图中展示类似于图11的处理阶段的处理阶段处的构造10b。形成横越材料60和柱20到22的导电材料30，图案化掩蔽材料31形成于材料30上，且导电材料36和38形成于延伸穿过掩蔽材料31的开口32到34内。
参考图15和15A，图中展示类似于图12和12A的处理阶段的处理阶段处的构造10b。已移除掩蔽材料31(图14)，且将材料30、36和38并入到多个导电盖44b到46b中。所述盖具有沿着柱20的侧壁表面延伸的边缘(例如，盖44b的边缘50沿着柱20的侧壁表面23延伸)；其中在所展示实施例中，衬层26使所述边缘与柱的侧壁表面分离。
本文中所描述的实施例的若干者可有利地避免与横越穿过衬底的互连件(例如类似于图1到15的柱20到22的互连件)的铜和硅(例如类似于图1到15的基底12的含硅裸片)两者的平坦化相关联的现有技术问题。具体来说，与包括衬层26(图4的实施例)和/或填充材料28(图9的实施例)的暴露表面同时地平坦化柱20到22。因此，如果柱20到22包括在平坦化期间形成胶渣的铜或另一材料，则形成胶渣的导电材料将不会直接紧贴基底12的半导体材料，而是会改为沿着衬层26和/或填充材料28。随后，可在下伏材料的移除期间移除形成胶渣的导电材料(例如，在图9和10的实施例中，可在填充材料的移除期间除去横越填充材料28形成胶渣的任何导电材料)，或如果不会负面影响所得构造的性能，则可使形成胶渣的导电材料留在下伏绝缘材料上。
在一些实施例中，本文中所描述的处理的优点可包含：缓解或防止柱研磨铜形成胶渣；缓解或防止与硅干式蚀刻化学处理相关联的问题(例如硫化物形成、非均匀蚀刻速率等等)；能够在无需研磨成用于穿过衬底的互连件的柱的情况下控制过量柱研磨总厚度变动；和/或利用高精确度步进器来消除处理步骤。
在一些实施例中，衬层26和/或填充材料28可给柱20到22提供支撑以缓解或防止可发生在现有技术工艺(其中无法在横越类似柱的平坦化期间充分支撑所述柱)中的倾斜、弯曲、断裂等等。
在一些实施例中，可将本文中所描述的构造并入到混合式存储器立方(HMC)架构中，例如(例如)包括堆叠于逻辑电路上的DRAM电路的架构。
图式中的各种实施例的特定定向仅供说明性目的，且在一些应用中，可相对于所展示定向而旋转实施例。本文中所提供的描述和所附权利要求书针对具有各种特征之间的所描述关系的任何结构，不管所述结构是否沿图式的特定定向或相对于此定向旋转。
随附说明的横截面图仅展示横截面的平面内的特征，且不展示横截面的平面后方的材料以简化图式。
当结构在上文中被称为“在另一结构上”或“紧贴另一结构”时，其可直接位于所述另一结构上或也可存在介入结构。相比来说，当结构被称为“直接在另一结构上”或“直接紧贴另一结构”时，不存在介入结构。当结构被称为“连接”或“耦合”到另一结构时，其可直接连接或耦合到所述另一结构，或可存在介入结构。相比来说，当结构被称为“直接连接”或“直接耦合”到另一结构时，不存在介入结构。
一些实施例包含横越延伸到半导体衬底中的多个导电柱的平坦化的方法。形成横越衬底表面且沿着所述柱的侧壁表面和顶表面的衬层。填充材料形成于所述衬层上和所述柱之间。所述填充材料包括一或多个有机组合物。平坦化表面经形成以延伸横越所述柱和横越所述衬层和所述填充材料中的一或两者。
一些实施例包含平坦化延伸到半导体衬底中的多个导电柱的方法。形成横越衬底表面且沿着所述柱的侧壁表面和顶表面的衬层。所述衬层包括一或多个无机组合物。填充材料形成于所述衬层上和所述柱之间。所述填充材料包括一或多个有机组合物。平坦化表面经形成以延伸横越所述填充材料和所述柱。在形成所述平坦化表面之后，使用蚀刻来从所述柱之间移除所述填充材料，同时留下沿着所述柱的侧壁表面且横越所述柱之间的衬底表面的所述衬层。用于移除所述填充材料的蚀刻可例如包括适合的湿式化学处理或适合的干式化学处理，且在一些实施例中可利用氧化剂。
一些实施例包含平坦化延伸到半导体衬底中的多个导电柱的方法。衬层形成于衬底表面上且沿着所述柱的侧壁表面和顶表面。填充材料形成于所述衬层上和所述柱之间。平坦化表面经形成以延伸横越所述柱和所述衬层。导电材料形成于所述平坦化表面上。导电盖形成于所述导电材料上。所述导电盖的形成包括：在所述导电材料上形成图案化掩模；在所述导电材料上的延伸穿过所述图案化掩模的开口内生长含铜层；在所述图案化掩模中的所述开口内的所述含铜层上形成镍和钯中的一或两者(所述含铜层与镍和钯的所述一或两者一起形成所述导电材料上的间隔开的堆叠)；移除所述图案化掩模；和从所述堆叠之间的空间移除所述导电材料。
一些实施例包含半导体构造。所述构造具有延伸穿过半导体裸片的导电柱。所述柱具有位于所述裸片的背侧表面上方的上表面，且具有在所述裸片的所述背侧表面与所述上表面之间延伸的侧壁表面。衬层沿着所述柱的所述侧壁表面。导电盖直接紧贴所述柱的上表面，且具有沿着所述柱的侧壁表面且通过所述衬层而与所述侧壁表面间隔的边缘。

Claims (34)

1.一种平坦化延伸到半导体衬底中的多个导电柱的方法，所述方法包括：
形成横越衬底表面且沿着所述柱的侧壁表面和顶表面的衬层；
在所述衬层上和所述柱之间形成填充材料，所述填充材料包括一或多个有机组合物；和
平坦化以形成延伸横越所述柱和横越所述衬层和所述填充材料中的一或两者的平坦化表面。
2.根据权利要求1所述的方法，其中所述填充材料包括光致抗蚀剂。
3.根据权利要求1所述的方法，其中所述衬底包括半导体裸片；其中所述表面是所述裸片的背侧表面；且其中所述导电柱完全地延伸穿过所述裸片。
4.根据权利要求1所述的方法，其中所述平坦化形成延伸横越所述衬层和所述柱的所述平坦化表面；所述方法进一步包括形成直接紧贴所述柱的所述平坦化表面且与所述柱一一对应的导电盖。
5.根据权利要求1所述的方法，其中所述平坦化形成延伸横越所述填充材料和所述柱的所述平坦化表面；所述方法进一步包括：在形成所述平坦化表面之后，从所述柱之间移除所述填充材料，同时留下沿着所述柱的侧壁表面且横越所述柱之间的所述衬底表面的所述衬层。
6.根据权利要求5所述的方法，其中所述填充材料的所述移除包括湿式或干式化学处理。
7.根据权利要求5所述的方法，其进一步包括形成直接紧贴所述柱的平坦化上表面且沿着所述柱的所述侧壁表面的导电盖；沿着所述柱的所述侧壁表面的所述导电盖的区域通过所述衬层而与所述侧壁表面间隔开。
8.根据权利要求5所述的方法，其进一步包括：
在所述平坦化之后，形成横越所述衬层的图案化电性绝缘材料；所述图案化电性绝缘材料界定围绕所述柱的平坦化上表面的插入区域；和
形成位于所述插入区域内且直接紧贴所述柱的所述平坦化上表面且沿着所述柱的所述侧壁表面的导电盖；沿着所述柱的所述侧壁表面的所述导电盖的区域通过所述衬层而与所述侧壁表面间隔开。
9.根据权利要求8所述的方法，其中所述图案化电性绝缘材料包括聚酰亚胺。
10.根据权利要求8所述的方法，其中所述衬层包括具有在其内延伸的一或多个针孔的氮化硅；且其中所述图案化电性绝缘材料填充所述一或多个针孔。
11.根据权利要求1所述的方法，其中所述导电柱包括铜。
12.根据权利要求11所述的方法，其中所述衬层包括氮化硅。
13.根据权利要求11所述的方法，其中所述衬层包括钌。
14.一种平坦化延伸到半导体衬底中的多个导电柱的方法，所述方法包括：
形成位于衬底表面上且沿着所述柱的侧壁表面和顶表面的衬层；所述衬层包括一或多个无机组合物；
在所述衬层上和所述柱之间形成填充材料；所述填充材料包括一或多个有机组合物；
平坦化以形成延伸横越所述填充材料和所述柱的平坦化表面；和
在所述平坦化之后，从所述柱之间移除所述填充材料，同时留下沿着所述柱的侧壁表面且横越所述柱之间的所述衬底表面的所述衬层。
15.根据权利要求14所述的方法，其中所述衬底包括半导体裸片；其中所述表面是所述裸片的背侧表面；且其中所述导电柱是完全地延伸穿过所述裸片的含铜柱。
16.根据权利要求14所述的方法，其进一步包括：
形成直接紧贴所述柱的平坦化上表面且直接紧贴沿着所述柱的所述侧壁表面的所述衬层的导电材料；和
在所述导电材料上生长铜以在所述柱的所述平坦化上表面上形成导电盖。
17.根据权利要求14所述的方法，其进一步包括：
在所述平坦化之后，形成横越所述衬层的图案化电性绝缘材料；所述图案化电性绝缘材料界定围绕所述柱的平坦化上表面的插入区域；
形成直接紧贴所述柱的平坦化上表面且直接紧贴沿着所述柱的所述侧壁表面的所述衬层的导电材料；和
在所述导电材料上生长铜以在所述柱的所述平坦化上表面上形成导电盖。
18.一种横越延伸到半导体衬底中的多个导电柱的平坦化方法，所述方法包括：
形成横越衬底表面且沿着所述柱的侧壁表面和顶表面的衬层；
在所述衬层上和所述柱之间形成填充材料；
平坦化以形成延伸横越所述柱和所述衬层的平坦化表面；
在所述平坦化表面上形成导电材料；和
在所述导电材料上形成导电盖；所述导电盖的所述形成包括：
在所述导电材料上形成图案化掩模；
在所述导电材料上在延伸穿过所述图案化掩模的开口内生长含铜层；
在所述图案化掩模中的所述开口内的所述含铜层上形成镍和钯中的一或两者；所述含铜层与镍和钯中的所述一或两者一起形成所述导电材料上的间隔开的堆叠；
移除所述图案化掩模；和
从所述堆叠之间的空间移除所述导电材料。
19.根据权利要求18所述的方法，其中所述衬层包括氮化硅。
20.根据权利要求18所述的方法，其中所述衬层包括钌。
21.根据权利要求18所述的方法，其中所述衬层仅由一种同质物质组成。
22.根据权利要求18所述的方法，其中所述衬层包括两个或两个以上物质。
23.根据权利要求22所述的方法，其中所述衬底包括氮化硅上的二氧化硅。
24.根据权利要求18所述的方法，其中所述填充材料包括碳。
25.根据权利要求18所述的方法，其中所述填充材料包括光致抗蚀剂。
26.一种半导体构造，其包括：
导电柱，其延伸穿过半导体裸片；所述柱具有位于所述裸片的背侧表面上方的上表面，且具有在所述裸片的所述背侧表面与所述上表面之间延伸的侧壁表面；
衬层，其沿着所述柱的所述侧壁表面；和
导电盖，其直接紧贴所述柱的所述上表面；所述盖具有沿着所述柱的侧壁表面且通过所述衬层而与所述侧壁表面间隔的边缘。
27.根据权利要求26所述的构造，其进一步包括界定围绕所述柱的所述上表面的插入区域的图案化电性绝缘材料；且其中所述盖的所述边缘延伸到所述插入区域中。
28.根据权利要求27所述的构造，其中所述图案化电性绝缘材料包括聚酰亚胺。
29.根据权利要求26所述的构造，其中所述衬层仅由一种同质物质组成。
30.根据权利要求29所述的构造，其中所述衬层由氮化硅组成。
31.根据权利要求29所述的构造，其中所述衬层包括钌。
32.根据权利要求31所述的构造，其中所述导电柱包括铜。
33.根据权利要求26所述的构造，其中所述衬层包括两个或两个以上物质。
34.根据权利要求26所述的构造，其中所述导电盖包括镍和钯中的一或两者。
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