TW201349427A - 橫越複數個電性導體柱之平坦化的半導體結構及方法 - Google Patents

橫越複數個電性導體柱之平坦化的半導體結構及方法 Download PDF

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TW201349427A
TW201349427A TW102108525A TW102108525A TW201349427A TW 201349427 A TW201349427 A TW 201349427A TW 102108525 A TW102108525 A TW 102108525A TW 102108525 A TW102108525 A TW 102108525A TW 201349427 A TW201349427 A TW 201349427A
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pillars
liner
electrically conductive
forming
along
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TW102108525A
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TWI514535B (zh
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Jaspreet S Gandhi
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Micron Technology Inc
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Abstract

一些實施例包含一種平坦化方法。橫越一半導體基板且沿著自該基板向上延伸之柱而形成一襯層。在該襯層上及該等柱之間形成有機填充材料。形成橫越該等柱及橫越該襯層及該填充材料之一或兩者而延伸之一平坦化表面。一些實施例包含一種半導體結構，其含有一半導體晶粒。電性導體柱延伸穿過該晶粒。該等柱具有位於該晶粒之一背側表面上方之上表面，且具有在該背側表面與該等上表面之間延伸之側壁表面。一襯層橫越該晶粒之該背側表面且沿著該等柱之該等側壁表面。電性導體蓋位於該等柱之該等上表面上，且具有沿著與該等柱之該等側壁表面鄰近之該襯層之邊緣。

Description

橫越複數個電性導體柱之平坦化的半導體結構及方法
本發明係關於橫越複數個電性導體柱之平坦化的半導體結構及方法。
積體電路裝置(諸如記憶體晶粒)之商業生產可涉及在一單一半導體晶圓或其他主體半導體基板上製造大量相同電路圖案。半導體製造者不斷追求之目標為增大在一給定尺寸之半導體基板上所製造之半導體裝置之密度以實現半導體裝置之產率提高及其效能增強。
用於增大一半導體總成中之半導體裝置之密度之一方法為產生完全地延伸穿過一半導體晶粒且具體言之自該晶粒之一主動表面延伸至該晶粒之一相對背側表面之介層孔(即，通孔)。該等介層孔可填充有電性導體材料以形成提供自該晶粒之主動表面至該晶粒之背側表面之電性路徑之穿過基板之互連件。該等穿過基板之互連件可電性耦合至沿著該晶粒之背側且延伸至該晶粒外部之電路組件之電性接觸件。在一些應用中，可將該晶粒併入至一個三維多晶片模組(3-D MCM)中，且該晶粒外部之該等電路組件可由另一半導體晶粒及/或一載體基板組成。
已揭示用於形成半導體基板中之穿過基板之互連件之各種方 法。例如，美國專利第7,855,140號、第7,626,269號及第6,943,106號描述可用於形成穿過基板之互連件之實例性方法。
在穿過基板之互連件之製造期間，會遇到各種問題。例如，穿過基板之互連件之電性導體柱可在一處理階段於一半導體晶粒之一背側表面上方延伸，且可期望平坦化此等柱以形成橫越該等柱及該晶粒而延伸之一平坦化表面。然而，該等柱內之銅會在平坦化期間被塗抹；及/或該等柱會在平坦化期間傾斜或斷裂。可期望開發形成穿過基板之互連件之新方法，其緩解、防止及/或克服習知處理中遇到之問題。可進一步期望開發新的穿過基板之互連架構。
10‧‧‧半導體結構
10a‧‧‧結構
10b‧‧‧結構
12‧‧‧半導體基底
14‧‧‧背側
15‧‧‧背側表面
16‧‧‧前側
17‧‧‧虛線
20‧‧‧電性導體柱
21‧‧‧電性導體柱
22‧‧‧電性導體柱
23‧‧‧側壁表面
25‧‧‧頂面
26‧‧‧襯層
28‧‧‧填充材料
29‧‧‧平坦化表面
30‧‧‧電性導體材料
31‧‧‧遮罩材料
32‧‧‧開口
33‧‧‧開口
34‧‧‧開口
36‧‧‧電性導體材料
38‧‧‧電性導體材料
40‧‧‧堆疊
41‧‧‧堆疊
42‧‧‧堆疊
44‧‧‧電性導體蓋
44a‧‧‧電性導體蓋
44b‧‧‧電性導體蓋
45‧‧‧電性導體蓋
45a‧‧‧電性導體蓋
45b‧‧‧電性導體蓋
46‧‧‧電性導體蓋
46a‧‧‧電性導體蓋
46b‧‧‧電性導體蓋
49‧‧‧平坦化表面
50‧‧‧邊緣
60‧‧‧電性絕緣材料
62‧‧‧插入區域
63‧‧‧薄區域
65‧‧‧厚區域
圖1至圖7係一實例性實施例方法之各種處理階段處之一結構之一部分之圖解橫截面圖。
圖1A係圖1之結構之一俯視圖；其中圖1之視圖沿著圖1A之線1-1。
圖7A係圖7之結構之一俯視圖；其中圖7之視圖沿著圖7A之線7-7。
圖8至12係一實例性實施例方法之各種處理階段處之一結構之一部分之圖解橫截面圖。
圖12A係圖12之結構之一俯視圖；其中圖12之視圖沿著圖12A之線12-12。
圖13至15係一實例性實施例方法之各種處理階段處之一結構之一部分之圖解橫截面圖。
圖13A係圖13之結構之一俯視圖；其中圖13之視圖沿著圖13A之線13-13。
圖15A係圖15之結構之一俯視圖；其中圖15之視圖沿著圖15A之線15-15。
在一些實施例中，本發明包含用於形成橫越複數個電性導體柱之一平坦化表面之方法。此等柱可對應於穿過基板之互連件，且在一些實施例中可包括銅。
參考圖1至圖15而描述實例性實施例。
參考圖1及圖1A，圖中展示包括延伸至一半導體基底12中之複數個電性導體柱20至22之一半導體結構10。在一些實施例中，基底12可對應於一半導體晶粒。此晶粒具有一背側14及一前側16。積體電路(圖中未展示)可與前側相關聯，且提供一虛線17以圖解地繪示該晶粒內之該電路之一大致邊界。該積體電路可包括記憶體(例如NAND、DRAM等等)、邏輯等等。雖然該積體電路可主要與前側相關聯，但在一些實施例中亦可存在與背側相關聯之積體電路。
背側具有一表面15。柱20至22具有位於背側表面15上方之頂面及自該等頂面延伸至背側表面15之側壁表面。例如，圖中展示包括一頂面25及包括自頂面25延伸至基底12之背側表面15之側壁表面23之導體柱20。
基底亦將具有一前側表面，且在一些實施例中，柱20至22可完全穿過晶粒，使得該等柱具有沿著晶粒之前側表面之表面。圖1中未繪示該前側表面。晶粒之該前側表面可在圖1及圖1A之處理階段處接合至一載體晶圓(圖中未展示)以有助於透過處理設備而運輸晶粒。
基底12可包括單晶矽，且可被稱為一半導體基板或一半導體基板之一部分。術語「半導電基板」、「半導體結構」及「半導體基板」意指包括半導體材料(其包含(但不限於)主體半導體材料)之任何結構，諸如一半導體晶圓(單獨地或位於包括其他材料之總成中)及半導體材料層(單獨地或位於包括其他材料之總成中)。術語「基板」意指任何支撐結構，其包含(但不限於)上述半導體基板。
電性導體柱20至22可包括任何適合電性導體組合物或組合物之組合。在一些實施例中，該等柱可包括形成於基板穿孔(TSV)內之一或多個電性導體組合物。在一些實施例中，該等柱可包括銅。
在圖1及圖1A之所展示實施例中，形成距基底12之背側表面15上方變動距離之柱。暴露柱尺寸之此不均勻性可例如源自於用於製造柱之處理及/或發生在柱之表面之研磨期間或之後之總厚度變動(TTV)。在一些實施例中，暴露柱尺寸之變動可大於1微米、大於10微米等等。
參考圖2，形成橫越表面15且沿著柱20至22之側壁及頂面之一襯層26。襯層26可包括任何適合組合物或組合物之組合。雖然圖中展示之襯層為一單一同質組合物，但在一些實施例中，襯層可包括兩個或兩個以上離散材料。例如，襯層可包括氮化矽上之二氧化矽。在一些實施例中，襯層26由無機材料組成。在一些實施例中，襯層包括一銅障壁材料，諸如包括釕或氧化釕、基本上由釕或氧化釕組成或由釕或氧化釕組成之一材料。該銅障壁材料可與包括銅之柱一起使用，且可緩解或防止否則可發生於含銅之柱中之銅擴散。可單獨地或與二氧化矽及氮化矽之一或兩者組合地利用含釕材料。相應地，在一些實例性實施例中，襯層26包括二氧化矽、氮化矽及釕之一或多者、基本上由二氧化矽、氮化矽及釕之一或多者組成或由二氧化矽、氮化矽及釕之一或多者組成。
可藉由例如包含原子層沈積(ALD)、化學氣相沈積(CVD)及物理氣相沈積(PVD)之任何適合方法而形成襯層26。
形成具有任何適合厚度之襯層，且將在一些實施例中形成具有小於或等於500奈米之一厚度之襯層。
在一些實施例中，可期望在低溫處(即，在小於或等於約200℃之一溫度處)形成襯層26以避免負面影響與基底12相關聯之電路。在此 等實施例中，襯層包括在小於或等於約200℃之一溫度處沈積之氮化矽、基本上由在小於或等於約200℃之一溫度處沈積之氮化矽組成或由在小於或等於約200℃之一溫度處沈積之氮化矽組成。
參考圖3，填充材料28形成於襯層26上及柱20至22之間。在所展示實施例中，填充材料設置於柱之間之區域內，但未設置於柱之上方。在其他實施例(諸如圖8所展示之一實施例)中，可提供至少覆蓋柱之若干者之具有一厚度之填充材料。
填充材料可包括任何適合組合物或組合物之組合，且在一些實施例中可包括一或多個有機(即，含碳)組合物。例如，在一些實施例中，填充材料28可包括光阻劑、基本上由光阻劑組成或由光阻劑組成。
可提供具有任何適合厚度之填充材料。在一些實施例中，可提供具有自約500奈米至約4微米範圍內之一厚度之填充材料。在一些實施例中，填充材料及襯層之組合厚度可在自約500奈米至約5微米之一範圍內。
參考圖4，結構10經受平坦化以形成一平坦化表面29。可利用諸如(例如)化學機械拋光(CMP)之任何適合方法來完成該平坦化。在所展示實施例中，該平坦化移除填充材料28(圖3)，且形成橫越襯層26及柱20至22而延伸之平坦化表面29。在其他實施例(諸如(例如)以下參考圖9而描述之一實施例)中，平坦化表面可延伸橫越填充材料及柱。
參考圖5，形成橫越平坦化表面29之電性導體材料30，且圖案化遮罩材料31形成於該電性導體材料上。在一些實施例中，該電性導體材料可包括銅，且可用作為用於銅之隨後電解生長之一晶種材料(例如，材料30可包括鈦及銅之一混合物、基本上由鈦及銅之一混合物組成或由鈦及銅之一混合物組成)。在一些實施例中，圖案化遮罩材料31可包括經光微影圖案化之光阻劑。
圖案化遮罩材料具有於其內延伸穿過以分別暴露柱20至22上方之區域之開口32至34。
參考圖6，電性導體材料36及38形成於開口32至34內。在一些實施例中，材料36可包括生長於電性導體材料30上之銅、基本上由生長於電性導體材料30上之銅組成或由生長於電性導體材料30上之銅組成；且材料38包括鎳或鈀。雖然在所展示實施例中兩個材料36及38形成於開口32至34內，但在其他實施例中一單一導體材料可形成於該等開口內或兩個以上材料可形成於此等開口內。例如，在一些實施例中，鎳及鈀兩者可形成於含銅材料36上。材料36及38可最終併入至凸塊下金屬(UBM)中，因此，在一些實施例中，材料36及38可包括適合於用在UBM中之習知組合物。
材料36及38一起形成分別位於開口32至34內之堆疊40至42。在所展示實施例中，遮罩材料31之介入區域使此等堆疊彼此隔開。
參考圖7及圖7A，移除遮罩材料31(圖6)，隨後，在材料30之蝕刻期間將堆疊40至42用作為一硬遮罩。圖7及圖7A之結構可被視為包括複數個電性導體蓋44至46，其等包括與堆疊40至42之材料36及38組合之材料30。蓋44至46與柱20至22一一對應，且可最終對應於用於將焊料球或其他佈線組件(圖中未展示)與柱電性耦合之UBM。
蓋44至46可具有任何適合形狀，且圖7A展示其中蓋呈圓形之一實施例。
參考圖8至圖12而描述用於形成橫越多個電性導體柱延伸之一平坦化表面之另一實例性實施例方法。
參考圖8，圖中展示類似於以上參考圖3而描述之處理階段之一處理階段處之一結構10a。圖8之結構與圖3之結構之略微不同點在於：圖中展示填充材料28覆蓋柱21。提供此差異以繪示：在各種實施例中，填充材料28之深度可變動。在一些實施例中，可提供具有與圖 3之處理階段處所繪示深度相同之圖8之處理階段處之深度之填充材料28，或反之亦然。
參考圖9，形成橫越結構10a之一平坦化表面49。可利用例如CMP來形成此平坦化表面。該平坦化表面延伸橫越柱20至22及填充材料28。在所展示實施例中，該平坦化表面亦延伸橫越與柱20至22之側壁鄰近之襯層26之部分。
參考圖10，相對於襯層26及柱20至22而選擇性移除填充材料28(圖9)。在一些實施例中，填充材料包括一有機組合物(例如光阻劑)，且利用氧化條件(例如以電漿形成存在之O2)來相對於襯層26及柱20至22之無機組合物而選擇性移除填充材料。柱20至22之頂部區域包括平坦化表面49。
參考圖11，形成橫越襯層26及柱20至22之電性導體材料30，圖案化遮罩材料31形成於材料30上，且導體材料36及38形成於延伸穿過遮罩材料31之開口32至34內。
參考圖12及圖12A，圖中展示類似於圖7及圖7A之處理階段之一處理階段處之結構10a。已移除遮罩材料31(圖11)，且將材料30、36及38併入至複數個電性導體蓋44a至46a中。在一些實施例中，形成直接緊貼襯層26及柱之上表面之材料30(如圖所展示)，且材料36對應於電解地生長於材料30上之含銅材料。
在圖12及圖12A之所展示實施例中，柱20至22具有對應於平坦化表面49之平坦化上表面，且具有自該等平坦化上表面延伸至基底12之背側表面15之側壁表面。例如，柱20具有所繪示之側壁表面23。在所展示實施例中，導體材料30直接緊貼柱之上表面，因此，蓋44a至46a直接緊貼柱之平坦化上表面。蓋44a至46a具有沿著柱之側壁表面向下延伸之區域。例如，圖中展示具有沿著柱20之側壁表面23延伸之區域50之蓋44a。沿著側壁之蓋之區域可被稱為「邊緣」，且在所展示實施 例中，襯層26將該等區域與柱之側壁表面分離。
蓋44a至46a可具有任何適合形狀，且圖12A展示其中蓋呈圓形之一實施例。
參考圖13至圖15而描述用於形成橫越多個電性導體柱延伸之一平坦化表面之另一實例性實施例方法。
參考圖13及圖13A，圖中展示圖10之處理階段後之一處理階段處一結構10b。一圖案化電性絕緣材料60形成於襯層26上。該圖案化電性絕緣材料包括薄區域63及厚區域65。該等薄區域可被視為界定圍繞柱之平坦化上表面49延伸之插入區域62。
材料60可包括任何適合組合物或組合物之組合，且可例如包括聚醯亞胺、基本上由聚醯亞胺組成或由聚醯亞胺組成。在一些實施例中，襯層26包括藉由一低溫程序而形成之氮化矽。此氮化矽可具有於其內延伸或延伸穿過其之針孔。在此等實施例中，材料60可用於閉塞此等針孔，使得隨後形成之蓋(具體言之，以下參考圖15而描述之蓋44b至46b)之電性導體材料不直接接觸基底12之半導體材料。
可利用任何適合方法來圖案化材料60。在一些實施例中，可利用產生一光阻遮罩(圖中未展示)內之階梯式區域之一光微影程序來在一大片材料60上形成該遮罩(例如，一「洩漏」標線可用於圖案化該遮罩)，接著，可用一或多個適當蝕刻來將一圖案自該光阻遮罩轉移至材料60。此可在材料60內形成階梯式區域，其中該等階梯式區域之薄部分對應於區域63且該等階梯式區域之厚部分對應於區域65。接著，可移除該光阻遮罩以留下圖13及圖13A之結構。
透過材料60而暴露柱20至22之上表面。在一些實施例中，可在形成一大片材料60之後且在形成材料60內之階梯式區域之前進行蝕刻及/或平坦化以暴露柱20至22之上表面。
參考圖14，圖中展示類似於圖11之處理階段之一處理階段處之結 構10b。形成橫越材料60及柱20至22之電性導體材料30，圖案化遮罩材料31形成於材料30上，且導體材料36及38形成於延伸穿過遮罩材料31之開口32至34內。
參考圖15及圖15A，圖中展示類似於圖12及圖12A之處理階段之一處理階段處之結構10b。已移除遮罩材料31(圖14)，且將材料30、36及38併入至複數個電性導體蓋44b至46b中。該等蓋具有沿著柱20之側壁表面延伸之邊緣(例如，蓋44b之邊緣50沿著柱20之側壁表面23延伸)；其中在所展示實施例中，襯層26使該等邊緣與柱之側壁表面分離。
本文中所描述之實施例之若干者可有利地避免與橫越穿過基板之互連件(例如類似於圖1至圖15之柱20至22之互連件)之銅及矽(例如類似於圖1至圖15之基底12之一含矽晶粒)兩者之平坦化相關聯之先前技術問題。具體言之，與包括襯層26(圖4之實施例)及/或填充材料28(圖9之實施例)之一暴露表面同步地平坦化柱20至22。因此，若柱20至22包括在平坦化期間被塗抹之銅或另一材料，則經塗抹之導體材料不會直接緊貼基底12之半導體材料，而是會代以沿著襯層26及/或填充材料28。隨後，可在下伏材料之移除期間移除經塗抹之導體材料(例如，在圖9及圖10之實施例中，可在填充材料之移除期間除去橫越填充材料28塗抹之任何導體材料)，或若此不負面影響所得結構之效能，則可使經塗抹之電性導體材料留在下伏絕緣材料上。
在一些實施例中，本文中所描述之處理之優點可包含：緩解或防止柱研磨銅塗抹；緩解或防止與矽乾式蝕刻化學處理相關聯之問題(例如硫化物形成、非均勻蝕刻速率等等)；能夠在無需研磨成用於穿過基板之互連件之柱情況下控制過量柱研磨總厚度變動；及/或利用一高精確度步進器來消除一處理步驟。
在一些實施例中，襯層26及/或填充材料28可給柱20至22提供支 撐以緩解或防止可發生在先前技術程序(其中無法在橫越類似柱之平坦化期間充分支撐該等柱)中之傾斜、彎曲、斷裂等等。
在一些實施例中，可將本文中所描述之結構併入至混合式記憶體立方(HMC)架構中，諸如(例如)包括堆疊於邏輯電路上之DRAM電路之架構。
圖式中之各種實施例之特定定向僅供說明，且在一些應用中，可相對於所展示定向而旋轉實施例。本文中所提供之描述及以下申請專利範圍針對具有各種特徵之間之所描述關係之任何結構，不管該等結構是否沿圖式之特定定向或相對於此定向旋轉。
隨附說明之橫截面圖僅展示橫截面之平面內之特徵，且不展示橫截面之平面後方之材料以簡化圖式。
當一結構在上文中被稱為「在另一結構上」或「緊貼另一結構」時，其可直接位於該另一結構上或亦可存在介入結構。相比而言，當一結構被稱為「直接在另一結構上」或「直接緊貼另一結構」時，不存在介入結構。當一結構被稱為「連接」或「耦合」至另一結構時，其可直接連接或耦合至該另一結構，或可存在介入結構。相比而言，當一結構被稱為「直接連接」或「直接耦合」至另一結構時，不存在介入結構。
一些實施例包含橫越延伸至一半導體基板中之複數個電性導體柱之平坦化之一方法。形成橫越一基板表面且沿著該等柱之側壁表面及頂面之一襯層。填充材料形成於該襯層上及該等柱之間。該填充材料包括一或多個有機組合物。一平坦化表面經形成以延伸橫越該等柱及橫越該襯層及該填充材料之一或兩者。
一些實施例包含平坦化延伸至一半導體基板中之複數個電性導體柱之一方法。形成橫越一基板表面且沿著該等柱之側壁表面及頂面之一襯層。該襯層包括一或多個無機組合物。填充材料形成於該襯層 上及該等柱之間。該填充材料包括一或多個有機組合物。一平坦化表面經形成以延伸橫越該填充材料及該等柱。在形成該平坦化表面之後，使用一蝕刻來自該等柱之間移除該填充材料，同時留下沿著該等柱之側壁表面且橫越該等柱之間之基板表面之該襯層。用於移除該填充材料之該蝕刻可例如包括適合濕式化學處理或適合乾式化學處理，且在一些實施例中可利用氧化劑。
一些實施例包含平坦化延伸至一半導體基板中之複數個電性導體柱之一方法。一襯層形成於一基板表面上且沿著該等柱之側壁表面及頂面。填充材料形成於該襯層上及該等柱之間。一平坦化表面經形成以延伸橫越該等柱及該襯層。電性導體材料形成於該平坦化表面上。電性導體蓋形成於該電性導體材料上。該等電性導體蓋之形成包括：在該電性導體材料上形成一圖案化遮罩；在該電性導體材料上之延伸穿過該圖案化遮罩之開口內生長一含銅層；在該圖案化遮罩中之該等開口內之該含銅層上形成鎳及鈀之一或兩者(該含銅層與鎳及鈀之該一或兩者一起形成該電性導體材料上之隔開堆疊)；移除該圖案化遮罩；及自該等堆疊之間之空間移除該電性導體材料。
一些實施例包含一半導體結構。該結構具有延伸穿過一半導體晶粒之電性導體柱。該等柱具有位於該晶粒之一背側表面上方之上表面，且具有在該晶粒之該背側表面與該等上表面之間延伸之側壁表面。一襯層沿著該等柱之該等側壁表面。電性導體蓋直接緊貼該等柱之該等上表面，且具有沿著該等柱之側壁表面且藉由該襯層而與該等側壁表面間隔之邊緣。
10‧‧‧半導體結構
12‧‧‧半導體基底
14‧‧‧背側
16‧‧‧前側
17‧‧‧虛線
20‧‧‧電性導體柱
21‧‧‧電性導體柱
22‧‧‧電性導體柱
26‧‧‧襯層
29‧‧‧平坦化表面
30‧‧‧電性導體材料
36‧‧‧電性導體材料
38‧‧‧電性導體材料
40‧‧‧堆疊
41‧‧‧堆疊
42‧‧‧堆疊
44‧‧‧電性導體蓋
45‧‧‧電性導體蓋
46‧‧‧電性導體蓋

Claims (34)

  1. 一種平坦化延伸至一半導體基板中之複數個電性導體柱之方法，該方法包括：形成橫越一基板表面且沿著該等柱之側壁表面及頂面之一襯層；在該襯層上及該等柱之間形成填充材料，該填充材料包括一或多個有機組合物；及平坦化以形成延伸橫越該等柱及橫越該襯層及該填充材料之一或兩者之一平坦化表面。
  2. 如請求項1之方法，其中該填充材料包括光阻劑。
  3. 如請求項1之方法，其中該基板包括一半導體晶粒；其中該表面係該晶粒之一背側表面；且其中該等電性導體柱完全地延伸穿過該晶粒。
  4. 如請求項1之方法，其中該平坦化形成延伸橫越該襯層及該等柱之該平坦化表面；該方法進一步包括形成直接緊貼該等柱之該等平坦化表面且與該等柱一一對應之電性導體蓋。
  5. 如請求項1之方法，其中該平坦化形成延伸橫越該填充材料及該等柱之該平坦化表面；該方法進一步包括：在形成該平坦化表面之後，自該等柱之間移除該填充材料，同時留下沿著該等柱之側壁表面且橫越該等柱之間之該基板表面之該襯層。
  6. 如請求項5之方法，其中該填充材料之該移除包括濕式或乾式化學處理。
  7. 如請求項5之方法，其進一步包括形成直接緊貼該等柱之平坦化上表面且沿著該等柱之該等側壁表面之電性導體蓋；沿著該等柱之該等側壁表面之該等導體蓋之區域藉由該襯層而與該等側 壁表面間隔開。
  8. 如請求項5之方法，其進一步包括：在該平坦化之後，形成橫越該襯層之圖案化電性絕緣材料；該圖案化電性絕緣材料界定圍繞該等柱之平坦化上表面之插入區域；及形成位於該等插入區域內且直接緊貼該等柱之該等平坦化上表面且沿著該等柱之該等側壁表面之電性導體蓋；沿著該等柱之該等側壁表面之該等導體蓋之區域藉由該襯層而與該等側壁表面間隔開。
  9. 如請求項8之方法，其中該圖案化電性絕緣材料包括聚醯亞胺。
  10. 如請求項8之方法，其中該襯層包括具有於其內延伸之一或多個針孔之氮化矽；且其中該圖案化電性絕緣材料填充該一或多個針孔。
  11. 如請求項1之方法，其中該等電性導體柱包括銅。
  12. 如請求項11之方法，其中該襯層包括氮化矽。
  13. 如請求項11之方法，其中該襯層包括釕。
  14. 一種平坦化延伸至一半導體基板中之複數個電性導體柱之方法，該方法包括：形成位於一基板表面上且沿著該等柱之側壁表面及頂面之一襯層；該襯層包括一或多個無機組合物；在該襯層上及該等柱之間形成填充材料；該填充材料包括一或多個有機組合物；平坦化以形成延伸橫越該填充材料及該等柱之一平坦化表面；及在該平坦化之後，自該等柱之間移除該填充材料，同時留下沿著該等柱之側壁表面且橫越該等柱之間之該基板表面之該襯 層。
  15. 如請求項14之方法，其中該基板包括一半導體晶粒；其中該表面係該晶粒之一背側表面；且其中該等電性導體柱係完全地延伸穿過該晶粒之含銅柱。
  16. 如請求項14之方法，其進一步包括：形成直接緊貼該等柱之平坦化上表面且直接緊貼沿著該等柱之該等側壁表面之該襯層之電性導體材料；及在該電性導體材料上生長銅以在該等柱之該等平坦化上表面上形成電性導體蓋。
  17. 如請求項14之方法，其進一步包括：在該平坦化之後，形成橫越該襯層之圖案化電性絕緣材料；該圖案化電性絕緣材料界定圍繞該等柱之平坦化上表面之插入區域；形成直接緊貼該等柱之平坦化上表面且直接緊貼沿著該等柱之該等側壁表面之該襯層之電性導體材料；及在該電性導體材料上生長銅以在該等柱之該等平坦化上表面上形成電性導體蓋。
  18. 一種橫越延伸至一半導體基板中之複數個電性導體柱之平坦化之方法，該方法包括：形成橫越一基板表面且沿著該等柱之側壁表面及頂面之一襯層；在該襯層上及該等柱之間形成填充材料；平坦化以形成延伸橫越該等柱及該襯層之一平坦化表面；在該平坦化表面上形成電性導體材料；及在該電性導體材料上形成電性導體蓋；該等電性導體蓋之該形成包括： 在該電性導體材料上形成一圖案化遮罩；在延伸穿過該圖案化遮罩之開口內之該電性導體材料上生長一含銅層；在該圖案化遮罩中之該等開口內之該含銅層上形成鎳及鈀之一或兩者；該含銅層與鎳及鈀之該一或兩者一起形成該電性導體材料上之隔開堆疊；移除該圖案化遮罩；及自該等堆疊之間之空間移除該電性導體材料。
  19. 如請求項18之方法，其中該襯層包括氮化矽。
  20. 如請求項18之方法，其中該襯層包括釕。
  21. 如請求項18之方法，其中該襯層僅由一同質物質組成。
  22. 如請求項18之方法，其中該襯層包括兩個或兩個以上物質。
  23. 如請求項22之方法，其中該襯層包括氮化矽上之二氧化矽。
  24. 如請求項18之方法，其中該填充材料包括碳。
  25. 如請求項18之方法，其中該填充材料包括光阻劑。
  26. 一種半導體結構，其包括：電性導體柱，其等延伸穿過一半導體晶粒；該等柱具有位於該晶粒之一背側表面上方之上表面，且具有在該晶粒之該背側表面與該等上表面之間延伸之側壁表面；一襯層，其沿著該等柱之該等側壁表面；及電性導體蓋，其等直接緊貼該等柱之該等上表面；該等蓋具有沿著該等柱之側壁表面且藉由該襯層而與該等側壁表面間隔開之邊緣。
  27. 如請求項26之結構，其進一步包括界定圍繞該等柱之該等上表面之插入區域之圖案化電性絕緣材料；且其中該等蓋之該等邊緣延伸至該等插入區域中。
  28. 如請求項27之結構，其中該圖案化電性絕緣材料包括聚醯亞胺。
  29. 如請求項26之結構，其中該襯層僅由一同質物質組成。
  30. 如請求項29之結構，其中該襯層由氮化矽組成。
  31. 如請求項29之結構，其中該襯層包括釕。
  32. 如請求項31之結構，其中該等電性導體柱包括銅。
  33. 如請求項26之結構，其中該襯層包括兩個或兩個以上物質。
  34. 如請求項26之結構，其中該等電性導體蓋包括鎳及鈀之一或兩者。
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EP2826061A1 (en) 2015-01-21
WO2013138006A1 (en) 2013-09-19
US8519516B1 (en) 2013-08-27
US20150228603A1 (en) 2015-08-13
TWI514535B (zh) 2015-12-21
US20130234319A1 (en) 2013-09-12
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CN104285280B (zh) 2017-03-08
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US9029257B2 (en) 2015-05-12
US20130309861A1 (en) 2013-11-21

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