CN101752336A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN101752336A
CN101752336A CN200910141082A CN200910141082A CN101752336A CN 101752336 A CN101752336 A CN 101752336A CN 200910141082 A CN200910141082 A CN 200910141082A CN 200910141082 A CN200910141082 A CN 200910141082A CN 101752336 A CN101752336 A CN 101752336A
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China
Prior art keywords
semiconductor
separator
silicon
based end
hole electrode
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CN101752336B (zh
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张宏宾
许国经
陈承先
邱文智
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种半导体装置及其制造方法，包括用于叠置芯片的凸块结构。在一半导体基底内形成硅通孔电极。对半导体基底的背侧进行薄化，以露出硅通孔电极。在半导体基底的背侧及硅通孔电极的露出部分上方形成一隔离层。对隔离层进行薄化，以再次露出硅通孔电极。在半导体基底的背侧形成焊垫及重布线，以电性连接硅通孔电极。形成另一隔离层并进行图案化，再形成一阻挡层，以提供接触接垫来连接外部装置，例如，另一芯片/晶片或电路板。本发明解决了现有技术存在的问题，易于在热预算内形成重布线层。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种集成电路，特别涉及一种用于半导体芯片(die)的凸块(bump)结构，其具有用于叠置芯片的硅通孔电极(through-silicon via，TSV)。
背景技术
自集成电路的发明创造以来，由于各个电子部件(即，晶体管、二极管、电阻、电容等等)的集成度(integration density)持续的改进，使半导体业持续不断的快速成长发展。主要来说，集成度的改进来自于最小特征尺寸(minimum feature size)不断缩小而容许更多的部件整合至既有的芯片面积内。
这些集成度的改进实质上是朝二维(two-dimensional，2D)方面的，因为集成部件所占的体积实际上位于半导体晶片的表面。尽管光刻(lithography)技术的精进为2D集成电路制作带来相当大的助益，二维空间所能拥有的密度还是有其物理限制。这些限制之一在于制作这些部件所需的最小尺寸。再者，当更多的装置放入一芯片中，需具有更复杂的电路设计。
为了进一步增加集成电路密度，已开始研究三维(3D)集成电路(three-dimensional integrated circuit，3DIC)。在典型的3DIC工艺中，二个芯片彼此接合，且在每一芯片与基底上的接触接垫之间形成电性连接。例如，在彼此上方接合两个芯片。叠置的芯片接着与一承载基底(carrier substrate)接合，而接线将每一芯片上的接触接垫电性耦接至承载基底上的接触接垫。然而，上述做法需要一个大于芯片的承载基底来进行打线工艺(wirebonding)。
近来，已开始注意所谓的硅通孔电极(TSV)。一般而言，硅通孔电极是通过蚀刻在基底中形成一垂直通孔并于其中填入导电材料而成，例如铜。对基底背侧进行薄化，以露出TSV，而另一芯片则与露出的TSV接合，进而形成堆叠芯片封装(stacked die package)。若基底使用不同技术或脚位(pin-out)来与另一芯片/晶片接合，则需要一重布(redistribution)线层。
由于基底在薄化及接合之前是接合至一临时载板，因此热预算通常会是个考虑点。为了能够进行低温接合工艺，会使用焊球将另一基底接合至硅通孔电极。然而，由于需要一重布线层，必须进行额外的膜层制作来形成重布线层，而对于在热预算内形成重布线层来说是相当困难的。
因此，有必要寻求一种新的接合TSV的结构及方法。
发明内容
为了解决现有技术存在的上述问题，本发明一实施例提供一种半导体装置。半导体装置具有一半导体基底，其具有多个硅通孔电极延伸穿过并突出于半导体基底的一背侧。一第一隔离层，位于相邻的硅通孔电极之间半导体基底的背侧，且未延伸超过突出的硅通孔电极。多个导电部件具有渐细侧壁且分别电性耦接至硅通孔电极。一第二隔离层，位于第一隔离层上。在其他实施例中，导电部件包括一重布线且具有渐细侧壁。重布线可位于第一隔离层与第二隔离层之间。
本发明另一实施例提供一种半导体装置的制造方法。提供一半导体基底，具有一硅通孔电极自半导体基底的一第一侧延伸于其内。在半导体基底的一第二侧露出硅通孔电极。在半导体基底的第二侧形成一第一隔离层，且使硅通孔电极露出。在硅通孔电极上形成具有渐细侧壁的一导电部件。在第一隔离层上形成材料不同于第一隔离层的一第二隔离层。在导电部件上形成一接触阻挡层。导电部件可包括一重布线。
本发明又一实施例提供一种半导体装置的制造方法。提供一第一半导体基底，其具有多个硅通孔电极自第一半导体基底的一电路侧延伸至第一半导体基底的一背侧以及位于背侧上的每一硅通孔电极上具有渐细侧壁的一导电接垫。第一半导体基底的背侧具有一第一隔离层以及位于第一隔离层上的一第二隔离层。提供一第二半导体基底，其具有多个上接触点。将第一半导体基底接合至第二半导体基底，使第二半导体基底的每一上接触点电性耦接至第一半导体基底上对应的导电接垫。
本发明解决了现有技术存在的上述问题，易于在热预算内形成重布线层。
附图说明
图1至图13为示出根据本发明实施例的具有用于叠置芯片的凸块结构的半导体装置局部制造过程剖面示意图。
图14为示出根据本发明实施例的脚位配置平面示意图。
图15至图17为示出根据本发明另一实施例的叠置芯片的局部制造过程剖面示意图。
上述附图中的附图标记说明如下：
110～半导体基底；112～电路；114～蚀刻终止层；116～内层介电层；118～接触窗；120～金属层间介电层；122、1512～上金属接点；124～硅通孔电极；126～衬层；128～导电凸块；130～承载基底；310～第一隔离层；510～晶种层；610～第一掩模图案层；612～开口；710～导电部件；1010～第二隔离层；1110～第二掩模图案层；1310～接触阻挡层；1410～接触接垫；1412～重布线；1510～基底；1514～连接部件。
具体实施方式
以下说明本发明实施例的制作与使用。然而，必须了解的是本发明提供许多适当的实施例的发明概念，可实施于不同的特定背景。述及的特定实施例仅用于说明以特定的方法来制作及使用本发明，而并非用以局限本发明的范围。
本发明实施例有关于使用具有硅通孔电极的基底的金属焊垫。以下所说明的实施例关于金属焊垫与重布线层的整合，使其能够同时制造重布线层与金属焊垫。再者，金属焊垫较佳为具有渐细(tapered)侧壁，借以在晶片和/或芯片堆叠工艺中提供较大的接合界面。
图1至图14使用于三维集成电路(3DIC)或叠置芯片中具有凸块(bump)结构和/或重布线层的芯片的局部制造过程剖面示意图。而在本发明各个实施例中，相同的部件使用相同的标号。
请参照图1，一半导体基底100具有电路112形成于上。半导体基底100可包括掺杂或未掺杂的硅块材或是绝缘层上覆半导体(semiconductor-on-insulator，SOI)基底的有源(active)层。一般而言，SOI基底包括形成于一绝缘层上的一半导体材料层，例如硅。绝缘层可为埋入式氧化(buried oxide，BOX)层或是氧化硅层。绝缘层形成于一基底上，通常为硅基底或玻璃基底。另外也可使用其他基底，例如多层或渐层(gradient)基底。
形成于半导体基底110上的电路112可为适用于特定应用的任一类型电路。在一实施例中，电路112包括形成于基底上的电子装置，而电子装置上具有一层或多层的介电层。金属层可形成于介电层之间，以作为电子装置之间传送电子信号的路径。电子装置也可形成于一层或多层的介电层内。
举例而言，电路112可包括各个不同的N型金属氧化物半导体(N-typemetal-oxide semiconductor，NMOS)装置和/或P型金属氧化物半导体(PMOS)装置，例如晶体管、电容、电阻、二极管、光电二极管、熔丝等等，其相互连接以实施单一或多种功能。这些功能可包括存储结构、工艺结构、传感器、放大器、电源分配、输入/输出电路等等。所属技术领域中普通技术人员可以理解上述范例说明仅在于进一步解释本发明的应用而并非用以局限本发明。对于特定应用来说，也可使用其他电路。
图1也示出一蚀刻终止层114及一层间介电(inter-layer dielectric，ILD)层116。蚀刻终止层114较佳由一介电材料所构成且与相邻的膜层，例如下方的半导体基底110及上方的ILD层116，具有不同的蚀刻选择比。在一实施例中，蚀刻终止层114可由SiN、SiCN、SiCO、CN、或其组合等等所构成，且可通过化学气相沉积(chemical vapor deposition，CVD)或等离子体辅助化学气相沉积(plasma-enhanced CVD，PECVD)技术而形成。
ILD层116可由低介电常数(low-k)介电材料所形成，例如氧化硅、磷硅玻璃(phosphosilicate glass，PSG)、硼磷硅玻璃(borophosphosilicate glass，BPSG)、氟硅玻璃(fluorinated silicate glass，FSG)、SiOxCy、旋涂玻璃(spin-onglass，SOG)、旋涂高分子、碳化硅材料、其化合物、其复合材料、或其组合等等，并通过适当的公知方法制造而成，例如旋涂法、CVD或PECVD。须注意的是蚀刻终止层114及ILD层116可各自包括多个介电层，其中相邻的介电层之间可具有或不具有蚀刻终止层。
接触窗118贯穿ILD层116以提供电路112电性接触之用。接触窗118的制作可通过使用光刻技术在ILD层116上沉积及图案化一光致抗蚀剂材料而露出部分的ILD层116来形成接触窗118。可使用蚀刻工艺，例如异向性(anisotropic)干蚀刻工艺，在ILD层116内形成开口。最好在开口内沿表面形成扩散阻挡层和/或黏着层(未示出)，并填入导电材料。扩散阻挡层可包括一层或多层的TaN、Ta、TiN、Ti、或CoW等等，且导电材料可包括铜、钨、铝、银、或其组合，借以形成图1所示的接触窗118。
在ILD层116上形成一层或多层的金属层间介电(inter-metal dielectric，IMD)层120及配置的金属化层(未示出)。一般而言，IMD层120及所配置的金属化层是用于彼此电路的连接，并提供外部电性连接之用。IMD层120较佳由low-k介电材料所构成，例如由PECVD或是高密度等离子体化学气相沉积(high-density plasma CVD，HDPCVD)技术所形成的氟硅玻璃(FSG)，IMD层120也可包括中间蚀刻终止层，其与蚀刻终止层114相似。在最上层的IMD层中具有上金属接点122，以提供外部电性连接之用。
图1也示出硅通孔电极(through-silicon via，TSV)124。硅通孔电极124可由任何合适的方法所形成。举例而言，在形成ILD层116之前，通过单一或多重蚀刻工艺、钻孔、及激光技术等等，形成延伸于半导体基底110内的开口。最好在开口内沿表面形成一衬层，如作为隔离层的衬层126，且在开口内填入一导电材料。衬层126较佳由一层或多层的SiN、氧化物、或高分子等等所构成，而导电材料较佳为包括铜、钨、铝、银、或其组合等等，借以形成硅通孔电极124。另外也可使用其他材料，包括导电扩散阻挡层，如TaN、Ta、TiN、Ti、或CoW等等。
须注意的是附图中硅通孔电极124是从半导体基底110的上表面延伸于其内，此处仅作为说明的目的，然而也可使用其他的配置。举例而言，在另一实施例中，硅通孔电极124可从ILD层116或是其中一IMD层120的上表面延伸。举例而言，在一实施例中，硅通孔电极124的制造可在形成接触窗118之后，通过单一或多重蚀刻工艺、钻孔、或激光技术等等，形成延伸于半导体基底110内的开口。最好在开口内沿表面形成一衬层，如作为隔离层的衬层126，且在开口内填入如之前所述的导电材料。
在上金属接点122上形成导电凸块128，例如由Cu、W、CuSn、AuSn、InAu、或PbSn等等所构成的金属凸块，且利用一黏着层132使一承载基底130贴附于IMD层120的上表面。一般而言，承载基底130提供后续工艺步骤期间物理或结构上的支撑之用。通过此方式可降低或防止半导体基底110的损害。
承载基底130可包括玻璃、氧化硅、或氧化铝等等。黏着层132可为任何适合的黏着材料，例如UV胶，其接触到紫外(UV)光后会失去黏性。承载基底130的厚度较佳在几密尔(mil)到几十密尔的范围。
图2示出根据本发明实施例的对半导体基底110的背侧进行薄化(thinning)工艺，以露出硅通孔电极124/衬层126。可使用机械研磨工艺、化学机械研磨(chemical mechanical polishing，CMP)工艺、蚀刻工艺和/或其组合来进行薄化工艺。举例而言，可进行初步平坦化工艺，如研磨或CMP，以初步露出硅通孔电极124。之后，进行湿式或干式蚀刻，其对于衬层126的材料与半导体基底110的材料之间具有高蚀刻选择比而使半导体基底110向下凹陷，因而硅通孔电极124及衬层126突出于半导体基底110的下侧，如图2所示。在一实施例中，硅通孔电极124由铜所构成，且衬层126由TaN所构成。而可使用HBr/O2、HBr/Cl2/O2、SF6/Cl2、或SF6等等离子体来进行干蚀刻而使半导体基底110向下凹陷。硅通孔电极124及衬层126所露出的长度在次微米(sub-μm)至几微米的范围。
图3示出根据本发明实施例的在半导体基底110(半导体基底110表面上可形成一原生氧化层(native oxide))的背侧形成一第一隔离层310。在一实施例中，第一隔离层310为介电材料，例如SiN、氧化物、SiC、SiON、或高分子等等，且可通过旋涂法、印刷、或CVD等方式而形成。第一隔离层310较佳为通过低温工艺而形成，如使用温度小于250℃的PECVD工艺，以防止接合用的黏着层劣化，而确保整合工艺始终的机械强度。第一隔离层310的厚度最好足以覆盖露出的硅通孔电极124。
取决于形成第一隔离层310所使用的工艺，可能需要进行平坦化工艺。比较特别的是在一些沉积方法中会形成一平整表面，如旋涂法。然而，在其他的方法中则会形成一顺应层，如CVD，因而需进行平坦化工艺，如研磨或CMP，以形成一平整表面，如图3所示。
图4示出根据本发明实施例的二次露出硅通孔电极124。可使用机械研磨工艺、CMP工艺、蚀刻工艺和/或其组合来进行薄化工艺。举例而言，可进行初步平坦化工艺，如研磨或CMP，以初步露出硅通孔电极124。之后，进行湿式或干式蚀刻，其对于硅通孔电极124及衬层126的材料与第一隔离层310的材料之间具有高蚀刻选择比而使第一隔离层310向下凹陷，因而使硅通孔电极124突出于第一隔离层310的下侧，如图4所示。在一实施例中，硅通孔电极124由铜所构成，且第一隔离层310由二氧化硅所构成。可使用氢氟酸来进行湿蚀刻或使用干蚀刻，而使第一隔离层310向下凹陷。另外也可使用其他的工艺及材料。硅通孔电极124所露出的长度在次微米(sub-μm)至几微米的范围。
除了向下凹陷第一隔离层310之外，图4也同时示出自硅通孔电极124所露出的部分去除衬层126。
请参照图5，在第一隔离层310的表面上及硅通孔电极124所露出的部分上顺应性沉积一晶种层510。晶种层510是由导电材料所构成的薄膜层，用以在后续工艺步骤期间辅助形成一厚膜层。在一实施例中，可通过使用CVD或物理气相沉积(physical vapor deposition，PVD)技术来沉积一薄导电层，例如Cu、Ti、Ta、TiN、或TaN等薄膜层而形成晶种层510。举例而言，通过PVD工艺来沉积Ti层，以形成一阻挡层，并通过PVD工艺来沉积Cu层，以形成一晶种层。
图6示出根据本发明实施例的在晶种层510上形成一第一掩模图案层610。第一掩模图案层610是作为后续工艺步骤中用于形成导电接垫的模具。第一掩模图案层610可为图案化的光致抗蚀剂层或硬式掩模(hard mask)等等。在一实施例中，光致抗蚀剂材料的厚度约在次微米至几微米的范围，且经由图案化而在硅通孔电极124上方形成开口612。
须注意的是图6的实施例中较佳为利用一内凹(re-entrant)轮廓，使开口612在沿着晶种层510的开口612的底部宽于开口612的顶部。可通过任何适宜的技术来形成内凹轮廓，例如使用具有不同图案化特性及可一次或多次曝光的多重光致抗蚀剂层、扩散技术、或是图像反转工艺等等。然而，在其他实施例中，第一掩模图案层610可利用一渐细轮廓，使开口612在沿着晶种层510的开口612的底部窄于开口612的顶部。
之后，请参照图7，导电部件710形成于开口612(示出于图6)内。导电部件710较佳为金属，例如铜、钨、或其他导电金属，且可通过电镀或无电电镀等工艺而形成。在一实施例中，采用电镀工艺，其中晶片没入(submerged)或浸入(immersed)于电镀溶液中。晶片表面电性连接至外部直流(DC)电源供应器的负电极侧，使晶片在电镀工艺中作为阴极。一固体阳极，例如铜阳极，也浸入于溶液中且连接至电源供应器的正电极侧。原子自阳极分解至溶液中，而阴极，例如晶片，则自溶液中获取原子，以在晶片中露出的导电区域进行电镀，例如开口612内所露出的晶种层510部分。
须注意的是导电部件710可为接触接垫和/或重布线。请参照图14，其为图1至图13中实施例的平面示意图，图7中左侧的导电部件710为一接触接垫，而图7中右侧的导电部件710为一接触接垫及一重布线。重布线容许电性连接至位于TSV以外位置的另一装置，例如芯片、晶片或是封装基底等等。此对于TSV、基底上的电路、及脚位(pin-out)的放置具有较大的弹性及较高的自主性。
请参照图8，其示出根据本发明实施例之去除第一掩模图案层610(示出于图6及图7)。在一实施例中，第一掩模图案层610为一光致抗蚀剂掩模，且可通过等离子体灰化(ashing)或湿式剥除(wet strip)工艺来去除第一掩模图案层610。较佳的等离子体灰化工艺使用O2，举例而言，其流量约在1000sccm至2000sccm的范围。工艺压力约在300mTorr至600mTorr的范围。工艺功率约在500Watts至2000Watts的范围。工艺温度约在80℃至200℃的范围。另外，进行等离子体灰化工艺之后也可浸入硫酸(H2SO4)溶液中，清洗晶片并去除残留的光致抗蚀剂材料。
图9示出去除晶种层510所露出的部分。举例而言，晶种层510所露出的部分可通过湿式蚀刻工艺来去除。
图10示出根据本发明实施例的形成一第二隔离层1010。第二隔离层1010的形成方法及材料可使用相似于第一隔离层310的形成方法及材料。然而，使用于形成第二隔离层1010的材料较佳为与使用于第一隔离层310的材料之间具有高蚀刻选择比。在上述方法中，第一隔离层310(及导电部件710)可作为后续工艺步骤中图案化第二隔离层1010的蚀刻终止层。第二隔离层1010的厚度较佳在2000埃
Figure G2009101410820D0000081
至8000埃的范围。以下所要说明的是图案化第二隔离层1010，以隔离部分的重布线，同时露出接触接垫的所在位置。
图11示出根据本发明实施例的形成一第二掩模图案层1110。第二掩模图案层1110的材料可使用相似于第一掩模图案层610的材料，例如光致抗蚀剂或是硬式掩模材料，而形成方法可使用相似于第一掩模图案层610的形成方法。然而，须注意的是第一掩模图案层610所采用的技术在于形成一内凹图案，而第二掩模图案层1110则是具有垂直图案。因此，任何适合的光刻技术都可用来形成第二掩模图案层1110。
图12示出根据本发明实施例的图案化第二隔离层1010以及去除第二掩模图案层1110。举例而言，在一实施例中，第二隔离层1010由氮化硅所构成，而第一隔离层310则由氧化硅所构成。第二隔离层1010可通过干式蚀刻工艺来进行图案化，其在第二隔离层1010的氮化硅与第一隔离层310的氧化硅之间具有高蚀刻选择比。
在图案化第二隔离层1010之后，可去除第二掩模图案层1110，如图12所示。举例而言，第二掩模图案层1110可通过等离子体灰化工艺或是湿式剥除工艺将其去除，如上述关于图8的说明。另外，去除第二掩模图案层1110之后也可进行一清洁步骤，例如浸入硫酸溶液中，以去除表面上任何的污染物。
图13示出根据本发明实施例的形成一接触阻挡层1310。接触阻挡层1310作为与外部装置形成电性连接的导电接触点，例如另一芯片、晶片、电路板、或封装板等等。接触阻挡层1310与硅通孔电极124作电性接触，再依次与形成于基底上的电路(如，电路112)或是另一外部装置(如，另一芯片、晶片、电路板、或封装板等等)作电性接触。
在一实施例中，接触阻挡层1310由金属或金属合金所构成，例如Ni、AuSu、或Au等等，并采用无电电镀(electroless plating)技术。然而，也可采用其他的方法及技术。接触阻挡层1310的材料选择上必须能够加强导电部件710与外部装置上的接触部件之间的黏着性。须注意的是导电部件710与接触阻挡层1310共同构成接触接垫，其上可连接其他装置，例如芯片、晶片、或基底等等。
图14示出根据本发明实施例的排置接触接垫1410与重布线1412的平面示意图，而图1至图13为沿图14中A-A线的剖面示意图。第二隔离层1010作为保护(passivation)层并覆盖露出接触接垫1410(如，接触阻挡层1310及其下方的导电部件710)以外的基底背侧。第二隔离层1010形成于重布线1412(以虚线示出)上方。
可以理解的是上述实施例容许可同时形成接触电及重布线。重布线的使用容许在不同脚位及技术中使用相同的设计。具有渐细侧壁的导电凸块也在晶片和/或芯片堆叠工艺中提供较大的接合界面。
图15至图17示出根据本发明实施例的将上述关于图1至图14的结构接合至另一结构。特别的是一基底1510，其具有上金属接点1512及连接部件1514。举例而言，连接部件1514可为锡球(solder ball)。通过对准连接部件1514与接触接垫1410以及施加压力和/或热，以将基底1510贴附于半导体基底110，使连接部件1514黏附于接触阻挡层1310而形成电性连接，如图16所示。由于接触阻挡层1310与导电部件710具有渐细外形，因此可使接合界面具有较大的润湿(wetting)表面，进而形成较佳的电性连接以及提供额外结构上的支撑。
请参照图17，可去除临时的承载基板130，使半导体基底110的电路侧上的导电凸块128可接合至另一芯片、晶片、基底、或板子等等。之后，可进行适用于特定应用的其他后段(back-end-of-line)工艺。举例而言，在堆叠的芯片之间注入填充材料、形成封胶(encapsulant)、及进行切割(singulation)工艺以形成各自的堆叠芯片封装等等。然而，须注意的是本发明实施例可使用于诸多不同的情况。举例而言，本发明实施例可使用于芯片对芯片(die-to-die)接合结构配置、芯片对晶片(die-to-wafer)接合结构配置、或晶片对晶片(wafer-to-wafer)接合结构配置。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中的普通技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。

Claims (15)

1.一种半导体装置，包括：
一第一半导体基底；
多个硅通孔电极，延伸穿过该第一半导体基底，且所述多个硅通孔电极突出于该第一半导体基底的一背侧；
一第一隔离层，位于相邻的所述多个硅通孔电极之间该第一半导体基底的该背侧，且该第一隔离层未延伸超过所述多个突出的硅通孔电极；
一导电部件，具有一渐细侧壁且电性耦接至所述多个硅通孔电极中的至少一个；以及
一第二隔离层，位于该第一隔离层上以及一部分的该导电部件上。
2.如权利要求1所述的半导体装置，其中该导电部件包括一重布线，而该第二隔离层位于至少一部分的该重布线上。
3.如权利要求2所述的半导体装置，其中该第一隔离层的材料不同于该第二隔离层的材料。
4.如权利要求1所述的半导体装置，还包括一接触阻挡层，位于至少一部分的该导电部件上。
5.如权利要求1所述的半导体装置，还包括一衬层，沿着所述多个硅通孔电极的侧壁，且该衬层未延伸超过该第一隔离层的一上表面。
6.如权利要求1所述的半导体装置，还包括：
一接触阻挡层，位于该导电部件上；
一第二半导体基底，具有一上金属接点；以及
一导电连接部件，夹设于该接触阻挡层与该上金属接点之间，且向下延伸至该导电部件的该渐细侧壁。
7.一种半导体装置的制造方法，包括：
提供一第一半导体基底，该第一半导体基底具有一硅通孔电极自该第一半导体基底的一第一侧延伸于其内，
在该第一半导体基底的一第二侧露出该硅通孔电极；
沿着该第一半导体基底的该第二侧形成一第一隔离层，且使该硅通孔电极露出；
在该硅通孔电极上形成具有一渐细侧壁的一导电部件；
在该第一隔离层上形成一第二隔离层，其中该第一隔离层的材料不同于该第二隔离层的材料；以及
在该导电部件的至少一部分上形成一接触阻挡层。
8.如权利要求7所述的半导体装置的制造方法，其中形成该导电部件包括使用具有凹口的掩模图案层作为形成该导电部件的模具。
9.如权利要求7所述的半导体装置的制造方法，其中露出该硅通孔电极包括蚀刻该第一半导体基底至低于该硅通孔电极的一表面，使该硅通孔电极突出于该第一半导体基底。
10.如权利要求7所述的半导体装置的制造方法，其中该硅通孔电极突出于该第一隔离层。
11.如权利要求7所述的半导体装置的制造方法，其中形成该导电部件包括：
在该第一隔离层及该硅通孔电极上方形成一晶种层；
在该晶种层上形成一掩模图案层，该掩模图案层具有多个凹口而露出位于该硅通孔电极上方的该晶种层；
在该晶种层的露出部分上形成一金属接垫；
去除该掩模图案层；以及
去除未被该金属接垫覆盖的该晶种层。
12.一种半导体装置的制造方法，包括：
提供一第一半导体基底，其具有多个硅通孔电极自该第一半导体基底的一电路侧延伸至该第一半导体基底的一背侧以及位于该背侧上的每一硅通孔电极上具有渐细侧壁的一导电接垫，且该第一半导体基底的该背侧具有一第一隔离层以及位于该第一隔离层上的一第二隔离层；
提供一第二半导体基底，其具有多个上接触点；以及
将该第一半导体基底接合至该第二半导体基底，使该第二半导体基底的每一上接触点电性耦接至该第一半导体基底上对应的所述导电接垫。
13.如权利要求12所述的半导体装置的制造方法，其中所述导电接垫中至少有一些包括一重布线。
14.如权利要求13所述的半导体装置的制造方法，其中该重布线位于该第一隔离层与该第二隔离层之间。
15.如权利要求12所述的半导体装置的制造方法，其中至少通过一金属凸块来进行该第一半导体基底与该第二半导体基底的接合。
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