CN102315198A - 具有对准标记的结构及堆叠装置的制造方法 - Google Patents
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Abstract
本发明揭示一种具有对准标记的结构及堆叠装置的制造方法,该结构包括:一基底,具有一第一区及一第二区。一基底通孔电极(through substrate via,TSV),位于基底内且穿过基底的第一区。一隔离层,位于基底的第二区,隔离层具有一凹口。一导电材料,位于隔离层上并顺应凹口内的隔离层,隔离层设置于导电材料与基底之间。本发明可防止对准标记内金属的扩散。
Description
技术领域
本发明涉及一种半导体工艺及其所形成的结构,特别是涉及一种对准标记(alignment mark)制造方法及其所形成的结构。
背景技术
在半导体工艺中,结构及装置的制造通常包括依序将一层材料或材料组成形成于另一层上方。这些膜层通常利用微影技术进行蚀刻或掺杂,以控制这些被蚀刻或掺杂的区域。举例来说,晶体管的源极/漏极的制做可包括在半导体基底上形成一光致抗蚀剂层,其中形成了源极/漏极区。对光致抗蚀剂层进行曝光,使得位于源极/漏极区上方的光致抗蚀剂层被除去。利用光致抗蚀剂层对半导体层进行掺杂,以防止未曝光区受到掺杂。再者,源极/漏极区的接触窗(contact)可包括:在半导体基底上沉积绝缘层;在绝缘层上形成光致抗蚀剂层;对光致抗蚀剂层进行曝光,以去除位于源极/漏极区上方的光致抗蚀剂层;利用光致抗蚀剂层作为掩模,以蚀刻绝缘层;以及沉积金属。
整合利用微影技术形成的装置取决于从一层到另一层中特征部件(features)可适当的对准,在上述范例中,接触窗必须对准于源极/漏极区。膜层之间的误对准(misalignment)会阻碍装置的操作。
半导体工艺领域中已发展出对准标记,使膜层之间微影工艺的对准具有更高的精确性。对准标记容许晶片进行工艺时的定位测量。依据该测量,步进机(stepper)可移动或修正晶片位置,以协助微影工艺获得更佳的对准。
发明内容
为克服上述现有技术的缺陷,在本发明一实施例中,一种具有对准标记的结构,包括:一基底,具有一第一区及一第二区;一基底通孔电极,位于基底内且穿过基底的第一区;一隔离层,位于基底的第二区,隔离层具有一凹口;以及一导电材料,位于隔离层上并顺应凹口内的隔离层,隔离层设置于导电材料与基底之间。
在本发明另一实施例中,一种具有对准标记的结构,包括:一基底,包括一基底通孔电极,基底通孔电极自基底的一前表面延伸至基底的一背表面;一隔离层,位于基底的背表面,隔离层具有一凹穴;以及一导体,位于凹穴内并顺应凹穴内的隔离层,隔离层设置于导体与基底之间。
在本发明又一实施例中,一种堆叠装置的制造方法,包括:提供一基底,其具有一基底通孔电极突出于基底的一背侧;于基底的背侧上形成一隔离层,隔离层具有一凹口;以及于凹口内顺应形成一导电层,隔离层设置于导电层与基底之间。
上述实施例可防止对准标记内金属的扩散。同样地,上述实施例的方法及结构可增加工艺的产能。再者,由于工艺的改善(例如使用低温工艺),因此可缓和薄化基底内的应力及应变。
附图说明
图1A至图1H示出根据本发明实施例的用于堆叠装置的对准标记制造方法。
图2示出经由图1A至图1H的方法所形成具有对准标记的结构。
图3A至图3H示出根据本发明另一实施例的用于堆叠装置的基底上的对准标记制造方法。
图4A至图4F示出根据本发明又另一实施例的对准标记制造方法。
图5示出经由图3A至图3H或图4A至图4F的方法所形成具有对准标记的结构。
其中,附图标记说明如下:
100、200~基底;
102、202~基底通孔电极;
104、204~金属化层;
106、206~内连结构;
108、208~导电凸块;
110、210~粘着层;
112、212~承载板;
114、124、218、220、230~光致抗蚀剂层;
116、118、222、224、232、234~开口;
120、214~第一隔离层;
122、216~第二隔离层;
126、236~第一金属层;
128、238~第二金属层;
130、240~对准标记。
具体实施方式
以下说明本发明实施例的制作与使用。然而,可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明,并非用以局限本发明的范围。
以下说明本发明实施例的一特定背景,即在堆叠装置的芯片进行工艺处理期间所形成的对准标记。然而,上述实施例也可应用于转接板(interposer)或是在工艺期间使用对准标记的另一结构。
图1A至图1H出根据本发明实施例的用于堆叠装置的对准标记制造方法。图2示出由图1A至图1H的方法所形成的结构。该方法中所述的任何顺序仅为了清晰的说明,而方法的步骤可在任何逻辑进展中进行。
图1A示出工艺中间阶段(例如,进行前侧工艺之后)中的一基底100,例如一堆叠装置的芯片(die)。特别的是此时的工艺中,基底100内已形成了基底通孔电极(TSV)102、一或多个具有内连结构106的金属化层104已形成于基底100上,且形成了导电凸块(bump)108而电性耦接至内连结构106。基底100可为任何适当的材料,例如硅。基底通孔电极102可包括一衬层(liner layer)、一扩散阻挡层、一粘着层、一隔离层等等并且填有一导电材料。举例来说,衬层可为,氮化硅、氧化硅、高分子材料及/或其组合等等。扩散阻挡层可包括一或多层的TaN、Ta、TiN、Ti、CoW等等,而导电材料可包括由电化学电镀工艺所形成的铜、钨、铝、银及/或其组合等等。金属化层104、内连结构106及导电凸块108可为任何可接受的材料且由适当的工艺所形成,例如公知的后段(back end of the line,BEOL)工艺。
再者,基底100前侧经由粘着层110而贴附于一承载板112以进行背侧工艺。一般而言,承载板112在后续工艺期间提供暂时性的机械及结构上的支撑。在上述方式中,可降低或防止基底100受损。举例来说,承载板112可包括玻璃、氧化硅、氧化铝等等。粘着层110可为任何适当的粘着剂,例如紫外光固化胶(UV胶),其暴露于紫外光时会失去粘性。需注意的是标号104至112并未明确地标示于图1B至图1H及图2中。然而,对应于这些标号的特征部件示出于这些图中。未标示这些标号仅是为了让图式更为清晰。
请参照图1B,其示出图1A的结构在基底100进行薄化(thinned)及向下凹陷(recessed)之后露出于基底100背侧的基底通孔电极102。薄化及向下凹陷可使基底100形成一薄基底,其厚度近似20微米至200微米。可利用平坦化工艺、蚀刻工艺及/或其组合来进行薄化及向下凹陷工艺。举例来说,初始可进行平坦化工艺,例如化学机械研磨(chemical mechanical polishing,CMP),以初步露出基底通孔电极102的上表面。之后,可进行一或多道的蚀刻工艺,其对于基底通孔电极102的材料与基底100之间具有高蚀刻选择比,以留下突出于基底100背侧的基底通孔电极102。
图1C示出在基底100背侧上形成光致抗蚀剂层114。光致抗蚀剂层114的厚度可大于基底通孔电极102突出部位的高度。光致抗蚀剂层114内具有开口116。开口116可利用微影技术而形成,例如利用微影掩模,对欲形成开口116处的光致抗蚀剂层114进行曝光。在形成开口116之后,进行蚀刻工艺,例如异向性(anisotropic)蚀刻,以形成凹入基底100背侧表面下方的开口118,如图1D所示。图1E示出对图1D的结构进行灰化(ash/flash)工艺之后,而去除了光致抗蚀剂层114。
图1F示出在图1E的结构上形成第一隔离层120及第二隔离层122。第一及第二隔离层120及122可包括氮化硅、氧化硅、碳化硅、氮氧化硅、氧化物、高分子材料及/或其组合等等。第一及第二隔离层120及122可为单一层或是实质上由相同或不同材料所组成的多层结构。在图1F的范例中,第一隔离层120为氮化硅,而第二隔离层122为氧化硅。第一及第二隔离层120及122可使用适当的沉积技术而形成,例如化学气相沉积(chemical vapordeposition,CVD)或是低温CVD工艺。如图1F所示,第一及第二隔离层120及122两者形成于开口118内露出的基底100上表面上且顺应于这些露出的表面。
图1G示出在第二隔离层122上方形成一光致抗蚀剂层124。可对光致抗蚀剂层124进行图案化,例如对光致抗蚀剂层124进行曝光,以容许进行蚀刻工艺时,去除涂覆于基底通孔电极102突出部位的第一及第二隔离层120及122。接着,对第一及第二隔离层120及122进行蚀刻,例如干蚀刻,以容许基底通孔电极102自第一及第二隔离层120及122下方露出,如图1H所示。蚀刻工艺所使用的蚀刻剂对于基底通孔电极102与第一及第二隔离层120及122之间具有高蚀刻选择比,图1H更进一步示出进行灰化工艺之后,去除了光致抗蚀剂层124的结构。
图2示出经由图1A至图1H的方法所形成具有对准标记130的结构。如图2所示,图1H的结构更包括了第一金属层126及第二金属层128。第一金属层126可为钛(Ti)、氮化钛(TiN)、钛钨(TiW)、氮化硅钛(TiSiN)、钽(Ta)、氮化钽(TaN)、氮化硅钽(TaSiN)、钨(W)、氮化钨(W2N)、氮化硅钨(WSiN)及/或其组合等等。而第二金属层128可为铜等。第一及第二金属层126及128可借由适当的沉积技术而形成,例如物理气相沉积(physical vapor deposition,PVD)、CVD或原子层沉积(atomic layerdeposition,ALD)。形成于开口118内的第一及第二金属层126及128连同设置于第一金属层126与基底100之间的第一及第二隔离层120及122,构成了位于基底100背侧的对准标记130。任何本领域技术人员可轻易理解在后续工艺步骤中(例如,在基底通孔电极102上形成铜柱体之后)可去除部分的第一及第二金属层126及128,例如位于基底通孔电极102之间的部分,以避免基底通孔电极102发生短路。
图3A至图3H示出根据本发明另一实施例的用于堆叠装置的基底上的对准标记制造方法,而图4A至图4F示出根据本发明又另一实施例的用于堆叠装置的对准标记制造方法。图5示出由上述方法所形成的结构。方法中所述的任何顺序仅为了清晰的说明,而方法的步骤可在任何逻辑进展中进行。
首先说明图3A至图3H所示的方法。请参照图3A,工艺中间阶段(例如,进行前侧工艺之后)中的一基底200。特别的是此时的工艺中,基底200内已形成了基底通孔电极(TSV)202、一或多个具有内连结构206的金属化层204已形成于基底200上,且形成了导电凸块208而电性耦接至内连结构206。基底200可为任何适当的材料,例如硅。基底通孔电极202可包括一衬层、一扩散阻挡层、一粘着层等等并且填有一导电材料。举例来说,衬层可为,氮化硅、氧化硅、高分子材料及/或其组合等等。扩散阻挡层可包括一或多层的TaN、Ta、TiN、Ti、CoW等等,而导电材料可包括由电化学电镀工艺所形成的铜、钨、铝、银及/或其组合等等。金属化层204、内连结构206及导电凸块208可为任何可接受的材料且由适当的工艺所形成,例如公知的后段(BEOL)工艺。
再者,基底200前侧经由粘着层210而贴附于一承载板212以进行背侧工艺。一般而言,承载板212在后续工艺期间提供暂时性的机械及结构上的支撑。在上述方式中,可降低或防止基底200受损。举例来说,承载板212可包括玻璃、氧化硅、氧化铝等等。粘着层210可为任何适当的粘着剂,例如紫外光固化胶(UV胶),其暴露于紫外光时会失去粘性。需注意的是标号204至212并未明确地标示于图3B至图3H及图5中。然而,对应于这些标号的特征部件示出于这些图中。未标示这些标号仅是为了让图式更为清晰。
请参照图3B,其示出图3A的结构在基底100进行薄化及向下凹陷之后露出于基底200背侧的基底通孔电极202。薄化及向下凹陷可使基底200形成一薄基底,其厚度近似20微米至200微米。可利用平坦化工艺、蚀刻工艺及/或其组合来进行薄化及向下凹陷工艺。举例来说,初始可进行平坦化工艺,例如化学机械研磨(CMP),以初步露出基底通孔电极202的上表面。之后,可进行一或多道的蚀刻工艺,其对于基底通孔电极202的材料与基底200之间具有高蚀刻选择比,以留下突出于基底200背侧的基底通孔电极202。
图3C示出在图3B的结构上形成第一隔离层214及第二隔离层216。第一隔离层214形成于基底200背侧上,而第二隔离层216形成于第一隔离层214上。第一及第二隔离层214及216可包括氮化硅、氧化硅、碳化硅、氮氧化硅、氧化物、高分子材料及/或其组合等等。第一及第二隔离层214及216可为单一层或是实质上由相同或不同材料所组成的多层结构。在图3C的范例中,第一隔离层214为氮化硅,而第二隔离层216为氧化硅。第一及第二隔离层214及216可使用适当的沉积技术而形成,例如化学气相沉积(CVD)或是低温CVD工艺。
图3D示出在第二隔离层216上形成光致抗蚀剂层218。可对光致抗蚀剂层218进行图案化,例如对光致抗蚀剂层218进行曝光,以容许进行蚀刻工艺时,去除涂覆于基底通孔电极202突出部位的第一及第二隔离层214及216。接着,对第一及第二隔离层214及216进行蚀刻,例如干蚀刻,以容许基底通孔电极202自第一及第二隔离层214及216下方露出,如图3E所示。蚀刻工艺所使用的蚀刻剂对于基底通孔电极202与第一及第二隔离层214及216之间具有高蚀刻选择比,图3E更进一步示出进行灰化工艺之后,去除了光致抗蚀剂层218的结构。
图3F示出在第二隔离层216上形成光致抗蚀剂层220。光致抗蚀剂层220内具有开口222。开口222可利用微影技术而形成,例如利用微影掩模,对欲形成开口222处的光致抗蚀剂层220进行曝光。在形成开口222之后,进行异向性蚀刻工艺,以形成凹入第二隔离层216的开口224,如图3G所示。开口224可进一步凹入第一隔离层214内,但未及于或低于基底200背侧表面。图3H示出对图3G的结构进行灰化工艺之后,而去除了光致抗蚀剂层220。
现在说明图4A至图4F所示的方法。图4A至图4C所进行的方法相同于前述对应于图3A至图3C所进行的方法。因此,为了简化说明,在此不再赘述这些步骤。再者,图4A至图4C中相同或相似于图3A至图3C的部件使用相同的标号。
图4D示出在第二隔离层216上形成光致抗蚀剂层230。光致抗蚀剂层230内具有开口232。开口232可利用微影技术而形成,例如利用微影掩模,对欲形成开口222处的光致抗蚀剂层230进行曝光。接着蚀刻第二隔离层216,例如进行异向性蚀刻工艺,以形成凹入第二隔离层216的开口234,如图4E所示。蚀刻工艺所使用的蚀刻剂对于第二隔离层216与第一隔离层214所使用的材料之间具有高蚀刻选择比。之后,可利用平坦化工艺,例如CMP,去除基底通孔电极202上方的第一及第二隔离层214及216,以容许基底通孔电极202露出上表面,如图4F所示。图4F进一步示出进行灰化工艺之后,去除光致抗蚀剂层230的结构。
图5示出经由图3A至图3H或图4A至图4F的方法所形成具有对准标记240的结构。如图5所示,图3H或图4F的结构更包括了第一金属层236及第二金属层238。第一金属层236可为Ti、TiN、TiW、TiSiN、Ta、TaN、TaSiN、W、W2N、WSiN及/或其组合等等。而第二金属层238可为铜等。第一及第二金属层236及238可借由适当的沉积技术而形成,例如PVD、CVD或ALD。形成于开口234内的第一及第二金属层236及238连同设置于第一金属层236与基底200之间的第二隔离层216,构成了位于基底200背侧的对准标记240。任何本领域技术人员可轻易理解在后续工艺步骤中(例如,在基底通孔电极202上形成铜柱体之后)可去除部分的第一及第二金属层236及238,例如位于基底通孔电极202之间的部分,以避免基底通孔电极202发生短路。
上述实施例可防止对准标记内金属的扩散。隔离层可形成一阻挡层,以防止金属,例如铜,扩散进入上述实施例的基底内。透过预防扩散,形成于基底内的装置及结构很少会发生由于对准标记内金属扩散所造成的短路或其他问题而导致无法操作的情形。
同样地,上述实施例的方法及结构可增加工艺的产能。再者,由于工艺的改善(例如使用低温工艺),因此可缓和薄化基底内的应力及应变。
虽然本发明已以优选实施例揭示如上,然而其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作各种更动、替代与润饰。再者,本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤,任何本领域技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤,只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此,本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。
Claims (10)
1.一种具有对准标记的结构,包括:
一基底,具有一第一区及一第二区;
一基底通孔电极,位于该基底内且穿过该基底的该第一区;
一隔离层,位于该基底的该第二区,该隔离层具有一凹口;以及
一导电材料,位于该隔离层上并顺应该凹口内的该隔离层,该隔离层设置于该导电材料与该基底之间。
2.如权利要求1所述的具有对准标记的结构,其中该凹口延伸进入该基底内或未延伸进入该基底内。
3.如权利要求1所述的具有对准标记的结构,其中该隔离层包括一第一次层及位于其上的一第二次层,该第一次层的组成不同于该第二次层,且其中该凹口仅延伸穿过该第二次层。
4.一种具有对准标记的结构,包括:
一基底,包括一基底通孔电极,该基底通孔电极自该基底的一前表面延伸至该基底的一背表面;
一隔离层,位于该基底的该背表面,该隔离层具有一凹穴;以及
一导体,位于该凹穴内并顺应该凹穴内的该隔离层,该隔离层设置于该导体与该基底之间。
5.如权利要求4所述的具有对准标记的结构,该隔离层包括一第一次层及位于其上的一第二次层,而该凹穴为位于该第二次层内的一开口,且该第一次层设置于该导体与该基底之间。
6.如权利要求4所述的具有对准标记的结构,其中该凹穴包括延伸进入该基底而位于该基底的该背表面内的一凹口,该隔离层顺应该凹口。
7.一种堆叠装置的制造方法,包括:
提供一基底,其具有一基底通孔电极突出于该基底的一背侧;
于该基底的该背侧上形成一隔离层,该隔离层具有一凹口;以及
于该凹口内顺应形成一导电层,该隔离层设置于该导电层与该基底之间。
8.如权利要求7所述的堆叠装置的制造方法,其中形成该隔离层包括在该基底的该背侧内形成一开口以及形成顺应该开口的该隔离层,以构成该凹口。
9.如权利要求7所述的堆叠装置的制造方法,其中形成该隔离层包括在该隔离层内形成一开口,已构成该凹口,该开口未到达该基底的该背侧。
10.如权利要求7所述的堆叠装置的制造方法,其中形成该隔离层包括形成一第一次层及位于其上的一第二次层,而该第一及该第二次层具有不同的材料。
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Cited By (4)
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CN104064482A (zh) * | 2013-03-22 | 2014-09-24 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
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CN107527893A (zh) * | 2016-06-22 | 2017-12-29 | 南亚科技股份有限公司 | 半导体芯片与其多芯片封装及其制造方法 |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8513119B2 (en) | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US20100171197A1 (en) | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
US8466059B2 (en) | 2010-03-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer interconnect structure for stacked dies |
US8466553B2 (en) * | 2010-10-12 | 2013-06-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package having the same |
JP6053256B2 (ja) | 2011-03-25 | 2016-12-27 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体チップ及びその製造方法、並びに半導体装置 |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
US8525168B2 (en) * | 2011-07-11 | 2013-09-03 | International Business Machines Corporation | Integrated circuit (IC) test probe |
KR101840846B1 (ko) * | 2012-02-15 | 2018-03-21 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US8940637B2 (en) * | 2012-07-05 | 2015-01-27 | Globalfoundries Singapore Pte. Ltd. | Method for forming through silicon via with wafer backside protection |
KR102018885B1 (ko) * | 2012-12-20 | 2019-09-05 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US8860228B2 (en) * | 2012-12-26 | 2014-10-14 | Stmicroelectronics Pte. Ltd. | Electronic device including electrically conductive vias having different cross-sectional areas and related methods |
TWI517328B (zh) * | 2013-03-07 | 2016-01-11 | 矽品精密工業股份有限公司 | 半導體裝置 |
US20140264848A1 (en) * | 2013-03-14 | 2014-09-18 | SK Hynix Inc. | Semiconductor package and method for fabricating the same |
US8884427B2 (en) | 2013-03-14 | 2014-11-11 | Invensas Corporation | Low CTE interposer without TSV structure |
US9059111B2 (en) * | 2013-04-11 | 2015-06-16 | International Business Machines Corporation | Reliable back-side-metal structure |
KR20150048388A (ko) * | 2013-10-28 | 2015-05-07 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US9478509B2 (en) * | 2014-03-06 | 2016-10-25 | GlobalFoundries, Inc. | Mechanically anchored backside C4 pad |
US9318452B2 (en) | 2014-03-21 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
US9735129B2 (en) * | 2014-03-21 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
KR102165266B1 (ko) * | 2014-04-03 | 2020-10-13 | 삼성전자 주식회사 | 반도체 소자 및 반도체 패키지 |
KR20170037705A (ko) | 2015-09-25 | 2017-04-05 | 삼성전자주식회사 | 입력 신호들을 랭크별로 제어하는 메모리 버퍼를 갖는 메모리 모듈 |
KR20180014362A (ko) | 2016-07-29 | 2018-02-08 | 삼성전자주식회사 | 회로 기판 및 반도체 패키지 |
US10627720B2 (en) * | 2017-08-18 | 2020-04-21 | Globalfoundries Inc. | Overlay mark structures |
US20190392879A1 (en) * | 2018-06-26 | 2019-12-26 | Spin Memory, Inc. | MAGNETIC MEMORY ELEMENT HAVING MgO ISOLATION LAYER |
US11694968B2 (en) * | 2020-11-13 | 2023-07-04 | Samsung Electronics Co., Ltd | Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate |
US11798888B2 (en) * | 2020-12-11 | 2023-10-24 | Sj Semiconductor (Jiangyin) Corporation | Chip packaging structure and method for preparing same |
US11908836B2 (en) | 2021-01-13 | 2024-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of manufacturing semiconductor package |
KR20230034747A (ko) * | 2021-09-03 | 2023-03-10 | 삼성전자주식회사 | 웨이퍼 구조체 및 반도체 소자 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040169255A1 (en) * | 2003-02-28 | 2004-09-02 | Masahiro Kiyotoshi | Semiconductor device and method of manufacturing same |
CN101414589A (zh) * | 2007-10-17 | 2009-04-22 | 台湾积体电路制造股份有限公司 | 集成电路结构及形成该集成电路结构的方法 |
US20090166811A1 (en) * | 2007-12-27 | 2009-07-02 | Shinko Electric Industries Co., Ltd | Semiconductor device and manufacturing method thereof |
US20100025825A1 (en) * | 2008-08-04 | 2010-02-04 | Degraw Danielle L | Metal adhesion by induced surface roughness |
CN101719484A (zh) * | 2008-10-09 | 2010-06-02 | 台湾积体电路制造股份有限公司 | 具有再分布线的tsv的背连接 |
CN101752336A (zh) * | 2008-12-10 | 2010-06-23 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211239A (ja) | 1991-09-12 | 1993-08-20 | Texas Instr Inc <Ti> | 集積回路相互接続構造とそれを形成する方法 |
DE4314907C1 (de) | 1993-05-05 | 1994-08-25 | Siemens Ag | Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen |
US5391917A (en) | 1993-05-10 | 1995-02-21 | International Business Machines Corporation | Multiprocessor module packaging |
JP2595885B2 (ja) | 1993-11-18 | 1997-04-02 | 日本電気株式会社 | 半導体装置およびその製造方法 |
EP0948808A4 (en) | 1996-10-29 | 2000-05-10 | Trusi Technologies Llc | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF |
US6882030B2 (en) | 1996-10-29 | 2005-04-19 | Tru-Si Technologies, Inc. | Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate |
US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
US5783490A (en) | 1997-04-21 | 1998-07-21 | Vanguard International Semiconductor Corporation | Photolithography alignment mark and manufacturing method |
US5972793A (en) | 1997-06-09 | 1999-10-26 | Vanguard International Semiconductor Corporation | Photolithography alignment mark manufacturing process in tungsten CMP metallization |
US6337522B1 (en) * | 1997-07-10 | 2002-01-08 | International Business Machines Corporation | Structure employing electrically conductive adhesives |
US5966613A (en) | 1997-09-08 | 1999-10-12 | Lsi Corporation | Consistent alignment mark profiles on semiconductor wafers using metal organic chemical vapor deposition titanium nitride protective |
US6037822A (en) | 1997-09-30 | 2000-03-14 | Intel Corporation | Method and apparatus for distributing a clock on the silicon backside of an integrated circuit |
US5998292A (en) | 1997-11-12 | 1999-12-07 | International Business Machines Corporation | Method for making three dimensional circuit integration |
JP3532788B2 (ja) | 1999-04-13 | 2004-05-31 | 唯知 須賀 | 半導体装置及びその製造方法 |
JP4037561B2 (ja) | 1999-06-28 | 2008-01-23 | 株式会社東芝 | 半導体装置の製造方法 |
US6322903B1 (en) | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
US6444576B1 (en) | 2000-06-16 | 2002-09-03 | Chartered Semiconductor Manufacturing, Ltd. | Three dimensional IC package module |
US6780775B2 (en) | 2001-01-24 | 2004-08-24 | Infineon Technologies Ag | Design of lithography alignment and overlay measurement marks on CMP finished damascene surface |
US6383888B1 (en) | 2001-04-18 | 2002-05-07 | Advanced Micro Devices, Inc. | Method and apparatus for selecting wafer alignment marks based on film thickness variation |
US6878615B2 (en) * | 2001-05-24 | 2005-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to solve via poisoning for porous low-k dielectric |
JP4680424B2 (ja) | 2001-06-01 | 2011-05-11 | Okiセミコンダクタ株式会社 | 重ね合わせ位置検出マークの製造方法 |
US6599778B2 (en) | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
EP1472730A4 (en) | 2002-01-16 | 2010-04-14 | Mann Alfred E Found Scient Res | HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE |
US6762076B2 (en) | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
JP2003257970A (ja) * | 2002-02-27 | 2003-09-12 | Nec Electronics Corp | 半導体装置及びその配線構造 |
CN1276306C (zh) | 2002-05-14 | 2006-09-20 | 株式会社东芝 | 加工方法及半导体器件的制造方法 |
US6800930B2 (en) | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
US7030481B2 (en) | 2002-12-09 | 2006-04-18 | Internation Business Machines Corporation | High density chip carrier with integrated passive devices |
JP4072677B2 (ja) | 2003-01-15 | 2008-04-09 | セイコーエプソン株式会社 | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
US6621119B1 (en) * | 2003-02-04 | 2003-09-16 | Ching-Yuan Wu | Isolated stack-gate flash cell structure and its contactless flash memory arrays |
US6803291B1 (en) | 2003-03-20 | 2004-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd | Method to preserve alignment mark optical integrity |
US6841883B1 (en) | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
US6924551B2 (en) | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US7241668B2 (en) | 2003-06-24 | 2007-07-10 | International Business Machines Corporation | Planar magnetic tunnel junction substrate having recessed alignment marks |
US7111149B2 (en) | 2003-07-07 | 2006-09-19 | Intel Corporation | Method and apparatus for generating a device ID for stacked devices |
TWI251313B (en) | 2003-09-26 | 2006-03-11 | Seiko Epson Corp | Intermediate chip module, semiconductor device, circuit board, and electronic device |
US7335972B2 (en) | 2003-11-13 | 2008-02-26 | Sandia Corporation | Heterogeneously integrated microsystem-on-a-chip |
US7060601B2 (en) | 2003-12-17 | 2006-06-13 | Tru-Si Technologies, Inc. | Packaging substrates for integrated circuits and soldering methods |
US7049170B2 (en) | 2003-12-17 | 2006-05-23 | Tru-Si Technologies, Inc. | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
JP4467318B2 (ja) | 2004-01-28 | 2010-05-26 | Necエレクトロニクス株式会社 | 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法 |
JP4074862B2 (ja) * | 2004-03-24 | 2008-04-16 | ローム株式会社 | 半導体装置の製造方法、半導体装置、および半導体チップ |
JP4966487B2 (ja) * | 2004-09-29 | 2012-07-04 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
US7262495B2 (en) | 2004-10-07 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | 3D interconnect with protruding contacts |
US20060264021A1 (en) * | 2005-05-17 | 2006-11-23 | Intel Corporation | Offset solder bump method and apparatus |
US7297574B2 (en) | 2005-06-17 | 2007-11-20 | Infineon Technologies Ag | Multi-chip device and method for producing a multi-chip device |
US7902643B2 (en) * | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US8084854B2 (en) * | 2007-12-28 | 2011-12-27 | Micron Technology, Inc. | Pass-through 3D interconnect for microelectronic dies and associated systems and methods |
KR20100021856A (ko) | 2008-08-18 | 2010-02-26 | 삼성전자주식회사 | 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치 |
US8227295B2 (en) * | 2008-10-16 | 2012-07-24 | Texas Instruments Incorporated | IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV |
CN102197479A (zh) * | 2008-10-30 | 2011-09-21 | Nxp股份有限公司 | 具有金属膏的基板贯通过孔和重分布层 |
US7839163B2 (en) * | 2009-01-22 | 2010-11-23 | International Business Machines Corporation | Programmable through silicon via |
US8587121B2 (en) * | 2010-03-24 | 2013-11-19 | International Business Machines Corporation | Backside dummy plugs for 3D integration |
-
2010
- 2010-06-30 US US12/827,563 patent/US8896136B2/en active Active
- 2010-07-22 SG SG2010053197A patent/SG177042A1/en unknown
- 2010-11-24 TW TW099140503A patent/TWI450376B/zh active
- 2010-12-15 CN CN201010597701XA patent/CN102315198B/zh active Active
-
2014
- 2014-11-14 US US14/542,317 patent/US9478480B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040169255A1 (en) * | 2003-02-28 | 2004-09-02 | Masahiro Kiyotoshi | Semiconductor device and method of manufacturing same |
CN101414589A (zh) * | 2007-10-17 | 2009-04-22 | 台湾积体电路制造股份有限公司 | 集成电路结构及形成该集成电路结构的方法 |
US20090166811A1 (en) * | 2007-12-27 | 2009-07-02 | Shinko Electric Industries Co., Ltd | Semiconductor device and manufacturing method thereof |
US20100025825A1 (en) * | 2008-08-04 | 2010-02-04 | Degraw Danielle L | Metal adhesion by induced surface roughness |
CN101719484A (zh) * | 2008-10-09 | 2010-06-02 | 台湾积体电路制造股份有限公司 | 具有再分布线的tsv的背连接 |
CN101752336A (zh) * | 2008-12-10 | 2010-06-23 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104064482A (zh) * | 2013-03-22 | 2014-09-24 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
CN108878371A (zh) * | 2013-03-22 | 2018-11-23 | 瑞萨电子株式会社 | 半导体器件的制造方法 |
US10141295B2 (en) | 2013-03-22 | 2018-11-27 | Renesas Electronics Corporation | Method for manufacturing semiconductor device |
CN104465492A (zh) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | 穿透硅通孔结构的形成方法以及集成电路制造方法 |
CN104465492B (zh) * | 2013-09-23 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | 穿透硅通孔结构的形成方法以及集成电路制造方法 |
CN104733371A (zh) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔形成方法及半导体器件的对准结构 |
CN104733371B (zh) * | 2013-12-18 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔形成方法及半导体器件的对准结构 |
CN107527893A (zh) * | 2016-06-22 | 2017-12-29 | 南亚科技股份有限公司 | 半导体芯片与其多芯片封装及其制造方法 |
US10438887B2 (en) | 2016-06-22 | 2019-10-08 | Nanya Technology Corporation | Semiconductor chip and multi-chip package using thereof and method for manufacturing the same |
Also Published As
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US8896136B2 (en) | 2014-11-25 |
TW201201344A (en) | 2012-01-01 |
TWI450376B (zh) | 2014-08-21 |
SG177042A1 (en) | 2012-01-30 |
US20120001337A1 (en) | 2012-01-05 |
US20150069580A1 (en) | 2015-03-12 |
CN102315198B (zh) | 2013-09-11 |
US9478480B2 (en) | 2016-10-25 |
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