CN101719484A - 具有再分布线的tsv的背连接 - Google Patents

具有再分布线的tsv的背连接 Download PDF

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CN101719484A
CN101719484A CN200910150012A CN200910150012A CN101719484A CN 101719484 A CN101719484 A CN 101719484A CN 200910150012 A CN200910150012 A CN 200910150012A CN 200910150012 A CN200910150012 A CN 200910150012A CN 101719484 A CN101719484 A CN 101719484A
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rdl
integrated circuit
circuit structure
semiconductor substrate
liner
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CN101719484B (zh
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许国经
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

一种集成电路结构，该结构包括半导体衬底，其包括一个正面和一个背面。穿透该半导体衬底的穿透硅通孔(TSV)，且该穿透硅通孔(TSV)具有延伸到该半导体衬底背面的后端。再分布线(RDL)，其位于该半导体衬底的背面之上，并连接到该TSV的该后端。该集成电路进一步包括钝化层，该钝化层位于该RDL之上；位于该钝化层中的开口，其中该RDL的一部分通过该开口暴露；以及镍层，其位于该开口中并接触该RDL。

Description

具有再分布线的TSV的背连接
技术领域
本发明一般涉及集成电路结构，且更具体地，涉及穿透硅通孔，且更优选地，再具体而言涉及连接到穿透硅通孔的焊垫的形成。
背景技术
自从发明了集成电路，由于各种电子部件(即晶体管、二极管、电阻、电容等)的集成密度的不断改进，所以半导体产业经历了持续快速的增长。在大多数情况下，这种集成密度的改进来源于最小特征尺寸的一再削减，它允许更多的部件被集成到一个给定的芯片区域中。
这些集成的改进在性质上基本是二维(2D)的，因为被集成部件所占据的体积基本上位于半导体晶元的表面上。虽然光刻技术的显著改进已经致使2D集成电路构造的显著改进，但是对于二维制造而言，存在密度的物理局限。这些局限的其中一个是制造这些部件所需的最小尺寸。而且，当更多的器件集成到一个晶片中时，就需要更复杂的设计。
另一局限来源于由于器件数量的增加而导致的器件间互连的数量和长度的显著增加。当互连的数量和长度增加时，电路RC延迟和功耗也随之增加。
在致力于解决上述讨论的局限的努力中，常使用三维集成电路(3DIC)和堆叠管芯。因此，穿透硅通孔(TSV)应用于3DIC和堆叠管芯中，用来连接管芯。在这种情况下，TSV通常用于将管芯上的集成电路连接到晶片的背面。而且，TSV还用于提供短接地路径，来通过管芯的背面将集成电路接地，其可被接地金属膜覆盖。
图1说明了形成在芯片104中的传统TSV102。TSV102形成在硅衬底106中。通过金属层中的互连(金属线和通孔，未示出)，TSV102电连接到焊垫108，该焊垫108位于芯片104的正面。TSV102穿过衬底106的背面，以铜柱的形式暴露。当芯片104键合到另一芯片时，TSV102键合到另一芯片上的焊垫，其间具有或不具有焊料。这种设计具有缺陷。因为TSV的键合需要相对大的TSV之间的间距，所以限制了TSV的位置且需要TSV之间的距离足够大，以允许预留例如焊球的空间。因此需要新的背面结构。
发明内容
根据本发明的一个方面，提供一种集成电路结构，其包括包含了一个正面和一个背面的半导体衬底。导电通孔(其可以是穿透硅通孔(TSV))穿透半导体衬底，且具有延伸到该半导体衬底背面的后端。再分布线(RDL)位于该半导体衬底的背面之上，并连接到TSV的后端。该集成电路结构进一步包括在RDL上的钝化层；位于钝化层中的开口，其中RDL的一部分通过开口暴露；以及镍层，其位于开口中并接触RDL。
根据本发明的另一方面，提供一种集成电路结构，其包括包含了一个正面和一个背面的半导体衬底；且导电通孔(例如TSV)穿透半导体衬底。该TSV包括后端，其延伸超过半导体衬底的背面。RDL形成在半导体衬底的背面之上，且连接到TSV的后端，其中该RDL包括接触TSV的RDL带，且RDL衬垫的宽度大于该RDL带。RDL衬垫连接RDL带。钝化层形成在RDL之上。在钝化层中形成开口，其中RDL衬垫的中部通过开口暴露，且其中该钝化层覆盖RDL衬垫的边缘部分。镍层形成在开口中并接触RDL的中部，其中该镍层的厚度大于该钝化层的厚度。
本发明的优点包括改进了键合能力且增加了的堆叠管芯间的间隙。
附图说明
为了更全面的理解本发明及其优点，现在结合附图参考以下描述，其中：
图1说明了一种包括了穿透硅通孔(TSV)的传统集成电路结构，其中该TSV通过衬底的背面突出，且以铜柱的形式键合到另一芯片上的焊垫；以及
图2至8是本发明的一个实施例的制造过程中的中间步骤的顶视图和截面图。
具体实施方式
以下，详细讨论本发明的实施例的制造和应用。但是应当认识到，本发明的实施例提供了多种适用的创造性概念，其可以在多种具体情况下实施。所讨论的特定实施例仅仅是制造和应用本发明的特定方式的说明，且不限制本发明的范围。
提供一种连接到穿透硅通孔(TSV)的新型背面连接结构及其形成方法。说明了本发明的一个优选实施例的制造过程的中间步骤。讨论了该优选实施例的变型。贯穿各个附图和本发明的说明性实施例，相同的附图标记用于指代相同的元件。
参考图2，提供芯片2，其包括衬底10以及其中的集成电路(未示出)。衬底10优选是半导体衬底，例如体硅衬底，而其也可包括其他半导体材料，诸如III族、IV族和/或V族元素。诸如晶体管(未示出)的半导体器件可以形成在衬底10的正面处(图2中朝下的表面)。互连结构12包括形成于其中的金属线和通孔(未示出)，该互连结构12形成在衬底10之下且连接到半导体器件。金属线和通孔可由铜或铜合金形成，且可以利用众所周知的镶嵌工艺来形成。互连结构12可以包括公知的层间电介质(ILD)和金属间电介质(IMD)。焊垫14形成在芯片2的正表面，且突出超过芯片2的正表面的正面侧上(图2中朝下的一侧)。
TSV20形成在衬底10中，且从背面(图2中朝上的表面)延伸到正面(其上形成有源电路的表面)。在第一实施例中，如图2中所示，利用先通孔方法形成TSV20，且在互连结构12的形成之前形成TSV20。因此，TSV20仅延伸到用于覆盖有源器件的ILD，但未延伸进互连结构12中的IMD层。在可替换地实施例中，利用后通孔方法形成TSV20，且在互连结构12的形成之后形成TSV20。因此，TSV20穿透通过衬底10和互连结构12。绝缘层22形成在TSV20的侧壁上，且将TSV20与衬底10电绝缘。绝缘层22可由常用的介电材料形成，例如氮化硅、氧化硅(例如四乙基原硅酸盐(TEOS)氧化物)等。
TSV20通过衬底10的背面暴露。优选地，形成覆盖衬底10背面的背面绝缘层24。在一个示例性实施例中，背面绝缘层24的形成包括深腐蚀衬底10的背面，敷设形成背面绝缘层24，以及轻微实施化学机械抛光来移除直接位于TSV20之上的背面绝缘层24的部分。因此，TSV20通过背面绝缘层24中的开口而暴露。在可替换地实施例中，通过蚀刻来形成位于背面绝缘层24中的、通过其而暴露TSV20的开口。
参考图3，一个薄种子层26，其也可称为凸点下金属化层(UBM)，敷设形成在背面绝缘层24和TSV20上。UBM26的可用材料包括铜或铜合金。然而，也可包括其他金属，例如银、金、铝及其组合。在一个实施例中，利用溅射形成UBM26。在其他实施例中，可以使用物理气相沉积(PVD)或电镀。
图3还说明了掩模46的形成。在一个实施例中，掩模46是一个干膜，其可以包括有机材料，例如Ajinimoto膜(ABF膜)、预浸料、涂覆树脂的铜(RCC)等。可替换地，掩模46由光致抗蚀剂形成。接着，图案化掩模46以在掩模46中形成开口50，通过开口50暴露TSV20。
图4中，用金属材料选择性填充开口50，以在开口50中形成再分布线(RDL)52。在优选实施例中，填充材料包括铜或铜合金，而也可使用其他金属，例如铝、银、金及其组合。该形成方法优选包括电化学镀(ECP)、化学镀或其他常用的沉积方法，例如溅射、印刷和化学气相沉积(CVD)方法。接着移除掩模46。因此，暴露了位于掩模46之下的部分UBM26。
参考图5，通过快速蚀刻移除UBM26的暴露部分。剩余的RDL52可以包括RDL带(也称作再分布轨迹)521，其包括直接位于TSV20之上且与其连接的部分，以及与RDL带521连接的可选择地RDL衬垫522。可以在图7中观察到RDL52的顶视图。在图5和后续附图中，未示出UBM26，因为其典型地由与RDL52相类似的材料形成，且因此其看起来似乎与RDL52合并在一起。由于快速蚀刻，所以还移除了RDL52的一个薄层。然而，RDL52的移除部分相比其总厚度是微不足道的。
接着，如图6A所示，敷设形成钝化层56且图案化该钝化层56，以形成开口58。钝化层56可由氮化物、氧化物、聚酰亚胺等形成。通过钝化层56中的开口58暴露RDL衬垫522的一部分。优选地，开口58占据了RDL衬垫522的中心部分(请参照图7)。RDL带部分521仍然被钝化层56覆盖。可以认识到，一个芯片可以包括多个TSV20，如图6B中所示，其是芯片2的顶视图。在优选实施例中，贯穿芯片2的开口58的尺寸基本是统一的。开口58的统一尺寸致使用于键合多个TSV中的每一个所需的焊料的数量相同，这样就降低了冷接或无接头的可能性。
图7说明了钝化开口58和RDL52的顶部示意图。请注意，所说明的特征的尺寸没有按比例绘制。优选地，开口58具有小于RDL衬垫522的尺寸，并暴露RDL衬垫522的中心部分。在一个示例性实施例中，RDL带521具有约5μm和约15μm之间的宽度W1。RDL衬垫522具有约80μm到约100μm的宽度W2，而钝化开口58具有约70μm到约90μm的宽度W3。钝化开口58的顶视图可以是八角形、六角形、正方形或任何其他可适用的形状。
接着，如图8中所示，金属饰面60形成于开口58中。金属饰面60的形成方法包括ECP、化学镀等。在优选实施例中，金属饰面60包括直接形成于RDL衬垫522之上并与之接触的镍层62。可选地，诸如金层66或钯层64之上的金层66的其他层可以形成在镍层62之上。镍层62的厚度大于钝化层56的厚度，以便镍层62的顶表面高于钝化层56的顶表面。钯层64和金层66的形成进一步增加了金属饰面60的高度，以便芯片2(以及芯片2所在的相应的晶元)和另一芯片之间的间隙足够允许后续封装步骤中被填充的底层填料的流动。利用上文所讨论的金属饰面的形成，就无需在开口58中形成铜衬垫或在开口58中形成共熔焊垫，其中共熔焊垫可以包括由例如锡铅(Sn-Pb)合金形成的共熔焊料材料。
本发明的实施例具有几个有利地特点。通过直接在RDL上形成包括镍、金等的金属饰面，而不是形成铜或共熔键合，可以避免可能发生的铜氧化。因此，增强了键合(焊接)能力。而且，可以将镍直接形成为一个厚度，该厚度足以允许用于在后续封装步骤中将被填充的底层填料的流动的足够的间隙。
虽然详细描述了本发明及其优点，但应当理解的是，在不脱离由附加的权利要求所定义的本发明的范围和精神的情况下，在这里可以作出各种变化、替换和改造。而且，本申请的范围不限定在说明书中所描述的工艺、机械、制造和问题、手段、方法和步骤的组成的特定实施例中。作为本领域技术人员，将从本发明的公开内容中容易地理解到，根据本发明，可以使用与这里描述的相应实施例执行基本相同的功能或实现基本相同的结果的现有的或将来可以被进一步完善的工艺、机械、制造和问题、手段、方法和步骤的组成。因此，附加的权利要求涵盖了这些工艺、机械、制造和问题、手段、方法和步骤的组成的范围。而且，每个权利要求都构成一个单独的实施例，且不同权利要求和实施例的组合都限于本发明的范围之内。

Claims (13)

1.一种集成电路结构，包括：
半导体衬底，其包括一个正面和一个背面；
穿透该半导体衬底的导电通孔，该导电通孔包括延伸到该半导体衬底背面的后端；
再分布线(RDL)，其位于该半导体衬底的背面之上，并连接到该导电通孔的该后端；
钝化层，在该RDL之上，在该钝化层中具有开口且该RDL的一部分通过该开口暴露；以及
镍层，其位于该开口中并接触该RDL。
2.根据权利要求1的集成电路结构，其中该RDL包括RDL带以及RDL衬垫，该RDL带包括直接位于该导电通孔之上并与之接触的部分，该RDL衬垫具有大于该RDL带的宽度，该RDL衬垫连接该RDL带，且其中该开口仅暴露该RDL衬垫的中部。
3.根据权利要求1的集成电路结构，进一步包括位于该镍层之上的金层。
4.根据权利要求3的集成电路结构，进一步包括在该金层和该镍层之间并连接该金层和该镍层的钯层。
5.根据权利要求1的集成电路结构，其中该镍层包括一个顶表面，该顶表面高于该钝化层的顶表面。
6.根据权利要求1的集成电路结构，其中该集成电路结构没有位于该RDL之上并与之接触的衬垫，该衬垫以选自基本上由铜和共熔焊料构成的组中的一种材料形成。
7.根据权利要求1的集成电路结构，进一步包括：
多个穿透该半导体衬底的导电通孔；
多个位于该半导体衬底背面的RDL，其中多个该RDL中的每一个连接到该多个导电通孔中的其中一个的后端；
多个位于该钝化层中的开口，其中通过该多个开口中的一个暴露该多个RDL中每一个的一部分，且其中该多个开口具有基本上相同的尺寸；以及
镍层，形成在该多个开口的每一个中，且接触该多个RDL中的一个。
8.一种集成电路结构，该结构包括：
半导体衬底，其包括一个正面和一个背面；
穿透该半导体衬底的导电通孔，该导电通孔包括延伸超过该半导体衬底背面的后端；
再分布线(RDL)，其位于该半导体衬底的背面之上，并连接到该导电通孔的该后端；该RDL包括：
接触该导电通孔的RDL带；以及
RDL衬垫，该RDL衬垫的宽度大于该RDL带，其中该RDL衬垫连接该RDL带，
钝化层，其在该RDL之上；
在该钝化层中形成的开口，其中该RDL衬垫的中部通过该开口暴露，且其中该钝化层覆盖该RDL衬垫的边缘部分；以及
镍层，其形成在开口中并接触该RDL的该中部，其中该镍层的厚度大于该钝化层的厚度。
9.根据权利要求8的集成电路结构，其中该镍层包括顶表面，该顶表面高于该钝化层的顶表面。
10.根据权利要求8的集成电路结构，进一步包括在该镍层之上的金层。
11.根据权利要求10的集成电路结构，进一步包括在该金层和该镍层之间并连接该金层和该镍层的钯层。
12.根据权利要求8的集成电路结构，其中该集成电路结构没有位于该RDL之上并与之接触的衬垫，该衬垫以选自基本上由铜和共熔焊料构成的组中的一种材料形成。
13.根据权利要求8的集成电路结构，进一步包括：
多个穿透该半导体衬底的导电通孔；
多个位于该半导体衬底背面处的RDL，其中多个该RDL中的每一个连接到该多个导电通孔中的其中一个的后端；
多个位于该钝化层中的开口，其中通过该多个开口中的一个暴露该多个RDL中每一个的一部分，且其中该多个开口具有基本上相同的尺寸；以及
镍层，形成在该多个开口的每一个中，且接触该多个RDL中的一个。
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