CN112736069B - 晶粒组件及其制备方法 - Google Patents

晶粒组件及其制备方法 Download PDF

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Publication number
CN112736069B
CN112736069B CN202011140647.6A CN202011140647A CN112736069B CN 112736069 B CN112736069 B CN 112736069B CN 202011140647 A CN202011140647 A CN 202011140647A CN 112736069 B CN112736069 B CN 112736069B
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die
substrate
layer
metal lines
plug
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CN112736069A (zh
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施江林
吴珮甄
张庆弘
丘世仰
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种晶粒组件及其制备方法。该晶粒组件包括堆叠在一起的第一晶粒、第二晶粒、和第三晶粒。该第一晶粒包括多个第一金属线，其面对该第二晶粒的多个第二金属线，以及位于所述多个第二金属线之下的第二基板，其面对该第三晶粒的多个第三金属线。该晶粒组件还包括至少第一插塞、第一重分布层、和第二重分布层。该第一插塞穿过该第二基板以连接到所述多个第二金属线的至少一者。第一重分布层将所述多个第一金属线的至少一者物理性连接到所述多个第二金属线的至少一者，且第二重分布层将所述多个第三金属线的至少一者物理性连接到该第一插塞。

Description

晶粒组件及其制备方法
技术领域
本公开主张2019年10月28日申请的美国正式申请案第16/665,310号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
背景技术
随着集成电路技术不断地发展，人们持续地努力以提高性能和密度。设计者为了实现这些好处而探索的一种方法是实施堆叠式三维集成电路。适合考虑三维集成电路的一些领域包括使用相同或不同的工艺堆叠两个或更多个芯片以缩小集成电路系统的覆盖区(footprint)。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明披露本公开的标的，不组成本公开的现有技术，且上文的“现有技术”的任何说明均不应做为本公开的任一部分。
发明内容
本公开的一方面提供了一种晶粒组件。该晶粒组件包括第一晶粒、第二晶粒、第三晶粒、至少一第一插塞、一第一重分布层、和一第二重分布层。第一晶粒包括一第一基板和设置于该第一基板之上的多个第一金属线。第二晶粒包括一第二基板和设置于该第二基板之上的多个第二金属线，其中该第一晶粒堆叠在该第二晶粒上，且所述多个第二金属线面对所述多个第一金属线。第三晶粒包括一第三基板和设置于该第三基板之上的多个第三金属线，其中该第二晶粒堆叠在该第三晶粒上，且所述多个第三金属线面对该第二基板。第一插塞穿过该第二基板以连接到所述多个第二金属线的至少一者。第一重分布层将所述多个第一金属线的至少一者物理性连接到所述多个第二金属线的至少一者，且第二重分布层将所述多个第三金属线的至少一者物理性连接到该第一插塞。
在一些实施例中，该第一重分布层与距离该第一基板最远的该第一金属线对齐，且该第二重分布层与该第一插塞对齐。
在一些实施例中，该晶粒组件还包括一第一介电层，其位于该第一晶粒和该第二晶粒之间且环绕该第一重分布层；以及一第二介电层，位于该第二晶粒和该第三晶粒之间且环绕该第二重分布层。
在一些实施例中，该晶粒组件还包括至少一第二插塞，其穿过该第三基板并与所述多个第三金属线的至少一者接触。
在一些实施例中，该晶粒组件还包括一第三重分布层和一钝化层；该第三重分布层与该第二重分布层接触，且该钝化层环绕该第三重分布层。
在一些实施例中，该晶粒组件还包括至少一焊锡凸块，其电性耦合到该第三重分布层。
在一些实施例中，该晶粒组件还包括一第一障壁衬层和一第二障壁衬层；该第一障壁衬层位于该第二基板和该第一插塞之间，且位于该第二金属线和该第一插塞之间，而该第二障壁衬层位于该第三基板和该第二插塞之间，且位于该第三金属线和该第二插塞之间。
本公开的另一方面提供一种晶粒组件的制备方法。该制备方法包括以下步骤：提供一第一晶粒，其包括一第一基板和位于该第一基板之上的多个第一金属线；形成一第一重绕线层，其物理性连接到所述多个第一金属线的至少一者；提供一第二晶粒，其包括一第二基板和位于该第二基板之上的多个第二金属线；形成一第二重绕线层，其与该第一重绕线层对齐且与所述多个第二金属线的至少一者接触；接合该第一重绕线层和该第二重绕线层以形成一第一重分布层；形成至少一第一插塞，其穿过该第二基板且与所述多个第二金属线的至少一者接触；形成一第三重绕线层，其与该第一插塞接触；提供一第三晶粒，其包括一第三基板和位于该第三基板之上的多个第三金属线；形成一第四重绕线层，其与该第三重绕线层对齐且与所述多个第三金属线的至少一者接触；以及接合该第三重绕线层和该第四重绕线层以形成一第二重分布层。
在一些实施例中，该制备方法还包括以下步骤：沉积一毯状介电质于该第一基板之上且连接到距离该第一基板最远的所述多个第一金属线；进行一第一蚀刻工艺以通过该毯状介电质暴露出距离该第一基板最远的所述多个第一金属线的一部分，从而形成一第一介电膜；以及进行一电镀工艺以形成该第一重绕线层于通过该第一介电膜而暴露出来的该第一金属线上。
在一些实施例中，该制备方法还包括以下步骤：在形成该第二重绕线层之前，沉积一第二介电膜以覆盖距离该第二基板最远的该第二金属线的部分；以及在接合该第一重绕线层和该第二重绕线层的同时接合该第一介电膜和该第二介电膜。
在一些实施例中，形成该第三重绕线层包括以下步骤：沉积一第一前驱层于该第二基板和该第一插塞上；以及图案化该第一前驱层以移除该第一前驱层未与该第一插塞接触的部分，其中该第三重绕线层与该第一插塞对齐。
在一些实施例中，该制备方法还包括以下步骤：沉积一第三介电膜以围绕该第三重绕线层；在形成该第四重绕线层之前，沉积一第四介电膜以覆盖距离该第三基板最远的该第三金属线的部分；以及在接合该第三重绕线层和该第四重绕线层的同时接合该第三介电膜和该第四介电膜。
在一些实施例中，该制备方法还包括以下步骤：形成至少一第二插塞，其穿过该第三基板且与所述多个第三金属线的至少一者接触；以及形成一第三重分布层，其与该第二插塞接触。
在一些实施例中，该制备方法还包括在形成该第三重分布层之后进行一研磨工艺以薄化该第一基板。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得优选了解。组成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可做为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
本公开各方面可配合以下附图及详细说明阅读以便了解。要强调的是，依照工业上的标准惯例，各个部件(feature)并未按照比例绘制。事实上，为了清楚的讨论，可能任意的放大或缩小各个部件的尺寸。
图1是根据本公开的一些实施例显示一半导体系统的剖面图。
图2是根据本公开的一些实施例显示一半导体系统的剖面图。
图3是根据本公开的一些实施例显示制造一晶粒组件的第一部分方法流程图。
图4到图28是根据本公开的一些实施例显示形成一晶粒组件的中间阶段的剖面图。
附图标记说明：
10：半导体系统
10A：半导体系统
12：主基板
14：晶粒组件
14A：晶粒组件
20a：第一晶粒
20b：第二晶粒
20c：第三晶粒
20d：第四晶粒
32：第一重分布层
34：第二重分布层
36：第三重分布层
38：第四重分布层
42：第一插塞
43：第一障壁衬层
44：第二插塞
45：第二障壁衬层
46：第一介电层
46-1：第三插塞
48：第二介电层
50：钝化层
51：第四介电层
52：焊锡凸块
54：凸块下金属构件
60：方法
124：布线垫
210a：第一基板
210b：第二基板
210c：第三基板
212a：第一前表面
212b：第二前表面
212c：第三前表面
214b：第二后表面
214c：第三后表面
220a：第一层间介电(ILD)层
220b：第二ILD层
220c：第三ILD层
222a：顶表面
222c：顶表面
230a：第一金属线
230b：第二金属线
230c：第三金属线
232a：顶表面
232c：顶表面
240b：第一开口
240c：第二开口
250b：第一导电材料
250c：第二导电材料
322：第一重绕线层
324：第二重绕线层
342：第一前驱层
344：第三重绕线层
346：第四重绕线层
36-1：顶表面
362：第二前驱层
462：毯状介电质
464：第一介电膜
466：第二介电膜
482：第三介电膜
484：介电材料
486：第四介电膜
502：顶表面
602：步骤
604：步骤
606：步骤
608：步骤
610：步骤
612：步骤
614：步骤
616：步骤
618：步骤
620：步骤
622：步骤
624：步骤
626：步骤
628：步骤
630：步骤
632：步骤
634：步骤
636：步骤
638：步骤
640：步骤
642：步骤
644：步骤
650：步骤
710：第一掩模
712：窗口
720：第二掩模
730：第三掩模
740：第四掩模
750：第五掩模
760：第六掩模
3222：顶表面
3442：顶表面
4642：顶表面
4822：顶表面
C1：中心轴线
C2：中心轴线
T1：厚度
T4：厚度
T5：厚度
T6：厚度
具体实施方式
以下使用特定语言描述附图中所示本公开的实施例或示例。应理解的是，于此并不意图限制本公开的范围。所述实施例的任何改变或修改，以及本文中所述原则的任何进一步应用，对于与本公开相关的本技术领域技术人员来说，都被视为是会正常发生的。在所有实施例中可以重复使用参考符号，但这不一定意味着一实施例的部件(feature)适用于另一实施例，即使它们使用相同的参考符号。
应理解的是，尽管本文可以使用第一、第二、第三等用词来描述各种元件、组件、区域、层、或部分，但是这些元件、组件、区域、层、或部分不受限于这些用词。相反地，这些用词仅用于区分一个元件、组件、区域、层、或部分与另一元件、组件、区域、层、或部分。因此，在不悖离本公开概念启示的情况下，以下所讨论的第一元件、组件、区域、层、或部分可以被称为第二元件、组件、区域、层、或部分。
在此使用的用词仅出于描述特定示例实施例的目的，且不用于限制本公开的概念。如本文所使用的，除非上下文另外明确指出，单数形式的“一(a/an)”和“该”也包括多个形式。应理解的是，用词“包括(comprises)”和“包含(comprising)”在本说明书中使用时指出所述的部件、整数、步骤、操作、元件、或构件的存在，但不排除一或多个部件、整数、步骤、操作、元件、构件、或前述的组合的存在或增加。
图1是根据本公开的一些实施例显示一半导体系统10的剖面图。参照图1，半导体系统10包括一主基板12和一晶粒组件14，该晶粒组件包括对齐并接合在一起的第一晶粒20a、第二晶粒20b、和第三晶粒20c，其中第三晶粒20c设置于最靠近主基板12处。主基板12可以是电子系统(例如计算机系统)的印刷电路板(printed circuit board；PCB)，并且包括用于与晶粒组件14形成物理性和电性连接的多个布线垫124。
在一些实施例中，可以使用相同的工艺来制造第一晶粒20a、第二晶粒20b、和第三晶粒20c以形成例如存储器堆叠。然而，可以使用不同的工艺来制造第一至第三晶粒20a至20c，以堆叠一或多个存储器元件和一或多个处理器或专用集成电路(application-specific integrated circuit；ASIC)元件。
距离主基板12最远的第一晶粒20a包括第一基板210a、设置于第一基板210a的第一前表面212a上的第一层间介电(inter-layer dielectric；ILD)层220a、和位于第一ILD层220a中的多个第一金属线230a。在一些实施例中，第一ILD层220a面对主基板12。夹在第一晶粒20a和第三晶粒20c之间的第二晶粒20b包括第二基板210b、设置于第二基板210b的第二前表面212b上且面对第一ILD层220a的第二ILD层220b、以及设置于第二ILD层220b中的多个第二金属线230b。第三晶粒20c包括第三基板210c、设置于第三基板210c的第三前表面212c上的第三ILD层220c、以及设置于第三ILD层220c中的多个第三金属线230c。
晶粒组件14进一步包括位于第一晶粒20a和第二晶粒20b之间的第一重分布层(first redistribution layer)32，其用来做为第一晶粒20a和第二晶粒20b的电性内连线。具体地，第一重分布层32与距离第一基板210a最远且通过第二ILD层220a而暴露的第一金属线230a以及通过第二ILD层220b而暴露的第二金属线230b接触。在一些实施例中，第一重分布层32用于接合第一晶粒20a和第二晶粒20b。在一些实施例中，第一介电层46被施加在第一晶粒20a和第二晶粒20b之间并且包围第一重分布层32以降低第一重分布层32的腐蚀。第一介电层46也可以用于接合第一晶粒20a和第二晶粒20b以增加它们之间连接的机械强度。
晶粒组件14也包括用于接合第二晶粒20b和第三晶粒20c的第二重分布层34，并且包括用来做为与第二晶粒20b和第二重分布层34电性连接的一或多个第一插塞42。详细地，第一插塞42穿过第二基板210b并进入第二ILD层220b，并与最靠近第二基板210b的第二金属线230b接触。位于第二晶粒20b和第三晶粒20c之间的第二重分布层34将第一插塞42连接到通过第三ILD层220c而暴露的第三金属线230c。在一些实施例中，第二介电层48设置于第二晶粒20b和第三晶粒20c之间，并且围绕第二重分布层34。
在一些实施例中，晶粒组件14可还包括一或多个第二插塞44，其穿过第三基板210c并进入第三ILD层220c，以将最靠近第三基板210c的第三金属线230c连接到位于第三基板210c上的第三重分布层36和围绕第三重分布层36的钝化层50。
在一些实施例中，电性耦合至第三重分布层36的一或多个焊锡凸块52位于与布线垫124对应的位置，以与其形成物理性和电性连接。换句话说，焊锡凸块52用来做为输入/输出(input/output；I/O)连接，以将晶粒组件14电性连接到主基板12。在一些实施例中，一或多个凸块下金属(under bump metallization；UBM)构件54包括铜及/或铝，其夹在第三重分布层36和焊锡凸块52之间，以与焊锡凸块52产生良好的可接合性。
在一些实施例中，晶粒组件14可包括围绕第一插塞42的第一障壁衬层43和围绕第二插塞44的第二障壁衬层45。第一障壁衬层43和第二障壁衬层45做为胶层，包括难熔金属、难熔金属氮化物、难熔金属硅氮化物、或前述的组合。
图2是根据本公开的一些实施例显示半导体系统10A的剖面图。如图2所示，半导体系统10A包括主基板12和安装在主基板12上的晶粒组件14A。晶粒组件14A包括对齐并接合在一起的第一至第四晶粒20a至20d，其中第四晶粒20d设置于最靠近主基板12处。在一些实施例中，第一晶粒20a和第二晶粒20b以前对前(front-to-front)的配置方式垂直堆叠，且第二晶粒20b、第三晶粒20c、和第四晶粒20d以前对后(front-to-back)的配置方式垂直堆叠。
晶粒组件14A还包括第一重分布层32，其用于将第一晶粒20a接合至第二晶粒20b。在一些实施例中，设置于第一晶粒20a的第一ILD层220a和第二晶粒20b的第二ILD层220b之间的第一重分布层32与通过第一ILD层220a而暴露的第一金属线230a以及通过第二ILD层220b而暴露的第二金属线230b接触。在一些实施例中，被施加以围绕第一重分布层32的第一介电层46也用于接合第一晶粒20a和第二晶粒20b。在一些实施例中，第一晶粒20a和第二晶粒20b通过包括第一重分布层32和第一介电层46的混合接合(hybrid bonding)而接合。
晶粒组件14A还包括第二重分布层34和一或多个第一插塞42，其共同做为第二晶粒20b与第三晶粒20c的电性连接。第二重分布层34与通过第三晶粒20c的第三ILD层220c而暴露的第三金属线230c接触。第一插塞42穿过第二晶粒20b的第二基板210b并进入第二ILD层220b，将第二重分布层34连接至位于第二ILD层220b中的第二金属线230b。在一些实施例中，与第一重分布层32接触的第二金属线230b和与第一插塞42接触的第二金属线230b处于不同层中。详细地，与第一重分布层32接触的第二金属线230b被设置于距离第二基板210b最远的位置，且与第一插塞42接触的第二金属线230b被设置于距离第二基板210b最近的位置。在一些实施例中，位于第二晶粒20b与第三晶粒20c之间的第二重分布层34和第二介电层48形成用于接合第二晶粒20b和第三晶粒20c的接合界面。
在一些实施例中，晶粒组件14A也包括一或多个第二插塞44，其穿过第四基板210d以将第四金属线230d连接到第四基板210d上的第三重分布层36、环绕第三重分布层36的钝化层50、电性耦合到第三重分布层36的一或多个焊锡凸块52、以及夹在第三重分布层36和焊锡凸块52之间的一或多个UBM构件54。
在一些实施例中，第四重分布层38和一或多个第三插塞46-1共同做为第三晶粒20c与第四晶粒20d的电性连接。更具体地，第四重分布层38与通过第四晶粒20d的第四ILD层220d而暴露的第四金属线230d接触，且第三插塞46-1穿过第三晶粒20c的第三基板210c以将第四重分布层38连接到第三ILD层220c中的第三金属线230c。在一些实施例中，施加第四介电层51以围绕第四重分布层38并接合第三晶粒20c和第四晶粒20d。
图3是根据本公开的一些实施例显示制造晶粒组件14的方法60流程图。图4至图28是根据本公开的一些实施例显示用于制造晶粒组件14的方法60的各个工艺阶段示意图。图4至图28所示的阶段也示意性地显示于图3的流程图中。在随后的讨论中，将参照图3所示的工艺步骤讨论图4至图28所示的制造阶段。
参照图4，根据图3的步骤602提供第一晶粒20a。在一些实施例中，第一晶粒20a包括第一基板210a、位于第一基板210a的第一前表面212a上的第一ILD层220a、以及位于第一ILD层220a中的多个第一金属线230a。在一些实施例中，第一基板210a包括硅或其他半导体材料，像是第III-V族构件。在一些实施例中，第一基板210a可包括未单独描绘且结合以形成各种微电子元件、经掺杂区域、和隔离特征的各种层。在一些实施例中，第一基板210a具有原始厚度T1，其可例如等于或大于775μm。
在一些实施例中，包括一或多个介电层的第一ILD层220a是由氧化物、氮化物、或低介电常数(low-K)介电材料(例如，磷硅酸盐玻璃、硼磷硅酸盐玻璃等)组成。在一些实施例中，第一ILD层220a具有大约平坦的顶表面222a。在一些实施例中，可以使用旋涂工艺或化学气相沉积(chemical vapor deposition；CVD)工艺来形成第一ILD层220a。
在一些实施例中，形成在第一ILD层220a中的第一金属线230a提供与微电子元件及/或经掺杂区域的电性连接。在一些实施例中，距离第一基板210a最远的一些第一金属线230a通过第一ILD层220a而暴露。通过第一ILD层220a而暴露的第一金属线230a具有顶表面232a，其与第一ILD层220a的顶表面222a共平面。第一金属线230a可包括铜、铝、钨、或其类似材料。在一些实施例中，第一晶粒20a可进一步包括在不同的层(tier)中连接到第一金属线230a的多个通孔(vias)(未显示)，其中图4所示的第一晶粒20a包括三层的第一金属线230a；然而，在替代实施例中，第一晶粒20a可包括任何层数的第一金属线230a。
接下来，沉积毯状介电质462以覆盖第一ILD层220a的顶表面222a和第一金属线230的顶表面232a。使用例如CVD工艺形成包括氧化物及/或氮化物的毯状介电质462。
接下来，提供第一掩模710于毯状介电质462上，该第一掩模710包括一或多个窗口712以暴露毯状介电质462的一部分，并进行第一蚀刻工艺以通过窗口712蚀刻毯状介电质462。因此，如图5所示，形成第一介电膜464，且第一金属线230a的一部分通过第一介电膜464而暴露。在进行第一蚀刻工艺之后，移除第一掩模710。
参照图6，在一些实施例中，根据图3中的步骤604，进行电镀工艺以形成第一重绕线层322于通过第一介电膜464而暴露的第一金属线230a上。在一些实施例中，当以剖面图观察时，第一重绕线层322可以位于通过第一介电膜464而暴露的第一金属线230a的中心轴线C1的中心上。在一些实施例中，第一重绕线层322具有一顶表面3222，其与第一介电膜464的顶表面4642共平面。在一些实施例中，第一重绕线层322可包括铜、铝、钨、钴、钛、金、铂、或前述的组合。
参照图7，在一些实施例中，根据图3的步骤606，提供第二晶粒20b，并形成第二介电膜466和第二重绕线层324于第二晶粒20b上。在一些实施例中，第二晶粒20b在图7中上下倒置，其包括第二基板210b、位于第二基板210b的第二前表面212b上的第二ILD层220b、以及设置于第二ILD层220b中的多个第二金属线230b。在一些实施例中，第二重绕线层324与第一重绕线层322对齐并且与通过第二ILD层220b而暴露的第二金属线230b接触。第二介电膜466环绕第二重绕线层324。在一些实施例中，第二介电膜466和第二重绕线层324的材料和形成方法与第一介电膜464和第一重绕线层322的材料和形成方法基本上相同。
参照图8，在一些实施例中，根据图3的步骤608，对齐并接合第二晶粒20b与第一晶粒20a。在第二晶粒20b和第一晶粒20a接合之后，进行退火工艺以将第一重绕线层322接合至第二重绕线层324，从而形成第一重分布层32，并且使第一介电膜464熔融至第二介电膜466，从而形成第一介电层46。在一些实施例中，第二基板210b具有大约755μm的厚度T2。在一些实施例中，第一晶粒20a和第二晶粒20b通过例如混合接合工艺(hybrid bondingprocess)而接合。
参照图9，在一些实施例中，根据图3的步骤610，进行第一薄化工艺以薄化第二基板210b。在一些实施例中，将第二基板210b薄化以减少用于形成第一插塞的工艺时间，如将在下文描述的。在图9中，将第二基板210b薄化至大约50μm的厚度T3。
参照图10和图11，在一些实施例中，根据图3的步骤612，形成一或多个第一开口240b以暴露出距离第二基板210b最近的第二金属线230b。在一些实施例中，通过提供第二掩模720于相对于第二前表面212b的第二后表面214b上，并进行第二蚀刻工艺以移除第二基板210b和第二ILD层220b未被第二掩模720覆盖的部分来形成第一开口240b。在进行第二蚀刻工艺之后，通过例如灰化工艺或湿剥离工艺来移除第二掩模720。
参照图12，在一些实施例中，根据图3中的步骤614，可选地沉积第一障壁衬层43于第二后表面214b上和第一开口240b中。在一些实施例中，第一障壁衬层43是实质(substantially)保形的层，并且是使用例如物理气相沉积(physical vapor deposition；PVD)工艺而形成的。
参照图13，在一些实施例中，根据图3的步骤616，沉积第一导电材料250b于第一障壁衬层43上。在一些实施例中，通过使用电镀工艺或CVD工艺来将第一导电材料250b沉积于第二后表面214b之上。
参照图14，在一些实施例中，根据图3中的步骤618，进行第一平坦化工艺以暴露出第二基板210b。据此，形成一或多个第一插塞42。在一些实施例中，将第一障壁衬层43和第一导电材料250b向下平坦化至第二后表面214b。在一些实施例中，第一平坦化工艺包括化学机械研磨(chemical mechanical polishing；CMP)工艺及/或湿蚀刻工艺。
参照图15，在一些实施例中，根据图3中的步骤620，沉积第一前驱层342以覆盖第二后表面214b、第一插塞42、和第一障壁衬层43。在一些实施例中，利用CVD工艺、PVD工艺、溅镀工艺，蒸发工艺、或电镀工艺来形成包括铝、钨、钴、钛、金、铂、或前述的合金的第一前驱层342。接下来，提供第三掩模730于第一前驱层342上以图案化第一前驱层342。在一些实施例中，第一插塞42设置于第三掩模730下方。
参照图16，在一些实施例中，根据图3中的步骤622，进行第三蚀刻工艺以通过第三掩模730蚀刻第一前驱层342，从而形成第三重绕线层344。在进行第三蚀刻工艺之后，移除第三掩模730。在一些实施例中，当以剖面图观察时，第三重绕线层344可以位于第一插塞42的中心轴线C2的中心上。在一些实施例中，第三重绕线层344覆盖第二后表面214b的一部分。
参照图17，在一些实施例中，根据图3中的步骤624，沉积第三介电膜482于第二后表面214b上并围绕第三重绕线层344。在一些实施例中，第三重绕线层344具有与第三介电膜482的顶表面4822共平面的顶表面3442。在一些实施例中，可以使用CVD工艺来形成第三介电膜482。
参照图18和图19，在一些实施例中，根据图3中的步骤626，提供第三晶粒20c，并形成第四重绕线层346和第四介电膜486于第三晶粒20c上。参照图18，使用例如CVD工艺来沉积介电材料484于第三ILD层220c上，然后提供第四掩模740于介电材料484上以定义用于形成第四重绕线层346的图案。在一些实施例中，第三ILD层220c设置于第三晶粒20c的第三基板210c上，且具有与通过第三ILD层220c而暴露的第三金属线230c的顶表面232c共平面的顶表面222c。图18中的第三基板210c具有大于750μm的厚度T4。
接下来，进行第四蚀刻工艺以蚀刻介电材料484，从而形成第四介电膜486。接着，进行电镀工艺以形成第四重绕线层346于通过第四介电膜486而暴露的第三ILD层220c和第三金属线230c上。在一些实施例中，第四重绕线层346和第三重绕线层344(图17所示)具有相同的图案。
参照图20，在一些实施例中，根据图3的步骤628，上下倒置的第三晶粒20c堆叠在第二晶粒20b上并与其接合。在一些实施例中，第四重分布层346与第三重分布层344对齐。在一些实施例中，第四重分布层346接合至第三重分布层344以形成第二重分布层34，且第三介电膜482接合至第四介电层486以形成第二介电层48。
参照图21，在一些实施例中，根据图3的步骤630，进行第二薄化工艺以薄化第三基板210c。在图21中，第三基板210c具有大约50μm的厚度T5。
参照图22，在一些实施例中，根据图3的步骤632，形成至少一个第二开口240c以暴露出距离第三基板210c最近的一或多个第三金属线230c。在一些实施例中，通过提供第五掩模750于第三晶粒20c的第三后表面214c上，并进行第五蚀刻工艺以移除第三基板210c和第三ILD层220c未被第五掩模750覆盖的部分来形成第二开口240c。在进行第五蚀刻工艺之后，移除第五掩模750。
参照图23，在一些实施例中，根据图3中的步骤634，可选地沉积第三障壁衬层45于第三后表面214c上和第二开口240c中。在一些实施例中，第二障壁衬层45具有实质均匀的厚度。接下来，根据图3中的步骤636，沉积第二导电材料250c于第二障壁衬层45上。在一些实施例中，第二障壁衬层45和第二导电材料250c的材料和形成方法与第一障壁衬层43和第一导电材料250b的材料和形成方法基本上相同。
参照图24，在一些实施例中，根据图3的步骤638，进行第二平坦化工艺以暴露第三后表面214c。据此，形成一或多个第二插塞44。在第二平坦化工艺期间移除第二障壁衬层45和第二导电材料250c的一部分以暴露出第三基板210c。
参照图25和图26，在一些实施例中，根据图3的步骤640，沉积第二前驱层362于第三后表面214c、第二插塞44、和第二障壁衬层45上。在一些实施例中，第二前驱层362的材料和形成方法与第一前驱层342的材料和形成方法基本上相同。
接下来，根据图3的步骤642，提供第六掩模760于第二前驱层362上，并进行第六蚀刻工艺以形成第三重分布层36。在一些实施例中，第二插塞44设置于第六掩模760下方。
接下来，沉积钝化层50于第三基板210c上以覆盖第三后表面214c并环绕第三重分布层36。在一些实施例中，可使用CVD工艺形成包括氧化物的钝化层50。在一些实施例中，钝化层50具有与第三重分布层36的顶表面36-1共平面的顶表面502。
参照图27，在一些实施例中，根据图3的步骤644，形成至少一个UBM构件54于第三重分布层36上，并设置至少一个焊锡凸块52于UBM构件54上。在一些实施例中，通过最初将焊锡助熔剂(solder flux)(未显示)放置于UBM构件54上来安装焊锡凸块52，而且一旦焊锡凸块52与焊锡助熔剂接触，就可进行回焊以回焊焊锡凸块52的材料和焊锡助熔剂以将焊锡凸块52物理性接合至UBM构件54。
参照图28，在一些实施例中，根据图3的步骤646，进行研磨工艺以薄化第一基板210a。据此，完全地形成晶粒组件14。在一些实施例中，将第一基板210a薄化至厚度T6，例如小于或等于约50μm，以缩小晶粒组件14的整体尺寸。
本公开的一实施例提供了一种晶粒组件。该晶粒组件包括第一晶粒、第二晶粒、第三晶粒、至少一第一插塞、一第一重分布层、和一第二重分布层。第一晶粒包括一第一基板和设置于该第一基板之上的多个第一金属线。第二晶粒包括一第二基板和设置于该第二基板之上的多个第二金属线，其中该第一晶粒堆叠在该第二晶粒上，且所述多个第二金属线面对所述多个第一金属线。第三晶粒包括一第三基板和设置于该第三基板之上的多个第三金属线，其中该第二晶粒堆叠在该第三晶粒上，且所述多个第三金属线面对该第二基板。第一插塞穿过该第二基板以连接到所述多个第二金属线的至少一者。第一重分布层将所述多个第一金属线的至少一者物理性连接到所述多个第二金属线的至少一者，且第二重分布层将所述多个第三金属线的至少一者物理性连接到该第一插塞。
本公开的另实施例提供一种晶粒组件的制备方法。该制备方法包括以下步骤：提供一第一晶粒，其包括一第一基板和位于该第一基板之上的多个第一金属线；形成一第一重绕线层，其物理性连接到所述多个第一金属线的至少一者；提供一第二晶粒，其包括一第二基板和位于该第二基板之上的多个第二金属线；形成一第二重绕线层，其与该第一重绕线层对齐且与所述多个第二金属线的至少一者接触；接合该第一重绕线层和该第二重绕线层以形成一第一重分布层；形成至少一第一插塞，其穿过该第二基板且与所述多个第二金属线的至少一者接触；形成一第三重绕线层，其与该第一插塞接触；提供一第三晶粒，其包括一第三基板和位于该第三基板之上的多个第三金属线；形成一第四重绕线层，其与该第三重绕线层对齐且与所述多个第三金属线的至少一者接触；以及接合该第三重绕线层和该第四重绕线层以形成一第二重分布层。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或前述的组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中该的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的公开内容理解可根据本公开而使用与本文该的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。

Claims (13)

1.一种晶粒组件，包括：
一第一晶粒，包括一第一基板和设置于该第一基板之上的多个第一金属线；
一第二晶粒，包括一第二基板和设置于该第二基板之上的多个第二金属线，其中该第一晶粒堆叠在该第二晶粒上，且所述多个第二金属线面对所述多个第一金属线；
一第三晶粒，包括一第三基板和设置于该第三基板之上的多个第三金属线，其中该第二晶粒堆叠在该第三晶粒上，且所述多个第三金属线面对该第二基板；
至少一第一插塞，穿过该第二基板以连接到所述多个第二金属线的至少一者；
一第一重分布层，将所述多个第一金属线的至少一者物理性连接到所述多个第二金属线的至少一者；
一第二重分布层，将所述多个第三金属线的至少一者物理性连接到该第一插塞；
一第一介电层，位于该第一晶粒和该第二晶粒之间且环绕该第一重分布层；以及
一第二介电层，位于该第二晶粒和该第三晶粒之间且环绕该第二重分布层。
2.如权利要求1所述的晶粒组件，其中该第一重分布层与距离该第一基板最远的该第一金属线对齐，且该第二重分布层与该第一插塞对齐。
3.如权利要求1所述的晶粒组件，还包括至少一第二插塞，其穿过该第三基板并与所述多个第三金属线的至少一者接触。
4.如权利要求3所述的晶粒组件，还包括：
一第三重分布层，与该第二插塞接触；以及
一钝化层，环绕该第三重分布层。
5.如权利要求4所述的晶粒组件，还包括至少一焊锡凸块，其电性耦合到该第三重分布层。
6.如权利要求3所述的晶粒组件，还包括：
一第一障壁衬层，位于该第二基板和该第一插塞之间，且位于该第二金属线和该第一插塞之间；以及
一第二障壁衬层，位于该第三基板和该第二插塞之间，且位于该第三金属线和该第二插塞之间。
7.一种晶粒组件的制备方法，包括：
提供一第一晶粒，其包括一第一基板和位于该第一基板之上的多个第一金属线；
形成一第一重绕线层，其物理性连接到所述多个第一金属线的至少一者；
提供一第二晶粒，其包括一第二基板和位于该第二基板之上的多个第二金属线；
形成一第二重绕线层，其与该第一重绕线层对齐且与所述多个第二金属线的至少一者接触；
混合接合该第一重绕线层和该第二重绕线层以形成一第一重分布层；
形成至少一第一插塞，其穿过该第二基板且与所述多个第二金属线的至少一者接触；
形成一第三重绕线层，其与该第一插塞接触；
提供一第三晶粒，其包括一第三基板和位于该第三基板之上的多个第三金属线；
形成一第四重绕线层，其与该第三重绕线层对齐且与所述多个第三金属线的至少一者接触；以及
接合该第三重绕线层和该第四重绕线层以形成一第二重分布层；
其中该第一晶粒和该第二晶粒以前对前的配置方式垂直堆叠，该第二晶粒和该第三晶粒以前对后的配置方式垂直堆叠。
8.如权利要求7所述的晶粒组件的制备方法，还包括：
沉积一毯状介电质于该第一基板之上且连接到距离该第一基板最远的所述多个第一金属线；
进行一第一蚀刻工艺以通过该毯状介电质暴露出距离该第一基板最远的所述多个第一金属线的一部分，从而形成一第一介电膜；以及
进行一电镀工艺以形成该第一重绕线层于通过该第一介电膜而暴露的所述多个第一金属线上。
9.如权利要求8所述的晶粒组件的制备方法，还包括：
在形成该第二重绕线层之前，沉积一第二介电膜以覆盖距离该第二基板最远的该第二金属线的部分；以及
在接合该第一重绕线层和该第二重绕线层的同时接合该第一介电膜和该第二介电膜。
10.如权利要求7所述的晶粒组件的制备方法，其中形成该第三重绕线层包括：
沉积一第一前驱层于该第二基板和该第一插塞上；以及
图案化该第一前驱层以移除该第一前驱层未与该第一插塞接触的部分；
其中该第三重绕线层与该第一插塞对齐。
11.如权利要求7所述的晶粒组件的制备方法，还包括：
沉积一第三介电膜以围绕该第三重绕线层；
在形成该第四重绕线层之前，沉积一第四介电膜以覆盖距离该第三基板最远的该第三金属线的部分；以及
在接合该第三重绕线层和该第四重绕线层的同时接合该第三介电膜和该第四介电膜。
12.如权利要求7所述的晶粒组件的制备方法，还包括：
形成至少一第二插塞，其穿过该第三基板且与所述多个第三金属线的至少一者接触；以及
形成一第三重分布层，其与该第二插塞接触。
13.如权利要求12所述的晶粒组件的制备方法，还包括在形成该第三重分布层之后进行一研磨工艺以薄化该第一基板。
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