CN101752270A - 堆叠集成电路半导体晶粒的形成方法 - Google Patents

堆叠集成电路半导体晶粒的形成方法 Download PDF

Info

Publication number
CN101752270A
CN101752270A CN200910206678A CN200910206678A CN101752270A CN 101752270 A CN101752270 A CN 101752270A CN 200910206678 A CN200910206678 A CN 200910206678A CN 200910206678 A CN200910206678 A CN 200910206678A CN 101752270 A CN101752270 A CN 101752270A
Authority
CN
China
Prior art keywords
semiconductor crystal
wafer
those
crystal wafer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910206678A
Other languages
English (en)
Other versions
CN101752270B (zh
Inventor
陈明发
陈承先
邱文智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101752270A publication Critical patent/CN101752270A/zh
Application granted granted Critical
Publication of CN101752270B publication Critical patent/CN101752270B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明是有关于一种堆叠集成电路半导体晶粒的形成方法，是在集成电路晶粒或晶圆上形成穿硅介层窗(through-silicon vias；TSVs)，其中穿硅介层窗形成在金属化制程前的整合制程中。可制造具有增加的高宽比的穿硅介层窗，而更深入地延伸在晶圆基板中。此方法大致上可降低在晶圆背面研磨制程中过度薄化晶圆基板的风险，其中此晶圆背面研磨制程一般是用来露出及产生穿硅介层窗的电性连接。藉由提供更深的穿硅介层窗与接合垫，个别晶圆与晶粒可直接结合在穿硅介层窗与另一个晶圆上的接合垫之间。

Description

堆叠集成电路半导体晶粒的形成方法
技术领域
本发明涉及一种集成电路的制造方法，特别是涉及一种具有一个或多个穿硅介层窗(through-silicon vias；TSVs)的堆叠集成电路半导体晶粒的形成方法。
背景技术
一般来说，集成电路的操作速度会受到晶片上分离最远且可彼此通讯的元件之间的距离的影响。三维结构的布局电路已经被证实可以有效地降低晶片上元件间的通讯路径长度，其所提供的层间垂直距离远小于各层晶片宽度。因此，藉由垂直的堆叠电路层，通常可增加整体晶片的速度。现在已经运用一种通过晶圆键合的方式来进行这样的堆叠。
晶圆键合就是将两个或多个上面已经形成集成电路的半导体晶圆结合在一起。晶圆通常是藉由外氧化层的直接结合、或者藉由加入粘着剂至层间介电层(ILD)的方式来加以结合。结合的结果产生了一个三维的晶圆堆叠，此晶圆堆叠后续将被切割成独立的堆叠晶粒，其中每一个堆叠晶粒都具有多层集成电路。除了三维结构电路系统通常具有的增加速度的优点之外，晶圆堆叠还具有其它潜在利益，包含改善形成因素、低成本以及通过系统晶片(system-on-chip；SOC)解决方案所获得的较大的积集度。为了使得各种元件可整合到每个堆叠晶粒内，提供电性连接，以提供垂直层间的导体。通常制造穿硅介层窗时是藉由提供填满导体材料的介层窗，其中这些介层窗彻底穿过层，以接触及连接其它结合层的TSVs以及导体。
在一个现存的TSV形成制程中，在形成互补型金属氧化物半导体(CMOS)装置于晶圆基板上之后，或者甚至在上层金属化制程后，形成TSVs。CMOS制程或金属化制程后，再形成TSVs的一个缺点，就是由于蚀刻与设计的限制，介层窗的密度通常较低。蚀刻穿过金属化层通常不会造成凹槽，而可提供特别密集的TSV。此外，再次因为制程蚀刻通过金属化及接触区域，介层窗的设计受限于金属化层与接触区域的已存结构。因此，设计者通常必须将TSV网状系统设计于已存的金属层与接触线路的周遭。这些受限的设计与密度可能造成连接、接触以及可靠性的问题。
现存TSV的形成制程的另一个限制为，在晶圆基板中可形成的TSVs的有限深度。由于金属化层的现存结构，一般用来形成TSV开口于晶圆基板的蚀刻制程是在晶圆基板中进行至一有限深度，其中此有限深度远小于基板的厚度。例如，等离子体蚀刻制程通常可用以形成深度介于实质25微米(micron)至实质50微米的TSV开口，相比较于一般硅晶圆基板的厚度则有实质700微米。一般利用背面研磨的方式来薄化晶圆基板的厚度至小于100微米，并露出TSVs，以连接堆叠晶粒。然而，这样的实施方式可能降低晶圆基板的机械强度，其中此晶圆基板是作为形成于其上的集成电路的固体基础。此外，过度薄化的晶圆基板常会破损，因此严重的影响了整体IC产品的良率。
由此可见，上述现有的堆叠集成电路半导体晶粒的形成方法在方法与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决上述存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般方法又没有适切的方法能够解决上述问题，此显然是相关业者急欲解决的问题。因此如何能创设一种新的堆叠集成电路半导体晶粒的形成方法，实属当前重要研发课题之一，亦成为当前业界极需改进的目标。
发明内容
本发明的目的在于，克服现有的堆叠集成电路半导体晶粒的形成方法存在的缺陷，而提供一种新的堆叠集成电路半导体晶粒的形成方法，所要解决的技术问题是使其在金属化处理前形成TSVs，因而通常可以解决或避免上述现有或其他问题的发生，且可以获得技术优势。可以制作出具有更大高宽比且更深入晶圆基板中的TSVs。此方法大致上降低了晶圆基板在晶圆背磨制程中被过度薄化的风险，其中晶圆背磨制程一般是用来露出及制作出TSVs的电性接触，本发明藉由提供更深的TSVs与接合垫，使每个晶圆及晶粒可直接接合在这些TSVs与另一晶圆上的接合垫之间，非常适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种堆叠集成电路半导体晶粒的形成方法，其包括以下步骤：形成一个或多个凹槽于一第一半导体晶圆中；以一导体材料填满该或该些凹槽，以形成一个或多个穿硅介层窗于该第一半导体晶圆中；形成一个或多个接合接触于该第一半导体晶圆的一正面上；贴附该第一半导体晶圆的该正面至一载体，并暴露出该第一半导体晶圆的一背面；薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面；以及对齐及接合该或该些穿硅介层窗与一第二半导体晶粒或晶圆上的一个或多个接合表面上的一个或多个接合接触。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的堆叠集成电路半导体晶粒的形成方法，其中该或该些凹槽具有一直径范围介于实质5微米至实质50微米、以及一高宽比范围介于实质12∶1至实质3∶1。
前述的堆叠集成电路半导体晶粒的形成方法，更包含：形成一个或多个半导体元件于该第一半导体晶圆中；形成一层间介电层于该第一半导体晶圆上；形成一个或多个接触垫于该层间介电层上，并电性接触该或该些穿硅介层窗；形成多个互连金属线路于该层间介电层上的一金属间介电层中，该些互连金属线路电性连接至该或该些半导体元件以及该层间介电层中的该或该些接触垫；以及形成具有该或该些接合接触的一上介电层，该或该些接合接触电性耦接至该些互连金属线路的一个或多个。
前述的堆叠集成电路半导体晶粒的形成方法，其中所述的薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面步骤之后，该第一半导体晶圆具有一厚度范围介于实质25微米至实质250微米。
前述的堆叠集成电路半导体晶粒的形成方法，更包含：在薄化步骤后，形成一金属化绝缘层于该第一半导体晶圆的该背面上；以及形成一个或多个第二接合垫于该金属化绝缘层中，其中该或该些第二接合垫电性连接至该或该些穿硅介层窗且稍微突出于该金属化绝缘层。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种堆叠集成电路半导体晶粒的形成方法，其包括以下步骤：提供一第一半导体晶圆，该第一半导体晶圆具有一个或多个穿硅介层窗形成于一基板中；贴附该第一半导体晶圆的一正表面至一载体，并暴露出该第一半导体晶圆的一背面；薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面；形成一个或多个第一接合接触于该第一半导体晶圆薄化后的该背面上的一金属化绝缘层中，该或该些第一接合接触电性耦接至该或该些穿硅介层窗；提供一第二半导体工件，该第二半导体工件具有一个或多个第二接合接触位于该第二半导体工件的一接合表面上；以及对齐及接合该第一半导体晶圆上的该或该些第一接合接触与该第二半导体工件上的对应的一个或多个第二接合接触。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的堆叠集成电路半导体晶粒的形成方法，其中该或该些穿硅介层窗具有一直径范围介于实质5微米至实质50微米、以及一高宽比范围介于实质12∶1至实质3∶1。
前述的堆叠集成电路半导体晶粒的形成方法，其中所述的薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面步骤后，该第一半导体晶圆具有一厚度范围介于实质25微米至实质250微米。
前述的堆叠集成电路半导体晶粒的形成方法，更包含：形成一个或多个半导体元件于该第一半导体晶圆中；以及形成一个或多个第三接合接触于该第一半导体晶圆的该正面上，经由该第一半导体晶圆上的一金属间介电层中的一个或多个互连金属线路，该或该些第三接合接触电性耦接至该或该些半导体元件以及该或该些穿硅介层窗。
前述的堆叠集成电路半导体晶粒的形成方法，更包含：藉由在一覆晶集成电路封装结构中的多个凸块，将该堆叠集成电路半导体晶粒上的该或该些第三接合接触接合至一集成电路封装基板。
本发明与现有技术相比具有明显的优点和有益效果。借由上述技术方案，本发明堆叠集成电路半导体晶粒的形成方法至少具有下列优点及有益效果：本发明在金属化处理前形成TSVs，因而通常可以获得技术优势。可以制作出具有更大高宽比且更深入晶圆基板中的TSVs。此方法大致上降低了晶圆基板在晶圆背磨制程中被过度薄化的风险，其中晶圆背磨制程一般是用来露出及制作出TSVs的电性接触，本发明藉由提供更深的TSVs与接合垫，使每个晶圆及晶粒可直接接合在这些TSVs与另一晶圆上的接合垫之间。
综上所述，本发明是有关于一种堆叠集成电路半导体晶粒的形成方法，是在集成电路晶粒或晶圆上形成穿硅介层窗(through-siliconvias；TSVs)，其中穿硅介层窗形成在金属化制程前的整合制程中。可制造具有增加的高宽比的穿硅介层窗，而更深入地延伸在晶圆基板中。此方法大致上可降低在晶圆背面研磨制程中过度薄化晶圆基板的风险，其中此晶圆背面研磨制程一般是用来露出及产生穿硅介层窗的电性连接。本发明藉由提供更深的穿硅介层窗与接合垫，使得个别晶圆与晶粒可以直接结合在穿硅介层窗与另一个晶圆上的接合垫之间。本发明在技术上有显著的进步，具有明显的积极效果，诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1A至图1M是本发明一实施例形成具有穿硅介层窗的晶圆的剖面图。
图2是本发明一实施例的具有形成于基板与介电层中的穿硅介层窗的晶圆的剖面图。
图3是在覆晶球栅阵列结构中的集成电路封装的剖面图。
图4是实施本发明实施例的一示范步骤的流程图。
图5是实施本发明实施例的另一示范步骤流程图。
图6是实施本发明实施例的再一示范步骤流程图。
图7是实施本发明实施例的又一示范步骤流程图。
10、10’、11、12、13：晶圆    100：基板
101A、101B、101C：装置        102：层间介电层
103、104：穿硅介层窗凹槽      105：介电衬
106：导体                     107、108：穿硅介层窗
118A、118B、118C：接触        120A、120B、120C：第一互连线路
127：金属化绝缘层             124、125：接触垫
130、131：凹槽                132、133：接合垫
200：第一金属间介电层         300：第二金属间介电层
210：互连线路                 viala、vialb：介层窗
310：互连线路                 345：隔离层
339：介电层                   350：重布层
347：介层窗                   450：粘着剂
410、411、412：接合接触       600：基板
500：载体                     624：介电层
607、608：接合垫              20：集成电路封装
626：绝缘层
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的堆叠集成电路半导体晶粒的形成方法其具体实施方式、方法、步骤、特征及其功效，详细说明如后。
有关本发明的前述及其他技术内容、特点及功效，在以下配合参考图式的较佳实施例的详细说明中将可清楚呈现。通过具体实施方式的说明，当可对本发明为达成预定目的所采取的技术手段及功效获得一更加深入且具体的了解，然而所附图式仅是提供参考与说明之用，并非用来对本发明加以限制。
图1A至图1M是本发明一实施例形成具有穿硅介层窗的晶圆的剖面图。
现请参照阅图1A所示，其绘示了晶圆10的剖面图。晶圆10包含基板100以及制作在基板100上的装置101A、101B及101C，其中基板100的材料一般为硅(Si)，但也可为砷化镓(GaAs)、磷化镓砷(GaAsP)、磷化铟(InP)、砷化镓铝(GaAlAs)、磷化铟镓(InGaP)及其类似物。在图1B中，绝缘层(有时也称为层间介电层或ILD层)102沉积于晶圆10的基板100上。其绝缘材料包含，例如二氧化硅以及磷硅玻璃(phosphosilicate glass；PSG)。如图1C所示般，在晶圆10上进行蚀刻，以制造出穿硅介层窗凹槽103与104以及接触开口111A、111B及111C于层间介电层102中。为了要防止任何导体材料溶入晶圆10的电路系统的任何主动部分中，以共形层(Conformallayer)的方式沉积介电衬105，例如氮化硅(Silicon Nitride)，于晶圆10上，包覆介层窗凹槽103及104。在一较佳实施例中，介层窗凹槽103及104的尺寸(例如直径)的范围均是从实质5微米至实质50微米，且高宽比的范围从实质12∶1至实质3∶1。
如图1D所示，形成一层导体材料，即导体106，于晶圆10之上。此导体材料可包含各种材料，例如铜、钨、铝、金、银及其类似物。导体106填充TSV介层窗凹槽103及104，以及接触开口111A、111B与111C。利用蚀刻、化学机械研磨法(CMP)及类似方法移除导体106的多余部分后，此时晶圆10包含位于层间介电层102中的接触118A、118B及118C以及穿硅介层窗(TSVs)107与108，其中TSVs 107与108同时形成于基板100与层间介电层102中，如图1E所示。
在另一实施例中，接触118A、118B及118C可在制作TSVs 107及108之前形成。在另一及/或替代实施例中，接触118A、118B及118C可形成在TSVs 107及108形成之后。
接着，请参阅图1F，藉由应用在集成电路制造制程中的一般后段制作流程，在晶圆10上沉积且图案化第一互连层(M1层)，而形成第一互连线路120A、120B与120C以及接触垫124与125，其中第一互连线路120A至120C分别通过接触118A至118C而耦接于装置101A至101C，且接触垫124与125分别耦接于穿硅介层窗107、108。沉积第一金属间介电层200至晶圆10上。接着，利用现有技术，例如双镶嵌(dual damascene)制程，在晶圆10上沉积且图案化第二互连层(M2层)，而形成互连线路210。利用类似的方法，形成互连线路310于第三互连层(M3层)中，且覆盖于第二互连层中的互连线路210上方，其中互连线路310与互连线路210由第二金属间介电层300所分隔。晶圆10上的互连结构的制程，可继续在上方的互连层中进行，直到制作出晶圆10中各种装置及特征之间的所需交互连接。用来作为各互连层中的互连线路的导体材料可包含各种材料，例如铜、钨、铝、金、银及其类似物。值得注意的是，介层窗通常是用来将穿硅介层窗107及108通过接触垫124及125，而耦接至上层互连层(M2层与上方层)中的互连线路。例如，接触垫124以及互连线路210是藉由介层窗viala而以直接连接的方式进行耦接，其中介层窗viala是形成于穿硅介层窗107上且对齐穿硅介层窗107。又例如，接触垫125延伸通过一重布M1特征138，其中重布M1特征138通过介层窗vialb而耦接于互连线路210。在此例子中，介层窗vialb并非形成于穿硅介层窗108上，也非对齐于穿硅介层窗108。本发明的各种实施例并不受限于穿硅介层窗接触垫与上层互连层中的互连线路间仅为直接连接的型态。也值得注意的一点是，介层窗是用来连接各互连层中的互连线路，但为了简化图式，而未绘示于图1F中。之后，沉积隔离层345(有时也称为钝化层)于晶圆10上，其中隔离层345可提供晶圆10中的装置及互连线路机械或化学上的保护。
如图1G所示，经由沉积介电层339，来形成接合接触410、411及412，其中介电层339可使晶圆10中的装置及互连线路与连接至晶圆10的任何晶圆中的任何其他电路系统或装置之间绝缘。在介电层339中蚀刻出凹槽，沉积导体材料于这些凹槽中，以形成接合接触410、411及412。移除或蚀刻构成介电层339的绝缘材料，至暴露出接合接触410、411及412，使得接合接触410、411及412稍稍地高于介电层339的顶端。接合接触410、411及412可通过绝缘层345中的介层窗347而电性耦接至互连线路310。
应注意的是，如图1G所示，接合接触410、411及412相对于下方顶端互连层中的互连线路310的位置并未受到限制。然而，接合接触410、411及412与互连线路310间的连接应存在其它方式，例如重布层350(如图2所示)、互连线路或相似结构。本发明的各实施例并未限制接合接触与顶端互连层中的互连线路之间只能直接连接。
如图1H所示，涂布粘着剂450于晶圆10，以将晶圆10接合至晶圆载体500。载体500通常是用以在后续基板100背面的薄化制程中，提供机械支撑。在一较佳实施例中，载体500可为玻璃基板，或具有厚度介于实质500微米至实质1000微米的裸硅晶圆。
图1I是本发明的一实施例的晶圆10的剖面图。为了要提供介层窗107及108在背面的接触点，将晶圆10翻面，并由背面对基板100进行薄化，且藉由如蚀刻、化学机械研磨法或类似的方法，来移除基板100的一部分，以暴露出介层窗107及108的接触点。为了要完成上述步骤，将载体500固定于晶圆薄化手柄式夹具(Wafer thinning handle jig)，晶圆薄化手柄式夹具接着将装在晶圆薄化机构上。在移除基板100的这些部分中，介层窗107及108稍微地突出于基板100。在基板薄化制程后，晶圆10的厚度下降至实质25微米至实质250微米的范围。
图1J是晶圆10堆叠且接合至晶圆11的剖面图。晶圆11包含基板600、介电层624以及绝缘层626。基板600可包含一个或多个预先形成的半导体元件，介电层624可用以隔离形成在不同互连层中的互连线路，而绝缘层626可用来限制任何一个晶圆上的各种元件间的干扰。在介层窗107与接合垫607、以及介层窗108与接合垫608处，将晶圆10及11对齐且结合在一起，以形成堆叠晶圆12。接合的媒介，例如铜、钨、铜锡合金、金锡合金、铟金合金、铅锡合金或其相似物，都可涂布于预备接合的晶圆10及11上的接合接触之间。
在另一较佳实施例中，在对基板100进行薄化制程后(如图1I所示)，自晶圆10上将载体500拆下，并移除粘着剂450。如图1K所示，沉积金属化绝缘层127于介层窗107及108的突出边上的基板100背面上。金属化绝缘层127包含具有一层衬垫材料的多层绝缘材料层，其中此衬垫材料层可防止在金属化制程中所沉积的任何金属渗入晶圆10中。接着，在金属化绝缘层127中蚀刻出凹槽130及131。如图1L所示，金属化制程形成了接合垫132及133。沉积金属，例如铜、钨、铝或其相似物，于金属化绝缘层127，接着藉由蚀刻法或化学机械研磨法来蚀刻或移除金属的多余部分，以形成接合垫132及133。经过上述制程处理的晶圆在图1L中标示为晶圆10’。
图1M是晶圆11堆叠且接合至晶圆10’的剖面图。晶圆11包含基板600、介电层624以及绝缘层626。基板600可包含一个或多个预先形成的半导体元件，介电层624可用以隔离形成在不同互连层中的互连线路，而绝缘层626可用来限制两晶圆上各种元件间的干扰。在接合垫607与132以及接合垫608与133处，将晶圆10’及11对齐且接合在一起，而形成堆叠晶圆13。接合媒介，例如铜、钨、铜锡合金、金锡合金、铟金合金、铅锡合金或其相似物，涂布于预备接合的晶圆10’及11上的接合接触之间。
应该注意的是，虽然晶圆10、10’及11是以形成堆叠晶圆结构的方式来予以说明，在此所用的特定晶圆并非用以在任何方面限制本发明的实施例。在实际应用上，晶圆10、10’及11的结构可能为晶圆或晶粒，因此堆叠后的结构可能具有晶粒结合晶粒的结构、晶粒结合晶圆的结构或晶圆结合晶圆的结构。
也应该注意的是，任何数目的不同装置、元件、连接件或其相似结构可整合于晶圆10、10’及11中。在此所可能例示出的特定元件或缺少的元件并非用以在任何方面限制本发明的实施例。
应进一步注意的是，仅绘示一定数目的主动元件，例如装置101A至101C，以及介层窗，例如介层窗107及108，以利于清楚说明。然而，在此技术领域中具有通常知识的普通技术人员可了解到，在实际应用中，与集成电路及堆叠式晶粒有关的集成电路系统可能包含数百万甚至数千万或更多的主动元件，且这些互连结构在最上层的介电层中可能包含数十种甚至数百种导体。相同地，在此技术领域中具有通常知识的普通技术人员应理解到，在实际应用上，每一个堆叠晶粒包含数十个或更多的利用导电介层窗或导线的背面连接。较佳实施例中的堆叠晶粒结构可能包含数十个或者甚至数百个以上用以与集成电路封装产生电性连接的接合接触，例如，尽管只显示出三个接合接触410至412。
图3是在覆晶球栅阵列结构中的集成电路封装20的剖面图，其中集成电路封装20包含较佳实施例的堆叠晶粒，例如堆叠晶圆12(如图1J所示)或13(如图1M所示)中的堆叠晶粒。在堆叠晶圆12、13中的堆叠晶粒形成之后，通常以阵列形式排列大量的接合接触，例如接合接触410-412，在接合表面75上。接合表面75通过焊锡块(例如焊锡球)55，而贴附于封装基板50，进一步通过封装导线65而与印刷电路板(未绘示)产生电性连接。值得注意的是，在较佳实施例中，也可以用其它集成电路封装系统来封装堆叠晶粒。在另一个例子中，堆叠晶粒可直接焊接至印刷电路板。在此例示出的特定元件或缺少的元件并非用以在任何方面限制本发明的实施例。
应该注意的是，上述每一个例子所描述或图示出的晶圆及晶粒，意欲提供可应用在本发明的各种实施例的介层窗、接触垫以及接合垫的替代实施例。在本发明的其它或替代实施例中，可利用例示的选择的任意组合。这些说明实施例并非用以限制本发明的各种其它及/或替代实施例的实施。
更应注意的是，在说明实施例中所描述的不同层可依据所需功能或制程的可利用性而包含各种不同的材料。金属化接合垫的金属可以是任何适合的金属或合金，例如铜、钨、铝、铝铜及其相似物。再者，按照不同介电层或绝缘层的所需用途及功能，可使用任何介电材料，例如二氧化硅、氮化硅、碳化硅、氮氧化硅及其相似物。本发明并非仅限于使用任何特定范围的化合物及材料。
更应注意的是，说明实施例中的不同层与凹槽可利用各种已知的制程来沉积或形成。例如，氧化物、介电质或其它层等各种不同层的形成都可以经由化学气相沉积法(CVD)、原子层沉积法(ALD)或类似方法来达成。再者，由晶圆上移除材料可经由干蚀刻或湿蚀刻、化学机械研磨法(CMP)或类似方法来达成。本发明并不受限于任何单一方法。
图4是实施本发明实施例的一示范步骤的流程图。在步骤400中，在半导体元件形成于晶圆中之前，先形成一个或多个凹槽于第一晶圆中。上述凹槽由晶圆正表面延伸至与晶圆背表面相隔一预定距离处。在步骤410中，将导体材料，例如铜、钨、铝或其相似物，沉积至上述凹槽中，其中导体材料形成一个或多个介层窗。在一较佳实施例中，介层窗的尺寸(例如直径)介于实质15微米至实质35微米，且高宽比的范围由实质2∶1至实质3.3∶1。在步骤420中，于晶圆上形成半导体元件(例如互补金属氧化物半导体、或双极性装置或其相似装置)。在步骤430中，层间介电层沉积于半导体元件与介层窗上的晶圆的正表面上，其中层间介电层是由一绝缘材料组成，此材料例如为二氧化硅、氮化硅、碳化硅、氮氧化硅、或其相似物。在步骤440中，一个或多个接触形成于层间介电层上，其中多个选定接触电性连接至多个选定的穿硅介层窗。
图5是实施本发明的实施例的另一示范步骤流程图。在步骤500中，形成多个半导体元件(例如互补式金属氧化物半导体元件)于第一半导体晶圆的正面上。在步骤510中，沉积层间介电层至半导体元件上的晶圆的正表面上，其中层间介电层是由一绝缘材料组成，此材料例如为二氧化硅、磷硅酸盐玻璃(phosphosilicate glass；PSG)、氮化硅、碳化硅、氮氧化硅或其相似物等材料所组成。在步骤520中，形成一个或多个凹槽至半导体晶圆中。这些凹槽延伸穿过层间介电层与晶圆的正表面至与晶圆的背表面相隔一预定距离处。在步骤530中，将导体材料，例如铜、钨、铝、或其相似物，沉积至凹槽中，以在晶圆中形成穿硅介层窗。在一较佳实施例中，穿硅介层窗的尺寸(例如直径)的范围介于实质15微米至实质35微米之间，且高宽比的范围介于实质2∶1至实质3.3∶1之间。在步骤540中，形成一个或多个接触于层间介电层上，其中多个选定接点电性连接至多个选定穿硅介层窗。
图6是实施本发明实施例的再一示范步骤流程图。在步骤600中，在形成半导体元件于晶圆中之前(例如图4所示)，或者在形成半导体元件于晶圆之后，但在形成多个互连线路于晶圆上以连接形成于晶圆中的半导体元件之前(例如图5所示)，在第一晶圆中形成一个或多个凹槽。这些凹槽自晶圆的正表面延伸至与晶圆的背表面相隔一预定距离处。在步骤610中，在凹槽中沉积导体材料，例如铜、钨、铝或其相似物，此导体材料形成多个穿硅介层窗。在此实施例中，这些穿硅介层窗的尺寸(例如直径)的范围介于实质15微米至实质35微米之间，且高宽比的范围介于实质2∶1至实质3.3∶1之间。在步骤620中，在沉积于晶圆正表面上的一层间介电层中，形成一个或多个接触，其中多个选定接点电性连接至多个选定穿硅介层窗。在步骤630中，沉积一层或多层金属间介电层至层间介电层与接触上。形成多条金属线路至金属间介电层中，以电性耦接半导体元件及穿硅介层窗。在步骤640中，形成一个或多个接合接触于前述的一层或多层介电层上，其中所述接合接触电性连接至多个选定的金属线路及/或穿硅介层窗。在步骤650中，将前述的一个或多个接合接触对齐堆叠式晶粒对晶圆结构或晶圆对晶圆结构中的第二晶粒或晶圆上的一个或多个接触表面上的一个或多个接合接触。其接合媒介，例如铜、钨、铜锡合金、金锡合金、铟金合金、铅锡合金或其相似物，涂布于欲接合晶圆上的接合接触之间。接着，可对堆叠式晶粒对晶圆结构或堆叠式晶圆对晶圆结构进行切割或封装，其中藉由焊锡凸块，前述的一个或多个接合接触接合于集成电路封装，再通过封装导线而电性连接至印刷电路板。
图7是实施本发明实施例的又一示范步骤流程图。在步骤700中，以粘着剂将第一晶圆的正表面贴附至载体，其中第一晶圆具有一个或多个穿硅介层窗。在步骤710中，移除第一晶圆背面上的基板材料的一部分，以暴露出穿硅介层窗的背面连接。在步骤720中，制作一个或多个背面接合接触，此背面接合接触电性连接至穿硅介层窗所暴露出的背面连接。在步骤730中，以与接合接触电性相容的材料，例如铜、钨、金、铜锡合金、铟金合金、铅锡合金或其相似物，将第一晶圆的背面接合接触与另一晶圆的接合接触对齐且接合。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种堆叠集成电路半导体晶粒的形成方法，其特征在于其包括以下步骤：
形成一个或多个凹槽于一第一半导体晶圆中；
以一导体材料填满该或该些凹槽，以形成一个或多个穿硅介层窗于该第一半导体晶圆中；
形成一个或多个接合接触于该第一半导体晶圆的一正面上；
贴附该第一半导体晶圆的该正面至一载体，并暴露出该第一半导体晶圆的一背面；
薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面；以及
对齐及接合该或该些穿硅介层窗与一第二半导体晶粒或晶圆上的一个或多个接合表面上的一个或多个接合接触。
2.根据权利要求1所述的堆叠集成电路半导体晶粒的形成方法，其特征在于其中该或该些凹槽具有一直径范围介于5微米至50微米、以及一高宽比范围介于12∶1至3∶1。
3.根据权利要求1所述的堆叠集成电路半导体晶粒的形成方法，其特征在于更包含：
形成一个或多个半导体元件于该第一半导体晶圆中；
形成一层间介电层于该第一半导体晶圆上；
形成一个或多个接触垫于该层间介电层上，并电性接触该或该些穿硅介层窗；
形成多个互连金属线路于该层间介电层上的一金属间介电层中，该些互连金属线路电性连接至该或该些半导体元件以及该层间介电层中的该或该些接触垫；以及
形成具有该或该些接合接触的一上介电层，该或该些接合接触电性耦接至该些互连金属线路的一个或多个。
4.根据权利要求1所述的堆叠集成电路半导体晶粒的形成方法，其特征在于在其中所述的薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面步骤之后，该第一半导体晶圆具有一厚度范围介于25微米至250微米。
5.根据权利要求1所述的堆叠集成电路半导体晶粒的形成方法，其特征在于更包含：
在薄化步骤后，形成一金属化绝缘层于该第一半导体晶圆的该背面上；以及
形成一个或多个第二接合垫于该金属化绝缘层中，其中该或该些第二接合垫电性连接至该或该些穿硅介层窗且稍微突出于该金属化绝缘层。
6.一种堆叠集成电路半导体晶粒的形成方法，其特征在于其包括以下步骤：
提供一第一半导体晶圆，该第一半导体晶圆具有一个或多个穿硅介层窗形成于一基板中；
贴附该第一半导体晶圆的一正表面至一载体，并暴露出该第一半导体晶圆的一背面；
薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面；
形成一个或多个第一接合接触于该第一半导体晶圆薄化后的该背面上的一金属化绝缘层中，该或该些第一接合接触电性耦接至该或该些穿硅介层窗；
提供一第二半导体工件，该第二半导体工件具有一个或多个第二接合接触位于该第二半导体工件的一接合表面上；以及
对齐及接合该第一半导体晶圆上的该或该些第一接合接触与该第二半导体工件上的对应的一个或多个第二接合接触。
7.根据权利要求6所述的堆叠集成电路半导体晶粒的形成方法，其特征在于其中该或该些穿硅介层窗具有一直径范围介于5微米至50微米、以及一高宽比范围介于12∶1至3∶1。
8.根据权利要求6所述的堆叠集成电路半导体晶粒的形成方法，其特征在于其中在所述的薄化该第一半导体晶圆的该背面直到该或该些穿硅介层窗暴露出且稍微突出于该第一半导体晶圆的该背面步骤后，该第一半导体晶圆具有一厚度范围介于25微米至250微米。
9.根据权利要求6所述的堆叠集成电路半导体晶粒的形成方法，其特征在于更包含：
形成一个或多个半导体元件于该第一半导体晶圆中；以及
形成一个或多个第三接合接触于该第一半导体晶圆的该正面上，经由该第一半导体晶圆上的一金属间介电层中的一个或多个互连金属线路，该或该些第三接合接触电性耦接至该或该些半导体元件以及该或该些穿硅介层窗。
10.根据权利要求9所述的堆叠集成电路半导体晶粒的形成方法，其特征在于更包含：
藉由在一覆晶集成电路封装结构中的多个凸块，将该堆叠集成电路半导体晶粒上的该或该些第三接合接触接合至一集成电路封装基板。
CN2009102066784A 2008-12-05 2009-10-28 堆叠集成电路半导体晶粒的形成方法 Active CN101752270B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/329,341 2008-12-05
US12/329,341 US8158456B2 (en) 2008-12-05 2008-12-05 Method of forming stacked dies

Publications (2)

Publication Number Publication Date
CN101752270A true CN101752270A (zh) 2010-06-23
CN101752270B CN101752270B (zh) 2012-07-04

Family

ID=42231536

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009102066784A Active CN101752270B (zh) 2008-12-05 2009-10-28 堆叠集成电路半导体晶粒的形成方法

Country Status (3)

Country Link
US (1) US8158456B2 (zh)
CN (1) CN101752270B (zh)
TW (1) TWI399827B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024801A (zh) * 2010-10-12 2011-04-20 北京大学 超薄芯片垂直互联封装结构及其制造方法
CN102347316A (zh) * 2010-07-29 2012-02-08 台湾积体电路制造股份有限公司 三维集成电路结构
CN103378015A (zh) * 2012-04-20 2013-10-30 南亚科技股份有限公司 半导体芯片与封装结构以及其形成方法
CN112736069A (zh) * 2019-10-28 2021-04-30 南亚科技股份有限公司 晶粒组件及其制备方法
TWI761957B (zh) * 2020-03-20 2022-04-21 美商矽成積體電路股份有限公司 晶圓接合結構與其形成方法

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2946795B1 (fr) * 2009-06-12 2011-07-22 3D Plus Procede de positionnement des puces lors de la fabrication d'une plaque reconstituee
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
KR101107627B1 (ko) * 2010-02-22 2012-01-25 (주)실리콘화일 3차원 구조를 갖는 웨이퍼의 패드 형성 방법
US8435835B2 (en) 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8993377B2 (en) 2010-09-29 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of bonding different size semiconductor die at the wafer level
KR101697573B1 (ko) * 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
TWI416679B (zh) * 2010-12-06 2013-11-21 Ind Tech Res Inst 半導體結構及其製造方法
US8354327B2 (en) * 2011-04-21 2013-01-15 Globalfoundries Singapore Pte Ltd Scheme for planarizing through-silicon vias
US9177893B2 (en) * 2011-05-17 2015-11-03 Infineon Technologies Ag Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8552548B1 (en) * 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
FR2983638A1 (fr) * 2011-12-02 2013-06-07 St Microelectronics Sa Procede de formation d'un circuit integre
KR101918609B1 (ko) * 2012-01-11 2018-11-14 삼성전자 주식회사 집적회로 소자
US20140147984A1 (en) * 2012-11-27 2014-05-29 United Microelectronics Corp. Semiconductor device and method of fabricating through silicon via structure
TWI492340B (zh) * 2012-12-12 2015-07-11 Ind Tech Res Inst 封裝結構及其製造方法
KR102038488B1 (ko) 2013-02-26 2019-10-30 삼성전자 주식회사 반도체 패키지의 제조 방법
US9406588B2 (en) 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9437572B2 (en) * 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9431351B2 (en) 2014-10-17 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9659863B2 (en) 2014-12-01 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, multi-die packages, and methods of manufacture thereof
US9502272B2 (en) 2014-12-29 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Devices and methods of packaging semiconductor devices
US10319701B2 (en) 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US9601410B2 (en) 2015-01-07 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9633958B2 (en) 2015-01-30 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad surface damage reduction in a formation of digital pattern generator
US10163709B2 (en) 2015-02-13 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9969614B2 (en) 2015-05-29 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS packages and methods of manufacture thereof
JP2016225471A (ja) * 2015-05-29 2016-12-28 株式会社東芝 半導体装置および半導体装置の製造方法
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9536865B1 (en) 2015-07-23 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection joints having variable volumes in package structures and methods of formation thereof
US9570431B1 (en) 2015-07-28 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer for integrated packages
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US9691695B2 (en) 2015-08-31 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
US10644229B2 (en) 2015-09-18 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetoresistive random access memory cell and fabricating the same
US10269682B2 (en) 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9659878B2 (en) 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US10163856B2 (en) 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
US9911623B2 (en) 2015-12-15 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Via connection to a partially filled trench
US9589941B1 (en) 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9741669B2 (en) 2016-01-26 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Forming large chips through stitching
US10050018B2 (en) 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US9842829B2 (en) 2016-04-29 2017-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US9859258B2 (en) 2016-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10147704B2 (en) 2016-05-17 2018-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof
US9881903B2 (en) 2016-05-31 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with epoxy flux residue
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US9875982B2 (en) 2016-06-01 2018-01-23 Taiwan Semiconductor Manufacturing Company Ltd Semiconductor device and manufacturing method thereof
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US10115675B2 (en) 2016-06-28 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of fabricating a packaged semiconductor device
US10685911B2 (en) 2016-06-30 2020-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9941186B2 (en) 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US10163805B2 (en) 2016-07-01 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9893046B2 (en) 2016-07-08 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Thinning process using metal-assisted chemical etching
US9870975B1 (en) 2016-07-14 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package with thermal dissipation structure and method for forming the same
US9875972B1 (en) 2016-07-14 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US10332841B2 (en) 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US10269732B2 (en) 2016-07-20 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info package with integrated antennas or inductors
US10157885B2 (en) 2016-07-29 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having magnetic bonding between substrates
US10720360B2 (en) 2016-07-29 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die singulation and structures formed thereby
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US10535632B2 (en) 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US10049981B2 (en) 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
US11097942B2 (en) 2016-10-26 2021-08-24 Analog Devices, Inc. Through silicon via (TSV) formation in integrated circuits
US10170429B2 (en) 2016-11-28 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming package structure including intermetallic compound
US10153218B2 (en) 2016-11-29 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10153320B2 (en) 2016-11-29 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of forming the same
TWI708358B (zh) * 2017-07-11 2020-10-21 聯華電子股份有限公司 半導體裝置及其製造方法
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US10879183B2 (en) 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11172142B2 (en) 2018-09-25 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor for sensing LED light with reduced flickering
US11201122B2 (en) 2018-09-27 2021-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating semiconductor device with reduced warpage and better trench filling performance
US11552019B2 (en) * 2019-03-12 2023-01-10 Intel Corporation Substrate patch reconstitution options
US11004829B2 (en) 2019-10-07 2021-05-11 Sandisk Technologies Llc Memory scaling semiconductor device
US11133304B2 (en) 2019-11-27 2021-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Packaging scheme involving metal-insulator-metal capacitor
US11276764B1 (en) * 2020-08-09 2022-03-15 Global Communication Semiconductors, Llc Method of making high frequency InGaP/GaAs HBTs
TWI839620B (zh) 2021-06-30 2024-04-21 立積電子股份有限公司 半導體裝置及形成半導體裝置之方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211239A (ja) * 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
DE4314907C1 (de) * 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) * 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
JP3537447B2 (ja) * 1996-10-29 2004-06-14 トル‐シ・テクノロジーズ・インコーポレイテッド 集積回路及びその製造方法
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6037822A (en) * 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US6274253B1 (en) * 1998-11-13 2001-08-14 Micron Technology, Inc. Processing methods for providing metal-comprising materials within high aspect ratio openings
JP3532788B2 (ja) * 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) * 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
WO2003063242A1 (en) * 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) * 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) * 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) * 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
TWI251313B (en) * 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
CN103199017B (zh) * 2003-12-30 2016-08-03 飞兆半导体公司 形成掩埋导电层方法、材料厚度控制法、形成晶体管方法
JP4467318B2 (ja) * 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4205613B2 (ja) * 2004-03-01 2009-01-07 エルピーダメモリ株式会社 半導体装置
US7262495B2 (en) * 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7297574B2 (en) * 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7598523B2 (en) * 2007-03-19 2009-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for stacking dies having through-silicon vias
US7576435B2 (en) * 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347316A (zh) * 2010-07-29 2012-02-08 台湾积体电路制造股份有限公司 三维集成电路结构
CN102347316B (zh) * 2010-07-29 2013-07-24 台湾积体电路制造股份有限公司 三维集成电路结构
CN102024801A (zh) * 2010-10-12 2011-04-20 北京大学 超薄芯片垂直互联封装结构及其制造方法
CN102024801B (zh) * 2010-10-12 2012-11-21 北京大学 超薄芯片垂直互联封装结构及其制造方法
CN103378015A (zh) * 2012-04-20 2013-10-30 南亚科技股份有限公司 半导体芯片与封装结构以及其形成方法
CN112736069A (zh) * 2019-10-28 2021-04-30 南亚科技股份有限公司 晶粒组件及其制备方法
CN112736069B (zh) * 2019-10-28 2024-03-29 南亚科技股份有限公司 晶粒组件及其制备方法
TWI761957B (zh) * 2020-03-20 2022-04-21 美商矽成積體電路股份有限公司 晶圓接合結構與其形成方法

Also Published As

Publication number Publication date
US8158456B2 (en) 2012-04-17
US20100144094A1 (en) 2010-06-10
CN101752270B (zh) 2012-07-04
TWI399827B (zh) 2013-06-21
TW201023299A (en) 2010-06-16

Similar Documents

Publication Publication Date Title
CN101752270B (zh) 堆叠集成电路半导体晶粒的形成方法
US9793192B2 (en) Formation of through via before contact processing
CN101542726B (zh) 具有硅通孔和侧面焊盘的半导体芯片
CN102332435B (zh) 电子元件及其制作方法
KR101171526B1 (ko) 캐리어 웨이퍼 수정을 통한 ｔｓｖ 후면 상호연결부 형성의 개선
US8026592B2 (en) Through-silicon via structures including conductive protective layers
CN101719484B (zh) 具有再分布线的tsv的背连接
US8097953B2 (en) Three-dimensional integrated circuit stacking-joint interface structure
CN102867777B (zh) 在半导体衬底中形成接地硅通孔
US20100123241A1 (en) Semiconductor chip with through-silicon-via and sidewall pad
US11217560B2 (en) Die assembly and method of manufacturing the same
CN101740417B (zh) 可堆叠芯片的制造方法
CN108428679A (zh) 具有热导柱的集成电路封装
JP5780165B2 (ja) 半導体装置およびその製造方法
CN110335859B (zh) 一种基于tsv的多芯片的封装结构及其制备方法
US20240055390A1 (en) Manufacturing method of semiconductor device
CN115910818A (zh) 扇出型芯片封装方法
CN116137257A (zh) 半导体封装件
CN115312496A (zh) 基于后通孔技术的三维半导体集成封装结构及工艺
KR102714218B1 (ko) 반도체 패키지
US20240105679A1 (en) Semiconductor package and method of fabricating the same
CN117936502A (zh) 半导体封装件
CN116344438A (zh) 封装方法及封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant