TW202117986A - 晶粒組件及其製備方法 - Google Patents

晶粒組件及其製備方法 Download PDF

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TW202117986A
TW202117986A TW109123471A TW109123471A TW202117986A TW 202117986 A TW202117986 A TW 202117986A TW 109123471 A TW109123471 A TW 109123471A TW 109123471 A TW109123471 A TW 109123471A TW 202117986 A TW202117986 A TW 202117986A
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layer
substrate
die
plug
metal wires
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TW109123471A
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TWI749633B (zh
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施江林
吳珮甄
張慶弘
丘世仰
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南亞科技股份有限公司
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Abstract

本揭露提供一種晶粒組件及其製備方法。該晶粒組件包括堆疊在一起的第一晶粒、第二晶粒、和第三晶粒。該第一晶粒包括複數個第一金屬線，其面對該第二晶粒的複數個第二金屬線，以及位於該些第二金屬線之下的第二基板，其面對該第三晶粒的複數個第三金屬線。該晶粒組件更包括至少第一插塞、第一重分佈層、和第二重分佈層。該第一插塞穿過該第二基板以連接到該些第二金屬線之至少一者。第一重分佈層將該些第一金屬線之至少一者物理性連接到該些第二金屬線之至少一者，且第二重分佈層將該些第三金屬線之至少一者物理性連接到該第一插塞。

Description

晶粒組件及其製備方法
本申請案主張2019年10月28日申請之美國正式申請案第16/665,310號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是關於一種晶粒組件及其製備方法。
隨著積體電路技術不斷地發展，人們持續地努力以提高性能和密度。設計者為了實現這些好處而探索的一種方法是實施堆疊式三維積體電路。適合考慮三維積體電路的一些領域包括使用相同或不同的製程堆疊兩個或更多個晶片以縮小積體電路系統的覆蓋區（footprint）。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不組成本揭露之先前技術，且上文之「先前技術」之任何說明均不應做為本案之任一部分。
本揭露的一方面提供了一種晶粒組件。該晶粒組件包括第一晶粒、第二晶粒、第三晶粒、至少一第一插塞、一第一重分佈層、和一第二重分佈層。第一晶粒包括一第一基板和設置於該第一基板之上的複數個第一金屬線。第二晶粒包括一第二基板和設置於該第二基板之上的複數個第二金屬線，其中該第一晶粒堆疊在該第二晶粒上，且該些第二金屬線面對該些第一金屬線。第三晶粒包括一第三基板和設置於該第三基板之上的複數個第三金屬線，其中該第二晶粒堆疊在該第三晶粒上，且該些第三金屬線面對該第二基板。第一插塞穿過該第二基板以連接到該些第二金屬線之至少一者。第一重分佈層將該些第一金屬線之至少一者物理性連接到該些第二金屬線之至少一者，且第二重分佈層將該些第三金屬線之至少一者物理性連接到該第一插塞。
在一些實施例中，該第一重分佈層與距離該第一基板最遠之該第一金屬線對齊，且該第二重分佈層與該第一插塞對齊。
在一些實施例中，該晶粒組件更包括一第一介電層，其位於該第一晶粒和該第二晶粒之間且環繞該第一重分佈層；以及一第二介電層，位於該第二晶粒和該第三晶粒之間且環繞該第二重分佈層。
在一些實施例中，該晶粒組件更包括至少一第二插塞，其穿過該第三基板並與該些第三金屬線之至少一者接觸。
在一些實施例中，該晶粒組件更包括一第三重分佈層和一鈍化層；該第三重分佈層與該第二重分佈層接觸，且該鈍化層環繞該第三重分佈層。
在一些實施例中，該晶粒組件更包括至少一銲錫凸塊，其電性耦合到該第三重分佈層。
在一些實施例中，該晶粒組件更包括一第一障壁襯層和一第二障壁襯層；該第一障壁襯層位於該第二基板和該第一插塞之間，且位於該第二金屬線和該第一插塞之間，而該第二障壁襯層位於該第三基板和該第二插塞之間，且位於該第三金屬線和該第二插塞之間。
本揭露的另一方面提供一種晶粒組件的製備方法。該製備方法包括以下步驟：提供一第一晶粒，其包括一第一基板和位於該第一基板之上的複數個第一金屬線；形成一第一重繞線層，其物理性連接到該些第一金屬線之至少一者；提供一第二晶粒，其包括一第二基板和位於該第二基板之上的複數個第二金屬線；形成一第二重繞線層，其與該第一重繞線層對齊且與該些第二金屬線之至少一者接觸；接合該第一重繞線層和該第二重繞線層以形成一第一重分佈層；形成至少一第一插塞，其穿過該第二基板且與該些第二金屬線之至少一者接觸；形成一第三重繞線層，其與該第一插塞接觸；提供一第三晶粒，其包括一第三基板和位於該第三基板之上的複數個第三金屬線；形成一第四重繞線層，其與該第三重繞線層對齊且與該些第三金屬線之至少一者接觸；以及接合該第三重繞線層和該第四重繞線層以形成一第二重分佈層。
在一些實施例中，該製備方法更包括以下步驟：沈積一毯狀介電質於該第一基板之上且連接到距離該第一基板最遠之該些第一金屬線；進行一第一蝕刻製程以透過該毯狀介電質暴露出距離該第一基板最遠之該些第一金屬線的一部分，從而形成一第一介電膜；以及進行一電鍍製程以形成該第一重繞線層於透過該第一介電膜而暴露出來的該第一金屬線上。
在一些實施例中，該製備方法更包括以下步驟：在形成該第二重繞線層之前，沈積一第二介電膜以覆蓋距離該第二基板最遠之該第二金屬線的部分；以及在接合該第一重繞線層和該第二重繞線層的同時接合該第一介電膜和該第二介電膜。
在一些實施例中，形成該第三重繞線層包括以下步驟：沈積一第一前驅層於該第二基板和該第一插塞上；以及圖案化該第一前驅層以移除該第一前驅層未與該第一插塞接觸的部分，其中該第三重繞線層與該第一插塞對齊。
在一些實施例中，該製備方法更包括以下步驟：沈積一第三介電膜以圍繞該第三重繞線層；在形成該第四重繞線層之前，沈積一第四介電膜以覆蓋距離該第三基板最遠之該第三金屬線的部分；以及在接合該第三重繞線層和該第四重繞線層的同時接合該第三介電膜和該第四介電膜。
在一些實施例中，該製備方法更包括以下步驟：形成至少一第二插塞，其穿過該第三基板且與該些第三金屬線之至少一者接觸；以及形成一第三重分佈層，其與該第二插塞接觸。
在一些實施例中，該製備方法更包括在形成該第三重分佈層之後進行一研磨製程以薄化該第一基板。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。組成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可做為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
以下使用特定語言描述圖式中所示本揭露的實施例或示例。應理解的是，於此並不意圖限制本揭露的範圍。所述實施例的任何改變或修改，以及本文中所述原則的任何進一步應用，對於與本揭露相關之本技術領域具有通常知識者來說，都被視為是會正常發生的。在所有實施例中可以重複使用參考符號，但這不一定意味著一實施例的部件（feature）適用於另一實施例，即使它們使用相同的參考符號。
應理解的是，儘管本文可以使用第一、第二、第三等用詞來描述各種元件、組件、區域、層、或部分，但是這些元件、組件、區域、層、或部分不受限於這些用詞。相反地，這些用詞僅用於區分一個元件、組件、區域、層、或部分與另一元件、組件、區域、層、或部分。因此，在不悖離本揭露概念教示的情況下，以下所討論的第一元件、組件、區域、層、或部分可以被稱為第二元件、組件、區域、層、或部分。
在此使用的用詞僅出於描述特定示例實施例的目的，且不用於限制本揭露之概念。如本文所使用的，除非上下文另外明確指出，單數形式的“一(a/an)”和“該”也包括複數形式。應理解的是，用詞“包括(comprises)”和“包含(comprising)”在本說明書中使用時指出所述之部件、整數、步驟、操作、元件、或構件的存在，但不排除一或多個部件、整數、步驟、操作、元件、構件、或前述之組合的存在或增加。
圖1是根據本揭露的一些實施例顯示一半導體系統10的剖面圖。參照圖1，半導體系統10包括一主基板12和一晶粒組件14，該晶粒組件包括對齊並接合在一起的第一晶粒20a、第二晶粒20b、和第三晶粒20c，其中第三晶粒20c設置於最靠近主基板12處。主基板12可以是電子系統（例如計算機系統）的印刷電路板（printed circuit board; PCB），並且包括用於與晶粒組件14形成物理性和電性連接的複數個佈線墊124。
在一些實施例中，可以使用相同的製程來製造第一晶粒20a、第二晶粒20b、和第三晶粒20c以形成例如記憶體堆疊。然而，可以使用不同的製程來製造第一至第三晶粒20a至20c，以堆疊一或多個記憶體元件和一或多個處理器或專用積體電路（application-specific integrated circuit; ASIC）元件。
距離主基板12最遠的第一晶粒20a包括第一基板210a、設置於第一基板210a的第一前表面212a上的第一層間介電（inter-layer dielectric; ILD）層220a、和位於第一ILD層220a中的複數個第一金屬線230a。在一些實施例中，第一ILD層220a面對主基板12。夾在第一晶粒20a和第三晶粒20c之間的第二晶粒20b包括第二基板210b、設置於第二基板210b的第二前表面212b上且面對第一ILD層220a的第二ILD層220b、以及設置於第二ILD層220b中的複數個第二金屬線230b。第三晶粒20c包括第三基板210c、設置於第三基板210c的第三前表面212c上的第三ILD層220c、以及設置於第三ILD層220c中的複數個第三金屬線230c。
晶粒組件14進一步包括位於第一晶粒20a和第二晶粒20b之間的第一重分佈層（first redistribution layer）32，其用來做為第一晶粒20a和第二晶粒20b的電性內連線。具體地，第一重分佈層32與距離第一基板210a最遠且透過第二ILD層220a而暴露的第一金屬線230a以及透過第二ILD層220b而暴露的第二金屬線230b接觸。在一些實施例中，第一重分佈層32用於接合第一晶粒20a和第二晶粒20b。在一些實施例中，第一介電層46被施加在第一晶粒20a和第二晶粒20b之間並且包圍第一重分佈層32以降低第一重分佈層32的腐蝕。第一介電層46也可以用於接合第一晶粒20a和第二晶粒20b以增加它們之間連接的機械強度。
晶粒組件14也包括用於接合第二晶粒20b和第三晶粒20c的第二重分佈層34，並且包括用來做為與第二晶粒20b和第二重分佈層34電性連接的一或多個第一插塞42。詳細地，第一插塞42穿過第二基板210b並進入第二ILD層220b，並與最靠近第二基板210b的第二金屬線230b接觸。位於第二晶粒20b和第三晶粒20c之間的第二重分佈層34將第一插塞42連接到透過第三ILD層220c而暴露的第三金屬線230c。在一些實施例中，第二介電層48設置於第二晶粒20b和第三晶粒20c之間，並且圍繞第二重分佈層34。
在一些實施例中，晶粒組件14可更包括一或多個第二插塞44，其穿過第三基板210c並進入第三ILD層220c，以將最靠近第三基板210c的第三金屬線230c連接到位於第三基板210c上的第三重分佈層36和圍繞第三重分佈層36的鈍化層50。
在一些實施例中，電性耦合至第三重分佈層36的一或多個銲錫凸塊52位於與佈線墊124對應的位置，以與其形成物理性和電性連接。換句話說，銲錫凸塊52用來做為輸入/輸出（input/output; I/O）連接，以將晶粒組件14電性連接到主基板12。在一些實施例中，一或多個凸塊下金屬（under bump metallization; UBM）構件54包括銅及/或鋁，其夾在第三重分佈層36和銲錫凸塊52之間，以與銲錫凸塊52產生良好的可接合性。
在一些實施例中，晶粒組件14可包括圍繞第一插塞42的第一障壁襯層43和圍繞第二插塞44的第二障壁襯層45。第一障壁襯層43和第二障壁襯層45做為膠層，包括難熔金屬、難熔金屬氮化物、難熔金屬矽氮化物、或前述之組合。
圖2是根據本揭露的一些實施例顯示半導體系統10A的剖面圖。如圖2所示，半導體系統10A包括主基板12和安裝在主基板12上的晶粒組件14A。晶粒組件14A包括對齊並接合在一起的第一至第四晶粒20a至20d，其中第四晶粒20d設置於最靠近主基板12處。在一些實施例中，第一晶粒20a和第二晶粒20b以前對前（front-to-front）的配置方式垂直堆疊，且第二晶粒20b、第三晶粒20c、和第四晶粒20d以前對後（front-to-back）的配置方式垂直堆疊。
晶粒組件14A更包括第一重分佈層32，其用於將第一晶粒20a接合至第二晶粒20b。在一些實施例中，設置於第一晶粒20a的第一ILD層220a和第二晶粒20b的第二ILD層220b之間的第一重分佈層32與透過第一ILD層220a而暴露的第一金屬線230a以及透過第二ILD層220b而暴露的第二金屬線230b接觸。在一些實施例中，被施加以圍繞第一重分佈層32的第一介電層46也用於接合第一晶粒20a和第二晶粒20b。在一些實施例中，第一晶粒20a和第二晶粒20b透過包括第一重分佈層32和第一介電層46的混合接合（hybrid bonding）而接合。
晶粒組件14A更包括第二重分佈層34和一或多個第一插塞42，其共同做為第二晶粒20b與第三晶粒20c的電性連接。第二重分佈層34與透過第三晶粒20c的第三ILD層220c而暴露的第三金屬線230c接觸。第一插塞42穿過第二晶粒20b的第二基板210b並進入第二ILD層220b，將第二重分佈層34連接至位於第二ILD層220b中的第二金屬線230b。在一些實施例中，與第一重分佈層32接觸的第二金屬線230b和與第一插塞42接觸的第二金屬線230b處於不同層中。詳細地，與第一重分佈層32接觸的第二金屬線230b被設置於距離第二基板210b最遠的位置，且與第一插塞42接觸的第二金屬線230b被設置於距離第二基板210b最近的位置。在一些實施例中，位於第二晶粒20b與第三晶粒20c之間的第二重分佈層34和第二介電層48形成用於接合第二晶粒20b和第三晶粒20c的接合界面。
在一些實施例中，晶粒組件14A也包括一或多個第二插塞44，其穿過第四基板210d以將第四金屬線230d連接到第四基板210d上的第三重分佈層36、環繞第三重分佈層36的鈍化層50、電性耦合到第三重分佈層36的一或多個銲錫凸塊52、以及夾在第三重分佈層36和銲錫凸塊52之間的一或多個UBM構件54。
在一些實施例中，第四重分佈層38和一或多個第三插塞46-1共同做為第三晶粒20c與第四晶粒20d的電性連接。更具體地，第四重分佈層38與透過第四晶粒20d的第四ILD層220d而暴露的第四金屬線230d接觸，且第三插塞46-1穿過第三晶粒20c的第三基板210c以將第四重分佈層38連接到第三ILD層220c中的第三金屬線230c。在一些實施例中，施加第四介電層51以圍繞第四重分佈層38並接合第三晶粒20c和第四晶粒20d。
圖3是根據本揭露的一些實施例顯示製造晶粒組件14之方法60流程圖。圖4至圖28是根據本揭露的一些實施例顯示用於製造晶粒組件14之方法60的各個製程階段示意圖。圖4至圖28所示之階段也示意性地顯示於圖3的流程圖中。在隨後的討論中，將參照圖3所示的製程步驟討論圖4至圖28所示之製造階段。
參照圖4，根據圖3的步驟602提供第一晶粒20a。在一些實施例中，第一晶粒20a包括第一基板210a、位於第一基板210a的第一前表面212a上的第一ILD層220a、以及位於第一ILD層220a中的複數個第一金屬線230a。在一些實施例中，第一基板210a包括矽或其他半導體材料，像是第III-V族構件。在一些實施例中，第一基板210a可包括未單獨描繪且結合以形成各種微電子元件、經摻雜區域、和隔離特徵的各種層。在一些實施例中，第一基板210a具有原始厚度T1，其可例如等於或大於775μm。
在一些實施例中，包括一或多個介電層的第一ILD層220a是由氧化物、氮化物、或低介電常數（low-K）介電材料（例如，磷矽酸鹽玻璃、硼磷矽酸鹽玻璃等）組成。在一些實施例中，第一ILD層220a具有大約平坦的頂表面222a。在一些實施例中，可以使用旋塗製程或化學氣相沉積（chemical vapor deposition; CVD）製程來形成第一ILD層220a。
在一些實施例中，形成在第一ILD層220a中的第一金屬線230a提供與微電子元件及/或經摻雜區域的電性連接。在一些實施例中，距離第一基板210a最遠的一些第一金屬線230a透過第一ILD層220a而暴露。透過第一ILD層220a而暴露的第一金屬線230a具有頂表面232a，其與第一ILD層220a的頂表面222a共平面。第一金屬線230a可包括銅、鋁、鎢、或其類似材料。在一些實施例中，第一晶粒20a可進一步包括在不同的層（tier）中連接到第一金屬線230a的複數個通孔（vias）（未顯示），其中圖4所示的第一晶粒20a包括三層的第一金屬線230a；然而，在替代實施例中，第一晶粒20a可包括任何層數的第一金屬線230a。
接下來，沉積毯狀介電質462以覆蓋第一ILD層220a的頂表面222a和第一金屬線230的頂表面232a。使用例如CVD製程形成包括氧化物及/或氮化物的毯狀介電質462。
接下來，提供第一罩幕710於毯狀介電質462上，該第一罩幕710包括一或多個窗口712以暴露毯狀介電質462的一部分，並進行第一蝕刻製程以透過窗口712蝕刻毯狀介電質462。因此，如圖5所示，形成第一介電膜464，且第一金屬線230a的一部分透過第一介電膜464而暴露。在進行第一蝕刻製程之後，移除第一罩幕710。
參照圖6，在一些實施例中，根據圖3中的步驟604，進行電鍍製程以形成第一重繞線層322於透過第一介電膜464而暴露的第一金屬線230a上。在一些實施例中，當以剖面圖觀察時，第一重繞線層322可以位於透過第一介電膜464而暴露的第一金屬線230a的中心軸線C1的中心上。在一些實施例中，第一重繞線層322具有一頂表面3222，其與第一介電膜464的頂表面4642共平面。在一些實施例中，第一重繞線層322可包括銅、鋁、鎢、鈷、鈦、金、鉑、或前述之組合。
參照圖7，在一些實施例中，根據圖3的步驟606，提供第二晶粒20b，並形成第二介電膜466和第二重繞線層324於第二晶粒20b上。在一些實施例中，第二晶粒20b在圖7中上下倒置，其包括第二基板210b、位於第二基板210b的第二前表面212b上的第二ILD層220b、以及設置於第二ILD層220b中的複數個第二金屬線230b。在一些實施例中，第二重繞線層324與第一重繞線層322對齊並且與透過第二ILD層220b而暴露的第二金屬線230b接觸。第二介電膜466環繞第二重繞線層324。在一些實施例中，第二介電膜466和第二重繞線層324的材料和形成方法與第一介電膜464和第一重繞線層322的材料和形成方法基本上相同。
參照圖8，在一些實施例中，根據圖3的步驟608，對齊並接合第二晶粒20b與第一晶粒20a。在第二晶粒20b和第一晶粒20a接合之後，進行退火製程以將第一重繞線層322接合至第二重繞線層324，從而形成第一重分佈層32，並且使第一介電膜464熔融至第二介電膜466，從而形成第一介電層46。在一些實施例中，第二基板210b具有大約755μm的厚度T2。在一些實施例中，第一晶粒20a和第二晶粒20b透過例如混合接合製程（hybrid bonding process）而接合。
參照圖9，在一些實施例中，根據圖3的步驟610，進行第一薄化製程以薄化第二基板210b。在一些實施例中，將第二基板210b薄化以減少用於形成第一插塞的製程時間，如將在下文描述的。在圖9中，將第二基板210b薄化至大約50μm的厚度T3。
參照圖10和圖11，在一些實施例中，根據圖3的步驟612，形成一或多個第一開口240b以暴露出距離第二基板210b最近的第二金屬線230b。在一些實施例中，藉由提供第二罩幕720於相對於第二前表面212b的第二後表面214b上，並進行第二蝕刻製程以移除第二基板210b和第二ILD層220b未被第二罩幕720覆蓋的部分來形成第一開口240b。在進行第二蝕刻製程之後，透過例如灰化製程或濕剝離製程來移除第二罩幕720。
參照圖12，在一些實施例中，根據圖3中的步驟614，可選地沉積第一障壁襯層43於第二後表面214b上和第一開口240b中。在一些實施例中，第一障壁襯層43是實質（substantially）保形的層，並且是使用例如物理氣相沉積（physical vapor deposition; PVD）製程而形成的。
參照圖13，在一些實施例中，根據圖3的步驟616，沉積第一導電材料250b於第一障壁襯層43上。在一些實施例中，藉由使用電鍍製程或CVD製程來將第一導電材料250b沉積於第二後表面214b之上。
參照圖14，在一些實施例中，根據圖3中的步驟618，進行第一平坦化製程以暴露出第二基板210b。據此，形成一或多個第一插塞42。在一些實施例中，將第一障壁襯層43和第一導電材料250b向下平坦化至第二後表面214b。在一些實施例中，第一平坦化製程包括化學機械研磨（chemical mechanical polishing; CMP）製程及/或濕蝕刻製程。
參照圖15，在一些實施例中，根據圖3中的步驟620，沉積第一前驅層342以覆蓋第二後表面214b、第一插塞42、和第一障壁襯層43。在一些實施例中，利用CVD製程、PVD製程、濺鍍製程，蒸發製程、或電鍍製程來形成包括鋁、鎢、鈷、鈦、金、鉑、或前述之合金的第一前驅層342。接下來，提供第三罩幕730於第一前驅層342上以圖案化第一前驅層342。在一些實施例中，第一插塞42設置於第三罩幕730下方。
參照圖16，在一些實施例中，根據圖3中的步驟622，進行第三蝕刻製程以透過第三罩幕730蝕刻第一前驅層342，從而形成第三重繞線層344。在進行第三蝕刻製程之後，移除第三罩幕730。在一些實施例中，當以剖面圖觀察時，第三重繞線層344可以位於第一插塞42的中心軸線C2的中心上。在一些實施例中，第三重繞線層344覆蓋第二後表面214b的一部分。
參照圖17，在一些實施例中，根據圖3中的步驟624，沉積第三介電膜482於第二後表面214b上並圍繞第三重繞線層344。在一些實施例中，第三重繞線層344具有與第三介電膜482的頂表面4822共平面的頂表面3442。在一些實施例中，可以使用CVD製程來形成第三介電膜482。
參照圖18和圖19，在一些實施例中，根據圖3中的步驟626，提供第三晶粒20c，並形成第四重繞線層346和第四介電膜486於第三晶粒20c上。參照圖18，使用例如CVD製程來沉積介電材料484於第三ILD層220c上，然後提供第四罩幕740於介電材料484上以定義用於形成第四重繞線層346的圖案。在一些實施例中，第三ILD層220c設置於第三晶粒20c的第三基板210c上，且具有與透過第三ILD層220c而暴露的第三金屬線230c的頂表面232c共平面的頂表面222c。圖18中的第三基板210c具有大於750μm的厚度T4。
接下來，進行第四蝕刻製程以蝕刻介電材料484，從而形成第四介電膜486。接著，進行電鍍製程以形成第四重繞線層346於透過第四介電膜486而暴露的第三ILD層220c和第三金屬線230c上。在一些實施例中，第四重繞線層346和第三重繞線層344（圖17所示）具有相同的圖案。
參照圖20，在一些實施例中，根據圖3的步驟628，上下倒置的第三晶粒20c堆疊在第二晶粒20b上並與其接合。在一些實施例中，第四重分佈層346與第三重分佈層344對齊。在一些實施例中，第四重分佈層346接合至第三重分佈層344以形成第二重分佈層34，且第三介電膜482接合至第四介電層486以形成第二介電層48。
參照圖21，在一些實施例中，根據圖3的步驟630，進行第二薄化製程以薄化第三基板210c。在圖21中，第三基板210c具有大約50μm的厚度T5。
參照圖22，在一些實施例中，根據圖3的步驟632，形成至少一個第二開口240c以暴露出距離第三基板210c最近的一或多個第三金屬線230c。在一些實施例中，藉由提供第五罩幕750於第三晶粒20c的第三後表面214c上，並進行第五蝕刻製程以移除第三基板210c和第三ILD層220c未被第五罩幕750覆蓋的部分來形成第二開口240c。在進行第五蝕刻製程之後，移除第五罩幕750。
參照圖23，在一些實施例中，根據圖3中的步驟634，可選地沉積第三障壁襯層45於第三後表面214c上和第二開口240c中。在一些實施例中，第二障壁襯層45具有實質均勻的厚度。接下來，根據圖3中的步驟636，沉積第二導電材料250c於第二障壁襯層45上。在一些實施例中，第二障壁襯層45和第二導電材料250c的材料和形成方法與第一障壁襯層43和第一導電材料250b的材料和形成方法基本上相同。
參照圖24，在一些實施例中，根據圖3的步驟638，進行第二平坦化製程以暴露第三後表面214c。據此，形成一或多個第二插塞44。在第二平坦化製程期間移除第二障壁襯層45和第二導電材料250c的一部分以暴露出第三基板210c。
參照圖25和圖26，在一些實施例中，根據圖3的步驟640，沉積第二前驅層362於第三後表面214c、第二插塞44、和第二障壁襯層45上。在一些實施例中，第二前驅層362的材料和形成方法與第一前驅層342的材料和形成方法基本上相同。
接下來，根據圖3的步驟642，提供第六罩幕760於第二前驅層362上，並進行第六蝕刻製程以形成第三重分佈層36。在一些實施例中，第二插塞44設置於第六罩幕760下方。
接下來，沉積鈍化層50於第三基板210c上以覆蓋第三後表面214c並環繞第三重分佈層36。在一些實施例中，可使用CVD製程形成包括氧化物的鈍化層50。在一些實施例中，鈍化層50具有與第三重分佈層36的頂表面36-1（請確認）共平面的頂表面502。
參照圖27，在一些實施例中，根據圖3的步驟644，形成至少一個UBM構件54於第三重分佈層36上，並設置至少一個銲錫凸塊52於UBM構件54上。在一些實施例中，藉由最初將銲錫助熔劑（solder flux）（未顯示）放置於UBM構件54上來安裝銲錫凸塊52，而且一旦銲錫凸塊52與銲錫助熔劑接觸，就可進行回焊以回焊銲錫凸塊52的材料和銲錫助熔劑以將銲錫凸塊52物理性接合至UBM構件54。
參照圖28，在一些實施例中，根據圖3的步驟646，進行研磨製程以薄化第一基板210a。據此，完全地形成晶粒組件14。在一些實施例中，將第一基板210a薄化至厚度T6，例如小於或等於約50μm，以縮小晶粒組件14的整體尺寸。
本揭露的一實施例提供了一種晶粒組件。該晶粒組件包括第一晶粒、第二晶粒、第三晶粒、至少一第一插塞、一第一重分佈層、和一第二重分佈層。第一晶粒包括一第一基板和設置於該第一基板之上的複數個第一金屬線。第二晶粒包括一第二基板和設置於該第二基板之上的複數個第二金屬線，其中該第一晶粒堆疊在該第二晶粒上，且該些第二金屬線面對該些第一金屬線。第三晶粒包括一第三基板和設置於該第三基板之上的複數個第三金屬線，其中該第二晶粒堆疊在該第三晶粒上，且該些第三金屬線面對該第二基板。第一插塞穿過該第二基板以連接到該些第二金屬線之至少一者。第一重分佈層將該些第一金屬線之至少一者物理性連接到該些第二金屬線之至少一者，且第二重分佈層將該些第三金屬線之至少一者物理性連接到該第一插塞。
本揭露的另實施例提供一種晶粒組件的製備方法。該製備方法包括以下步驟：提供一第一晶粒，其包括一第一基板和位於該第一基板之上的複數個第一金屬線；形成一第一重繞線層，其物理性連接到該些第一金屬線之至少一者；提供一第二晶粒，其包括一第二基板和位於該第二基板之上的複數個第二金屬線；形成一第二重繞線層，其與該第一重繞線層對齊且與該些第二金屬線之至少一者接觸；接合該第一重繞線層和該第二重繞線層以形成一第一重分佈層；形成至少一第一插塞，其穿過該第二基板且與該些第二金屬線之至少一者接觸；形成一第三重繞線層，其與該第一插塞接觸；提供一第三晶粒，其包括一第三基板和位於該第三基板之上的複數個第三金屬線；形成一第四重繞線層，其與該第三重繞線層對齊且與該些第三金屬線之至少一者接觸；以及接合該第三重繞線層和該第四重繞線層以形成一第二重分佈層。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或前述之組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中該之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文該之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體系統 10A:半導體系統 12:主基板 14:晶粒組件 14A:晶粒組件 20a:第一晶粒 20b:第二晶粒 20c:第三晶粒 20d:第四晶粒 32:第一重分佈層 34:第二重分佈層 36:第三重分佈層 38:第四重分佈層 42:第一插塞 43:第一障壁襯層 44:第二插塞 45:第二障壁襯層 46:第一介電層 46-1:第三插塞 48:第二介電層 50:鈍化層 51:第四介電層 52:銲錫凸塊 54:凸塊下金屬構件 60:方法 124:佈線墊 210a:第一基板 210b:第二基板 210c:第三基板 212a:第一前表面 212b:第二前表面 212c:第三前表面 214b:第二後表面 214c:第三後表面 220a:第一層間介電（ILD）層 220b:第二ILD層 220c:第三ILD層 222a:頂表面 222c:頂表面 230a:第一金屬線 230b:第二金屬線 230c:第三金屬線 232a:頂表面 232c:頂表面 240b:第一開口 240c:第二開口 250b:第一導電材料 250c:第二導電材料 322:第一重繞線層 324:第二重繞線層 342:第一前驅層 344:第三重繞線層 346:第四重繞線層 36-1:頂表面 362:第二前驅層 462:毯狀介電質 464:第一介電膜 466:第二介電膜 482:第三介電膜 484:介電材料 486:第四介電膜 502:頂表面 602:步驟 604:步驟 606:步驟 608:步驟 610:步驟 612:步驟 614:步驟 616:步驟 618:步驟 620:步驟 622:步驟 624:步驟 626:步驟 628:步驟 630:步驟 632:步驟 634:步驟 636:步驟 638:步驟 640:步驟 642:步驟 644:步驟 650:步驟 710:第一罩幕 712:窗口 720:第二罩幕 730:第三罩幕 740:第四罩幕 750:第五罩幕 760:第六罩幕 3222:頂表面 3442:頂表面 4642:頂表面 4822:頂表面 C1:中心軸線 C2:中心軸線 T1:厚度 T4:厚度 T5:厚度 T6:厚度
本揭露各方面可配合以下圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準慣例，各個部件（feature）並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個部件的尺寸。 圖1是根據本揭露的一些實施例顯示一半導體系統的剖面圖。 圖2是根據本揭露的一些實施例顯示一半導體系統的剖面圖。 圖3是根據本揭露的一些實施例顯示製造一晶粒組件之第一部份方法流程圖。 圖4到圖28是根據本揭露的一些實施例顯示形成一晶粒組件之中間階段的剖面圖。
14:晶粒組件
20a:第一晶粒
20b:第二晶粒
20c:第三晶粒
32:第一重分佈層
34:第二重分佈層
36:第三重分佈層
42:第一插塞
43:第一障壁襯層
44:第二插塞
45:第二障壁襯層
46:第一介電層
48:第二介電層
50:鈍化層
52:銲錫凸塊
54:凸塊下金屬構件
210a:第一基板
210b:第二基板
210c:第三基板
220a:第一層間介電(ILD)層
220b:第二ILD層
220c:第三ILD層
230a:第一金屬線
230b:第二金屬線
230c:第三金屬線
322:第一重繞線層
324:第二重繞線層
344:第三重繞線層
346:第四重繞線層
464:第一介電膜
466:第二介電膜
482:第三介電膜
486:第四介電膜
T6:厚度

Claims (14)

  1. 一種晶粒組件，包括： 一第一晶粒，包括一第一基板和設置於該第一基板之上的複數個第一金屬線； 一第二晶粒，包括一第二基板和設置於該第二基板之上的複數個第二金屬線，其中該第一晶粒堆疊在該第二晶粒上，且該些第二金屬線面對該些第一金屬線； 一第三晶粒，包括一第三基板和設置於該第三基板之上的複數個第三金屬線，其中該第二晶粒堆疊在該第三晶粒上，且該些第三金屬線面對該第二基板； 至少一第一插塞，穿過該第二基板以連接到該些第二金屬線之至少一者； 一第一重分佈層，將該些第一金屬線之至少一者物理性連接到該些第二金屬線之至少一者；以及 一第二重分佈層，將該些第三金屬線之至少一者物理性連接到該第一插塞。
  2. 如請求項1所述之晶粒組件，其中該第一重分佈層與距離該第一基板最遠之該第一金屬線對齊，且該第二重分佈層與該第一插塞對齊。
  3. 如請求項2所述之晶粒組件，更包括： 一第一介電層，位於該第一晶粒和該第二晶粒之間且環繞該第一重分佈層；以及 一第二介電層，位於該第二晶粒和該第三晶粒之間且環繞該第二重分佈層。
  4. 如請求項1所述之晶粒組件，更包括至少一第二插塞，其穿過該第三基板並與該些第三金屬線之至少一者接觸。
  5. 如請求項4所述之晶粒組件，更包括： 一第三重分佈層，與該第二插塞接觸；以及 一鈍化層，環繞該第三重分佈層。
  6. 如請求項5所述之晶粒組件，更包括至少一銲錫凸塊，其電性耦合到該第三重分佈層。
  7. 如請求項4所述之晶粒組件，更包括： 一第一障壁襯層，位於該第二基板和該第一插塞之間，且位於該第二金屬線和該第一插塞之間；以及 一第二障壁襯層，位於該第三基板和該第二插塞之間，且位於該第三金屬線和該第二插塞之間。
  8. 一種晶粒組件的製備方法，包括： 提供一第一晶粒，其包括一第一基板和位於該第一基板之上的複數個第一金屬線； 形成一第一重繞線層，其物理性連接到該些第一金屬線之至少一者； 提供一第二晶粒，其包括一第二基板和位於該第二基板之上的複數個第二金屬線； 形成一第二重繞線層，其與該第一重繞線層對齊且與該些第二金屬線之至少一者接觸； 接合該第一重繞線層和該第二重繞線層以形成一第一重分佈層； 形成至少一第一插塞，其穿過該第二基板且與該些第二金屬線之至少一者接觸； 形成一第三重繞線層，其與該第一插塞接觸； 提供一第三晶粒，其包括一第三基板和位於該第三基板之上的複數個第三金屬線； 形成一第四重繞線層，其與該第三重繞線層對齊且與該些第三金屬線之至少一者接觸；以及 接合該第三重繞線層和該第四重繞線層以形成一第二重分佈層。
  9. 如請求項8所述之晶粒組件的製備方法，更包括： 沈積一毯狀介電質於該第一基板之上且連接到距離該第一基板最遠之該些第一金屬線； 進行一第一蝕刻製程以透過該毯狀介電質暴露出距離該第一基板最遠之該些第一金屬線的一部分，從而形成一第一介電膜；以及 進行一電鍍製程以形成該第一重繞線層於透過該第一介電膜而暴露的該些第一金屬線上。
  10. 如請求項9所述之晶粒組件的製備方法，更包括： 在形成該第二重繞線層之前，沈積一第二介電膜以覆蓋距離該第二基板最遠之該第二金屬線的部分；以及 在接合該第一重繞線層和該第二重繞線層的同時接合該第一介電膜和該第二介電膜。
  11. 如請求項8所述之晶粒組件的製備方法，其中形成該第三重繞線層包括： 沈積一第一前驅層於該第二基板和該第一插塞上；以及 圖案化該第一前驅層以移除該第一前驅層未與該第一插塞接觸的部分； 其中該第三重繞線層與該第一插塞對齊。
  12. 如請求項8所述之晶粒組件的製備方法，更包括： 沈積一第三介電膜以圍繞該第三重繞線層； 在形成該第四重繞線層之前，沈積一第四介電膜以覆蓋距離該第三基板最遠之該第三金屬線的部分；以及 在接合該第三重繞線層和該第四重繞線層的同時接合該第三介電膜和該第四介電膜。
  13. 如請求項8所述之晶粒組件的製備方法，更包括： 形成至少一第二插塞，其穿過該第三基板且與該些第三金屬線之至少一者接觸；以及 形成一第三重分佈層，其與該第二插塞接觸。
  14. 如請求項13所述之晶粒組件的製備方法，更包括在形成該第三重分佈層之後進行一研磨製程以薄化該第一基板。
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