TW202017137A - 用於改善接合性的墊結構 - Google Patents

用於改善接合性的墊結構 Download PDF

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TW202017137A
TW202017137A TW108128804A TW108128804A TW202017137A TW 202017137 A TW202017137 A TW 202017137A TW 108128804 A TW108128804 A TW 108128804A TW 108128804 A TW108128804 A TW 108128804A TW 202017137 A TW202017137 A TW 202017137A
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substrate
pad
conductive
wires
wire
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TW108128804A
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TWI732269B (zh
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黃儒瑛
陳永慶
林月秋
郭彥良
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台灣積體電路製造股份有限公司
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Abstract

本申請案之各項實施例係關於一種具有高強度及接合性之墊。在一些實施例中，一積體晶片包括一基板、一互連結構、一墊及一導電結構。該互連結構鄰接該基板且包括導線及通路。該等導線及該等通路經堆疊於該墊與該基板之間。該導電結構(例如，一導線接合)延伸穿過該基板而至該墊。藉由在該墊與該基板之間配置該等導線及該等通路，可將該墊插入至該互連結構之一鈍化層中且該鈍化層可吸收該墊上之應力。此外，該墊可在一頂部導線層級處接觸該等導線及該等通路。該頂部導線層級之一厚度可超過其他導線層級之一厚度，藉此該頂部導線層級可更耐受應力。

Description

用於改善接合性的墊結構
本發明實施例係有關用於改善接合性的墊結構。
互補金屬氧化物半導體(CMOS)影像感測器用於各種現代電子裝置，舉例而言諸如相機、平板電腦、智慧型電話等等。CMOS影像感測器可為前照式(FSI)或背照式(BSI)。與FSI CMOS影像感測器相比，BSI CMOS影像感測器具有更佳靈敏度、更佳角度回應及更大金屬佈線靈活性。
BSI CMOS影像感測器可為二維(2D)或三維(3D)。一2D BSI CMOS影像感測器包含單個積體晶片中之一像素感測器陣列及相關聯電路，而一3D BSI CMOS影像感測器將像素感測器陣列及相關聯電路分離成接合在一起之單獨積體晶片。與2D BSI CMOS影像感測器相比，3D BSI CMOS影像感測器具有增加之速度、增加之像素密度、更低成本及更小封裝大小。
本發明的一實施例係關於一種積體晶片，其包括：一基板；一互連結構，其鄰接該基板，其中該互連結構包括複數個導線及複數個通路，且其中該等導線及該等通路交替堆疊；一墊，其在該互連結構中，其中該等導線及該等通路位於該墊與該基板之間；及一導電結構，其延伸穿過該基板至該墊。
本發明的一實施例係關於一種積體晶片，其包括：一鈍化層；一墊，其上覆於該鈍化層且凹入至該鈍化層中；一導電柱，其上覆於且接觸該墊，其中該導電柱在一第一閉合路徑中沿該墊之一周邊橫向延伸，且其中導電柱包括導線及通路之一交替堆疊；一半導體基板，其上覆於該導電柱；及一導電結構，其延伸穿過該半導體基板及該導電柱而至該墊。
本發明的一實施例係關於一種方法，其包括：在一基板之一第一側上形成一互連結構，其中該互連結構包括複數個導線及複數個通路，且其中該等導線及該等通路自該基板交替堆疊至一頂部導線層級；在該互連結構上形成一墊，其中該墊突出以與該頂部導線層級接觸；及自該基板之一第二側對該互連結構執行一蝕刻以形成延伸穿過該基板及該互連結構而至該墊之一開口。
本揭露提供用於實施本揭露之不同特徵之不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅僅係實例且並非意欲於限制性。例如，在下文描述中一第一構件形成於一第二構件上方或上可包含其中第一構件及第二構件經形成為直接接觸之實施例，且亦可包含其中額外構件可經形成於第一構件與第二構件之間使得第一構件及第二構件可不直接接觸之實施例。另外，本揭露可在各項實例中重複元件符號及/或字母。此重複出於簡化及清楚之目的且本身不規定所論述之各項實施例及/或組態之間的一關係。
此外，為便於描述，空間相對術語(諸如「在…下面」、「在…下方」、「下」、「在…上方」、「上」及類似者)可在本文中用來描述一個元件或構件與另一(些)元件或構件之關係，如圖中所繪示。空間相對術語意欲於涵蓋除圖中所描繪之定向以外之使用或操作中裝置之不同定向。設備可以其他方式定向(旋轉90度或按其他定向)且據此可同樣解釋本文中所使用之空間相對描述詞。
在一些實施例中，一背照式(BSI)影像感測器包括一基板、一互連結構及一墊結構。基板位於BSI影像感測器之一背側上，且互連結構位於BSI影像感測器之一前側上。互連結構包括複數個導線及複數個通路，且墊結構包括一或多個導電柱及一接合墊。該(等)導電柱位於BSI影像感測器之前側上且由導線及通路界定。接合墊位於BSI影像感測器之背側上且具有一對突起，該對突起延伸穿過基板以在最靠近基板之一導線層級(例如，金屬1)處與該(等)導電柱接觸。在墊結構之第一實施例中，突起突出至一共同導電柱。在墊結構之第二實施例中，突起突出至鄰接且電耦合至一共同導線之單獨導電柱。
在封裝BSI影像感測器期間，BSI影像感測器透過墊結構接合且電耦合至一外部結構。例如，可在接合墊上形成一導電凸塊堆疊或一接合導線以將BSI影像感測器接合且電耦合至外部結構。然而，接合導致接合墊上之大量應力，且例如可導致接合墊處之剝離及/或破裂缺陷。此外，因為接合墊突出以與該(等)導電柱接觸，所以接合墊上之應力經傳送至該(等)導電柱。例如，此可能導致一裂縫缺陷自接合墊傳播至該(等)導電柱及/或例如可導致接合墊之分層。
本申請案之各項實施例係關於一種具有高強度及接合性之墊結構。在一些實施例中，一積體晶片包括一基板、一互連結構及一接合墊。互連結構鄰接基板且包括多個導線及多個通路。導線及通路交替堆疊於接合墊與基板之間。此外，互連結構部分地界定延伸穿過基板且暴露接合墊之一墊開口。藉由在接合墊與基板之間配置導線及通路，可將接合墊插入至互連結構之一鈍化層中且鈍化層可吸收接合墊上之應力。此繼而改善墊結構之強度及接合性且降低接合墊處之剝離及/或破裂缺陷之可能性。此外，接合墊可在互連結構之一頂部導線層級(即，互連結構中最遠離基板之一導線層級)處接觸導線及通路。頂部導線層級之一厚度可超過其他導線層級之一厚度，藉此頂部導線層級可更耐受應力。此繼而進一步改善墊結構之強度及接合性且降低接合墊處之剝離及/或破裂缺陷之可能性。
參考圖1A，提供包括具有改善強度及改善接合性之一墊結構104之一積體晶片102之一些實施例之一剖面圖100A。積體晶片102進一步包括一晶片基板106及一互連結構108。晶片基板106位於積體晶片102之一背側102b上，且互連結構108位於積體晶片102之一前側102f上。互連結構108包括一互連介電質結構110、一鈍化層111、複數個導線112及複數個通路114。為便於繪示，僅將一些導線112標記為112且僅將一些通路114標記為114。互連介電質結構110位於鈍化層111與晶片基板106之間，且導線112及通路114交替堆疊於互連介電質結構110中。
墊結構104位於晶片基板106下方互連結構108中。此外，墊結構104包括一接合墊116及一對導電柱118。接合墊116在鈍化層111與互連介電質結構110之間經插入至鈍化層111中。此外，接合墊116下伏於且鄰接導電柱118以將導電柱118電耦合在一起。在一些實施例中，接合墊116具有分別突出至導電柱118之突起116p。此外，接合墊116藉由一墊開口120暴露。墊開口120延伸穿過晶片基板106及互連結構108而至接合墊116且至少部分由互連結構108界定。導電柱118係由導線112及通路114界定且經配置使得墊開口120位於導電柱118之間。在一些實施例中，當自上而下觀看時，導電柱118係在圍繞接合墊116之一閉合路徑中連續延伸之單個導電結構之區段。當自上而下觀看時，單個導電結構可例如具有一方環形狀、某一其他合適環形狀或某一其他合適閉合路徑形狀。
藉由將接合墊116插入至鈍化層111中，鈍化層111可吸收施加於接合墊116上之應力。此繼而改善墊結構104之強度及接合性且降低接合墊11處之剝離及/或破裂缺陷之可能性。此外，藉由將接合墊116插入至鈍化層111中，接合墊116在互連結構108之一頂部導線層級(即，互連結構108最遠離晶片基板106之一導線層級)處接觸導電柱118。頂部導線層級之一厚度Tw1 超過其他導線層級之一厚度Tw2 ，藉此頂部導線層級更耐受應力且不太可能在應力下破裂。此繼而進一步改善墊結構104之強度及接合性且降低接合墊116處之剝離及/或破裂缺陷之可能性。
在一些實施例中，接合墊116之一厚度TbP 為約0.6千埃至36.0千埃、約0.6千埃至18.0千埃或約18.0千埃至36.0千埃。然而，其他厚度係適合的。若接合墊116之厚度TbP 過小(例如，小於約0.6千埃或某一其他合適值)，則接合墊116將為弱的且易於失效。若接合墊116之厚度TbP 過大(例如，大於約36.0千埃或某一其他合適值)，則材料將被浪費。在一些實施例中，鈍化層111之一厚度Tp 為約10千埃至15千埃、約10.00千埃至12.75千埃或約12.75千埃至15.00千埃。然而，其他厚度係適合的。若鈍化層111之厚度Tp 過小(例如，小於約10千埃或某一其他合適值)，則鈍化層111將缺乏足夠剛性及/或強度以有意義地強化接合墊116。若厚度鈍化層111之Tp 過大(例如，大於約15.0千埃或一些其他合適值)，則材料將被浪費。
在一些實施例中，一隔離結構122在晶片基板106與互連結構108之間延伸至晶片基板106中，且部分地界定墊開口120。隔離結構122包括一介電質材料且可為例如一淺溝槽隔離(STI)結構或某一其他合適隔離結構。在一些實施例中，一緩衝層124在積體晶片102之背側102b上加襯裡於晶片基板106，且部分地界定墊開口120。緩衝層124可例如為或包括氧化矽、氮化矽、氮氧化矽、某一(些)其他合適介電質或前述之任何組合。
在一些實施例中，晶片基板106係一塊體矽基板、一絕緣體上覆矽(SOI)基板或某一其他合適半導體基板。在一些實施例中，互連介電質結構110係或包括氧化矽、一低k介電質、某一(些)其他合適介電質或前述之任何組合。如本文中所使用，一低k介電質可為例如具有小於約3.9、3、2或1之一介電係數k之一介電質。在一些實施例中，鈍化層111係或包括氧化矽、氮化矽、氮氧化矽、某一(些)其他合適介電質或前述之任何組合。在一些實施例中，導線112、通路114及接合墊116係銅、鎢、鋁銅、某一(些)其他合適金屬及/或(若干)導電材料、或前述之任何組合。例如，導線112及通路114可為或包括銅及/或接合墊116可為或包括鋁銅。
在一些實施例中，積體晶片102之前側102f經接合至一支撐基板126。支撐基板126可例如為積體晶片102提供機械支撐以防止翹曲及/或破裂。此繼而可改善墊結構104之強度以防止破裂及/或分層。支撐基板126可例如為一塊體矽基板或某一其他合適基板。在其他實施例中，省略支撐基板126。
參考圖1B，提供圖1A之墊結構104之一些實施例之一頂部佈局100B。例如，可沿線A截取圖1A之剖面圖100A。接合墊116具有一方形佈局，但其他形狀及/或佈局係適合的。圖1A之突起116p係單個突起116p’ (以虛線展示)之區段。單個突起116p’在一閉合路徑中沿接合墊116之一邊界延伸以圍封墊開口120。單個突起116p’可例如具有一方環狀佈局、某一其他合適環形佈局或某一其他合適閉合路徑佈局。
圖1A之導電柱118係單個導電結構118’之區段。單個導電結構118’在一閉合路徑中沿接合墊116之邊界延伸以圍封墊開口120。單個導電結構118’可例如具有一方環狀佈局、某一其他合適環形佈局或某一其他合適閉合路徑佈局。此外，單個導電結構118’係由圖1A之導線112及圖1A之通路界定。導線112經分組成複數個導線層級(例如，圖1A中所繪示之四個導線層級)，且單個導電結構118’部分地由來自導線層級之各者之一導線界定。來自導線層級之各者之導線在一閉合路徑中橫向延伸以圍封墊開口120。此外，來自導線層級之各者之導線可例如具有相同於單個導電結構118’之佈局及/或可例如具有一方環狀佈局、某一其他合適環形佈局或某一其他合適閉合路徑佈局。
參考圖2，提供圖1A之積體晶片102之一些實施例之一放大剖面圖200，其中積體晶片102係或包括一BSI互補金屬氧化物半導體(CMOS)影像感測器或某一其他合適BSI影像感測器。墊結構104之多個例項分別位於積體晶片102之相對側上，且像素感測器202之一陣列位於多個例項之間。為便於繪示，僅將一些像素感測器202標記為202。像素感測器202包括個別光偵測器204及個別傳送電晶體206。為便於繪示，僅將光偵測器204之一者標記為204且僅將傳送電晶體206之一者標記為206。在替代實施例中，省略傳送電晶體206。
光偵測器204位於晶片基板106中且在一些實施例中，包括個別集極區208及個別帽蓋區210。為便於繪示，僅將集極區208之一者標記為208且僅將帽蓋區210之一者標記為210。集極區208及帽蓋區210位於晶片基板106中且具有相反摻雜類型。此外，帽蓋區210具有相同於晶片基板106或光偵測器204定位於其內之井(未展示)之一塊體之摻雜類型。在操作期間，光偵測器204吸收輻射以產生電子電洞對。光偵測器204之PN接面界定分離電子電洞對之電子與電子電洞對之電洞之電場。電子累積在集極區208中，而電洞移動至集極區208之外部。
傳送電晶體206位於晶片基板106上晶片基板106與互連結構108之間。傳送電晶體206包括個別傳送閘極電極212、個別傳送閘極介電質層214及個別源極/汲極區。為便於繪示，僅將傳送閘極電極212之一者標記為212且僅將傳送閘極介電質層214之一者標記為214。傳送閘極電極212分別與傳送閘極介電質層214堆疊在一起。傳送閘極電極212之第一側與集極區208接界，集極區208界定傳送電晶體206之第一源極/汲極區。傳送閘極電極212之第二側與浮動擴散節點(FDN) 216接界，FDN 216界定傳送電晶體206之第二源極/汲極區。為便於繪示，僅將FDN之一者標記為216。
在一些實施例中，隔離結構122將像素感測器202彼此分離。在一些實施例中，彩色濾光器218及/或微透鏡220經堆疊於像素感測器202上方。彩色濾光器218使指定波長之輻射通過同時阻擋其他波長之輻射，且微透鏡220將輻射聚焦於光偵測器204上。
複數個邏輯裝置222位於像素感測器202之陣列與墊結構104之至少一個例項之間。為便於繪示，僅將邏輯裝置222之一者標記為222。邏輯裝置222可例如實施影像信號處理(ISP)電路、讀取/寫入電路、某一其他合適電路或前述之任何組合。在一些實施例中，邏輯裝置222包括個別邏輯閘極電極224、個別邏輯閘極介電質層226及個別源極/汲極區228。為便於繪示，僅將邏輯閘極電極224之一者標記為224，僅將邏輯閘極介電質層226之一者標記為226，且僅將源極/汲極區228之一者標記為228。邏輯閘極電極224及邏輯閘極介電質層226經堆疊於晶片基板106上晶片基板106與互連結構108之間，且源極/汲極區228在晶片基板106中與邏輯閘極電極224接界。在一些實施例中，隔離結構122將邏輯裝置222彼此分離。
參考圖3，提供包括圖1A之積體晶片102 (亦稱為第一積體晶片102)之一三維積體晶片(3DIC) 302之一些實施例之一剖面圖300。3DIC 302進一步包括一第二積體晶片304。第一積體晶片102及第二積體晶片304經堆疊且在第一積體晶片102之前側102f及第二積體晶片304之前側304f處接合在一起。第一積體晶片102包括晶片基板106 (亦稱為第一晶片基板106)及互連結構108 (亦稱為第一互連結構108)。類似於第一積體晶片102，第二積體晶片304包括一第二晶片基板306及一第二互連結構308。
第二晶片基板306位於第二積體晶片304之一背側304b上，且第二互連結構308位於第二積體晶片304之一前側304f上。第二互連結構308包括一第二互連介電質結構310、一第二鈍化層311、複數個第二導線312及複數個第二通路314。為便於繪示，僅將一些第二導線312標記為312且僅將一些第二通路314標記為314。第二互連介電質結構310位於第二鈍化層311與第二晶片基板306之間，且第二導線312及第二通路314交替堆疊於第二互連介電質結構310中。第二導線312及第二通路314界定一對第二導電柱316。第二導電柱316自一共同導線312c延伸至第二晶片基板306且分別位於墊開口120之相對側上。
一對貫穿基板通路(TSV) 318延伸穿過第一積體晶片102而至共同導線312c。TSV 318分別位於墊開口120之相對側上，且第一積體晶片102之導電柱118 (亦稱為第一導電柱118)位於TSV 318之間。此外，TSV 318藉由共同導線312c電耦合在一起，且將共同導線312c電耦合至第一積體晶片102之背側102b上之一對TSV墊320。TSV 318及TSV墊320可例如為或包括銅、鋁銅、鎢、某一(些)其他合適金屬及/或(若干)導電材料、或前述之任何組合。在替代實施例中，省略TSV 318及TSV墊320。
在一些實施例中，一第二隔離結構322在第二晶片基板306與第二互連結構308之間延伸至第二晶片基板306中。第二隔離結構322包括一介電質材料且可為例如一STI結構或某一其他合適隔離結構。
在一些實施例中，第二晶片基板306係一塊體矽基板、一SOI基板或某一其他合適半導體基板。在一些實施例中，第二互連介電質結構310係或包括氧化矽、一低k介電質、某一(些)其他合適介電質或前述之任何組合。在一些實施例中，第二鈍化層311係或包括氧化矽、氮化矽、氮氧化矽、某一(些)其他合適介電質或前述之任何組合。在一些實施例中，第二導線312及導線通路314係銅、鎢、鋁銅、某一(些)其他合適金屬及/或(若干)導電材料、或前述之任何組合。
參考圖4，提供圖3之3DIC 302之一些更詳細實施例之一剖面圖400，其中第一互連介電質結構110及第二互連介電質結構310包括多個層。第一互連介電質結構110及第二互連介電質結構310包括個別層間介電質(ILD)層402及個別金屬間介電質(IMD)層404。為便於繪示，僅將一些IMD層404標記為404。ILD層402分別與第一晶片基板106及第二晶片基板306接界，且IMD層404位於第一鈍化層111及第二鈍化層311與ILD層402之間。ILD層402及IMD層404可例如為或包括一低k介電質及/或某一(些)其他合適介電質。
在一些實施例中，第一互連介電質結構110及第二互連介電質結構310進一步包括個別蝕刻停止層406，個別蝕刻停止層406將IMD層404彼此分離，分離IMD層404與ILD層402且分離IMD層404與第一鈍化層111及第二鈍化層131。為便於繪示，僅將一些蝕刻停止層406標記為406。蝕刻停止層406可例如為或包括碳化矽、氮化矽、氮氧化矽、某一(些)其他合適介電質材料、或前述之任何組合。
雖然圖4繪示且描述使用圖3之3DIC 302之第一互連介電質結構110及第二互連介電質結構310之多層實施例，但應明白，多層實施例可用於圖1A及圖2之任一者中之積體晶片102中。
參考圖5，提供圖3之3DIC 302之一些實施例之一放大剖面圖500，其中3DIC 302係或包括一3D BSI CMOS影像感測器或某一其他合適3D BSI影像感測器。墊結構104之多個例項分別位於3DIC 302之相對側上，且像素感測器202之一陣列位於多個例項之間。為便於繪示，僅將一些像素感測器202標記為202。在一些實施例中，第一積體晶片102之隔離結構122將像素感測器202彼此分離。此外，在一些實施例中，彩色濾光器218及/或微透鏡220經堆疊於像素感測器202上方。像素感測器202、彩色濾光器218、微透鏡220或前述之任何組合可例如如關於圖2所描述般。
複數個邏輯裝置222位於第二晶片基板306上第二晶片基板306與第二互連結構308之間。為便於繪示，僅將一些邏輯裝置222標記為222。邏輯裝置222可例如實施ISP電路、讀取/寫入電路、某一其他合適電路或前述之任何組合。此外，邏輯裝置222可例如如關於圖2所描述般。
在一些實施例中，一混合接合結構502位於第一積體晶片102與第二積體晶片304之間以提供第一積體晶片102與第二積體晶片304之間的接合及電耦合。混合接合結構502包括第一鈍化層111及第二鈍化層311中之混合接合墊504及混合接合通路506。為便於繪示，僅將混合接合墊504之一者標記為504且僅將混合接合通路506之一者標記為506。混合接合墊504及混合接合通路506可為或包括例如銅、鋁、鋁銅、某一(些)其他合適金屬及/或(若干)導電材料、或前述之任何組合。在替代實施例中，省略混合接合結構502。在替代實施例中，省略TSV 318。
參考圖6A，提供一積體晶片封裝之一些實施例之一剖面圖600A，其中圖3之3DIC 302藉由導線接合電耦合至一封裝基板602。在一些實施例中，封裝基板602係陶瓷或某一其他合適絕緣材料。封裝基板602包括一封裝墊604，且一接合導線606自封裝墊604延伸至3DIC 302之接合墊116。接合導線606可例如為或包括銅、鋁、鋁銅、(若干)一些合適金屬及/或(若干)導電材料、或前述之任何組合。
接合導線606之形成可將高應力施加於接合墊116上。因為接合墊116經插入至第一鈍化層111中，所以第一鈍化層111吸收施加於接合墊116上之應力。此繼而降低接合墊116處之剝離及/或破裂缺陷之可能性。此外，因為接合墊116在第一互連結構108之頂部導線層級處接觸導電柱118，所以不太可能在此介面處破裂。頂部導線層級厚於其他導線層級且因此更耐受應力且不太可能破裂。
在一些實施例中，接合導線606之一厚度TbW 為約1密耳、約2密耳或某一其他合適厚度。若接合導線606之厚度TbW 過薄(例如，小於約1密耳或某一其他合適值)，則接合導線606可為弱的且易於破裂及/或斷裂。若接合導線606之厚度TbW 過大(例如，大於約2密耳或某一其他合適值)，則接合導線606將過於剛硬且在形成期間將大量應力施加於接合墊116上。在一些實施例中，墊開口120之一寬度Wpo 大於約60微米及/或墊開口120之一頂部佈局係方形。例如，當接合導線606之厚度TbW 為約1密耳或某一其他合適值時，可出現此等實施例。在其他實施例中，墊開口120之寬度Wpo 具有某一其他合適值及/或墊開口120之頂部佈局具有某一其他合適形狀。
參考圖6B，提供圖6A之積體晶片封裝之一些替代實施例之一剖面圖600B，其中圖3之3DIC 302藉由覆晶接合電耦合至封裝基板602。封裝基板602懸伸於墊開口120之上且導電凸塊608自接合墊116堆疊至封裝墊604。為便於繪示，僅將導電凸塊608之一者標記為608。導電凸塊608可例如為或包括金、銀、銅、鋁、鋁銅、某一(些)其他合適金屬及/或導電材料、或前述之任何組合。
參考圖7A及圖7B，分別提供圖6A及圖6B之積體晶片封裝之一些實施例之放大剖面圖700A、700B，其中積體晶片封裝包括圖5之3DIC 302。
雖然圖6A及圖6B使用圖3中之3DIC 302之實施例，但可代替地使用圖4中之實施例。類似地，雖然圖6A及圖6B中使用圖3中之3DIC 302，但可代替地使用圖1A中之積體晶片102 (具有或無支撐基板126)。雖然圖7A及圖7B使用圖5中之3DIC 302，但可代替地使用圖2中之積體晶片102 (具有或無支撐基板126)。
參考圖8至圖23、圖24A及圖24B，提供用於形成包括具有改善強度及接合性之一墊結構之一積體晶片封裝之一方法之一些實施例之一系列剖面圖800至2300、2400A、2400B。該方法之第一實施例自圖8至圖23前進至圖24A (且略過圖24B)以形成圖7A之積體晶片封裝，而該方法之第二實施例自圖8至圖23前進至圖24B (且略過圖24A)以形成圖7B之積體晶片封裝。
如由圖8之剖面圖800所繪示，在一第一晶片基板106上形成一第一隔離結構122及複數個像素感測器202。為便於繪示，僅將第一隔離結構122之一些區段標記為122且僅將像素感測器202之一者標記為202。第一隔離結構122將像素感測器202彼此分離且鄰接第一晶片基板106之一墊區106p。像素感測器202包括個別光偵測器204及個別傳送電晶體206。為便於繪示，僅將光偵測器204之一者標記為204且僅將傳送電晶體206之一者標記為206。光偵測器204及/或傳送電晶體206可例如如關於所圖2描述般。
在一些實施例中，用於形成第一隔離結構122之一程序包括：1)圖案化第一晶片基板106以形成具有第一隔離結構122之一佈局之隔離溝槽；及2)用一介電質材料填充隔離溝槽。在一些實施例中，用於形成像素感測器202之一程序包括：1)沉積堆疊於第一隔離結構122及第一晶片基板106上方之一介電質層及一導電層；2)將介電質層及導電層圖案化成傳送閘極電極212及傳送閘極介質層214；及3)執行一系列摻雜程序以形成與傳送閘極電極212接界之光偵測器204及FDN 216。為便於繪示，僅將傳送閘極電極212之一者標記為212，僅將傳送閘極介電質層214之一者標記為214，且僅將FDN 216之一者標記為216。
如由圖9之剖面圖900所繪示，在第一晶片基板106上部分地形成一第一互連結構108。第一互連結構108包括一第一互連介電質結構110、複數個第一導線112及複數個第一通路114。為便於繪示，僅將一些第一導線112標記為112且僅將一些第一通路114標記為114。第一導線112及第一通路114交替堆疊於互連介電質結構110中且界定自像素感測器202引出之導電路徑。此外，第一導線112及第一通路114界定上覆於第一晶片基板106之墊區106p之一對導電柱118。
在一些實施例中，用於部分地形成第一互連結構108之一程序包括：1)藉由單鑲嵌程序形成通路114之一最底層級；2)藉由單鑲嵌程序形成導線112之一最底層級；3)藉由重複執行雙鑲嵌程序在導線112之最底層級上方形成導線及通路；及4)形成第一互連介電結構110覆蓋導線112之一最頂層級之一頂部部分。然而，用於形成第一互連結構108之其他程序係適合的。在一些實施例中，單鑲嵌程序包括：1)沉積一介電質層；2)圖案化介電質層使之具有用於單個導電構件層級(例如，一通路層級或一導線層級)之開口；及3)用導電材料填充開口以形成單個導電構件層級。在一些實施例中，雙鑲嵌程序包括：1)沉積一介電質層；2)圖案化介電質層使之具有用於兩個導電構件層級(例如，一通路層級及一導線層級)之開口；及3)用導電材料填充開口以形成兩個導電構件層級。在單鑲嵌程序及雙鑲嵌程序兩者中，介電質層對應於第一互連介電質結構110之一部分。在一些實施例中，藉由氣相沉積及/或某一(些)其他合適沉積程序形成第一互連介電質結構110覆蓋導線112之最頂層級之頂部部分。
如由圖10之剖面圖1000所繪示，圖案化第一互連介電質結構110以形成分別上覆於且暴露導電柱118之墊突起開口1002。例如，可藉由一光微影/蝕刻程序或某一其他合適圖案化程序執行圖案化。在一些實施例中，光微影/蝕刻程序包括：1)在第一互連介電質結構110上形成具有墊突起開口1002之一佈局之一光阻劑遮罩1004；2)在光阻劑遮罩1004位於適當位置之情況下將一蝕刻劑1006施加至第一互連介電質結構110；及3)剝除光阻劑遮罩1004。
如由圖11之剖面圖1100所繪示，在第一互連介電質結構110上沉積一接合墊層1102，從而填充墊突起開口1002 (參見圖10)。接合墊層1102可例如為或包括銅、鋁、鋁銅、某一(些)其他合適導電材料或前述之任何組合。在一些實施例中，藉由化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍、無電電鍍、某一(些)其他合適沉積製程或前述之任何組合執行沉積。在一些實施例中，沉積係保形的及/或使得接合墊層1102在墊突起開口1002處具有凹痕1102i。
如由圖12之剖面圖1200所繪示，圖案化接合墊層1102 (參見圖11)以形成上覆於第一晶片基板106之墊區106p之一接合墊116。此外，接合墊116經形成而突出以在墊突起開口1002處與導電柱118接觸(參見圖10)。例如，可藉由一光微影/蝕刻程序或某一其他合適圖案化程序執行圖案化。在一些實施例中，光微影/蝕刻程序包括：1)在接合墊層1102上形成具有接合墊116之一佈局之一光阻劑遮罩1202；2)在光阻劑遮罩1202位於適當位置之情況下將一蝕刻劑1204施加至接合墊層1102；及3)剝除光阻劑遮罩1202。
如由圖13之剖面圖1300所繪示，圍繞接合墊116完成第一互連結構108，由此界定一第一積體晶片102。在完成第一互連結構108時，在接合墊116及第一互連介電質結構110上方形成一第一鈍化層111及一第一混合接合結構502a。在替代實施例中，省略第一混合接合結構502a。第一混合接合結構502a包括第一混合接合墊504a及第一混合接合通路506a。為便於繪示，僅將第一混合接合墊504a之一者標記為504a且僅將第一混合接合通路506a之一者標記為506a。第一混合接合墊504a及第一混合接合通路506a經堆疊於第一鈍化層111中，且第一混合接合通路506a將第一混合接合墊504a電耦合至第一導線112之一最頂層級。為便於繪示，僅將一些第一導線112標記為112。
在一些實施例中，用於完成第一互連結構108之一程序包括：1)沉積第一鈍化層111；2)圖案化第一鈍化層111使之具有用於第一混合接合墊504a及第一混合接合通路506a之開口；及3)用導電材料填充開口以形成第一混合接合墊504a及第一混合接合通路506a。在其他實施例中，用於完成第一互連結構108之一程序包括：1)沉積第一鈍化層111之一第一部分；2)圖案化第一部分使之具有用於第一混合接合通路506a之通路開口；3)用導電材料填充通路開口以形成第一混合接合通路506a；4)沉積第一鈍化層111之一第二部分；5)圖案化第二部分使之具有用於第一混合接合墊504a之墊開口；及6)用導電材料填充墊開口以形成第一混合接合墊504a。
如由圖14之剖面圖1400所繪示，提供或以其他方式形成一第二積體晶片304。第二積體晶片304可例如如關於圖3及/或圖5所描述般。第二積體晶片304包括一第二晶片基板306、複數個邏輯裝置222及一第二互連結構308。為便於繪示，僅將邏輯裝置222之一者標記為222。
邏輯裝置222上覆於第二晶片基板306且在一些實施例中，藉由一第二隔離結構322彼此分離。第二互連結構308上覆於第二晶片基板306及邏輯裝置222。此外，第二互連結構308包括一第二互連介電質結構310、一第二鈍化層311、複數個第二導線312、複數個第二通路314及一第二混合接合結構502b。為便於繪示，僅將一些第二導線312標記為312且僅將一些第二通路314標記為314。在替代實施例中，省略第二混合接合結構502b。第二導線312及第二通路314經堆疊於第二互連介電質結構310中，且第二混合接合結構502b位於第二鈍化層311中。第二混合接合結構502b包括第二混合接合墊504b及第二混合接合通路506b。為便於繪示，僅將第二混合接合墊504b之一者標記為504b且僅將第二混合接合通路506b之一者標記為506b。
亦由圖14之剖面圖1400所繪示，第一積體晶片102及第二積體晶片304在第一互連結構108及第二互連結構308處接合在一起。例如，可藉由直接接合、混合接合或某一其他合適接合程序執行接合。在替代實施例中，第一積體晶片102經接合至一支撐基板126 (參見例如圖2)而非第二積體晶片304。
如由圖15之剖面圖1500所繪示，薄化第一晶片基板106以減小第一晶片基板106之一厚度Tfcs 。例如，可藉由一化學機械平坦化(CMP)或某一其他合適薄化程序執行薄化。
如由圖16之剖面圖1600所繪示，圖案化第一晶片基板106以形成上覆於接合墊116且暴露第一隔離結構122之一第一墊開口1602。例如，可藉由一光微影/蝕刻程序或某一其他合適圖案化程序執行圖案化。在一些實施例中，光微影/蝕刻程序包括：1)在第一晶片基板106上形成具有第一墊開口1602之一佈局之光阻劑遮罩1604；2)在光阻劑遮罩1604位於適當位置之情況下將一蝕刻劑1606施加至第一晶片基板106；及3)剝除光阻劑遮罩1604。
如由圖17之剖面圖1700所繪示，在第一晶片基板106上形成一緩衝層124及一硬遮罩層1702。緩衝層124經形成而覆蓋第一晶片基板106及加襯裡於第一墊開口1602 (參見圖16)，而硬遮罩層1702經形成而覆蓋緩衝層124且填充緩衝層124上方之第一墊開口1602。此外，硬遮罩層1702經形成有一平坦或平坦化頂部表面。例如，可藉由CVD、PVD或一些合適沉積程序形成緩衝層124。例如，可藉由沉積硬遮罩層1702且隨後對硬遮罩層1702執行一平坦化以使硬遮罩層1702之頂表面變平或以其他方式平坦化來形成硬遮罩層1702。例如，可藉由CVD、PVD或某一合適沉積程序執行硬遮罩層1702之沉積。例如，可藉由一CMP或某一其他合適平坦化程序執行平坦化。
如由圖18之剖面圖1800所繪示，圖案化硬遮罩層1702以分別在接合墊116之相對側上界定TSV墊開口1802。例如，可藉由一光微影/蝕刻程序或某一其他合適圖案化程序執行圖案化。在一些實施例中，光微影/蝕刻程序包括：1)在硬遮罩層1702上形成具有TSV墊開口1802之一佈局之一光阻劑遮罩1804；2)在光阻劑遮罩1804位於適當位置之情況下將一蝕刻劑1806施加至硬遮罩層1702；及3)剝除光阻劑遮罩1804。
如由圖19之剖面圖1900所繪示，圖案化第一積體晶片102及第二積體晶片304以形成一對TSV開口1902，該對TSV開口1902延伸穿過第一晶片基板106、第一互連介電質結構110、第一鈍化層111及第二鈍化層311而至第二導線312之一最頂層級。例如，可藉由一光微影/蝕刻程序或某一其他合適圖案化程序執行圖案化。在一些實施例中，光微影/蝕刻程序包括：1)在硬遮罩層1702上形成具有TSV開口1902之一佈局之一光阻劑遮罩1904；2)在光阻劑遮罩1904位於適當位置之情況下將一或多種蝕刻劑1906施加至第一積體晶片102及第二積體晶片304；及3)剝除光阻劑遮罩1904。
如由圖20之剖面圖2000所繪示，形成覆蓋硬遮罩層1702且填充TSV開口1902 (參見圖19)及TSV墊開口1802 (參見圖18)之一TSV層2002。例如，可藉由CVD、PVD、無電電鍍、電鍍、某一(些)其他合適沉積程序或前述之任何組合形成TSV層2002。
如由圖21之剖面圖2100所繪示，對TSV層2002 (參見圖20)執行一平坦化以分別在TSV開口1902 (參見圖19)及TSV墊開口1802 (參見圖18)中形成TSV 318及TSV墊320。為便於繪示，僅將TSV墊320之一者標記為320且僅將TSV 318之一者標記為318。此外，應注意，TSV 318與TSV墊320之間的雜湊係不同的以更佳地繪示TSV墊320及TSV 318，儘管TSV墊320及TSV 318兩者係由TSV層2002形成。例如，可藉由一CMP或某一其他合適平坦化程序執行平坦化。
如由圖22之剖面圖2200所繪示，移除硬遮罩層1702 (參見圖21)。例如，可藉由一蝕刻程序或某一其他合適移除程序執行移除。
亦由圖22之剖面圖2200所繪示，圖案化緩衝層124、第一隔離結構122及第一互連介電質結構110以界定上覆於且暴露接合墊116之一第二墊開口120。例如，可藉由一光微影/蝕刻程序或某一其他合適圖案化程序執行圖案化。在一些實施例中，光微影/蝕刻程序包括：1)在緩衝層124上形成具有第二墊開口120之一佈局之一光阻劑遮罩2202；2)在光阻劑遮罩2202位於適當位置之情況下將一或多種蝕刻劑2204施加至第一積體晶片102；及3)剝除光阻劑遮罩2202。
如由圖23之剖面圖2300所繪示，形成堆疊於像素感測器202上方之彩色濾光器218及微透鏡220。為便於繪示，僅將彩色濾光器218之一者標記為218且僅將微透鏡220之一者標記為220。
如由圖24A之剖面圖2400A所繪示，提供包括一封裝墊604之一封裝基板602。此外，將封裝基板602接合至第二晶片基板306且執行導線接合以形成自接合墊116至封裝墊604之一接合導線606。在替代實施例中，如由圖24B之剖面圖2400B所繪示，執行覆晶接合而非導線接合。因此，一對導電凸塊608自接合墊116堆疊至封裝墊604。
圖24A及圖24B處之接合可將高應力施加於接合墊116上。因為接合墊116經插入至第一鈍化層111中，所以第一鈍化層111吸收施加於接合墊116上之應力。此繼而降低接合墊116處之剝離及/或破裂缺陷之可能性。此外，因為接合墊在頂部導線層級處接觸第一導線112，所以不太可能在此介面處破裂。頂部導線層級厚於其他導線層級，且因此更耐受應力且不太可能破裂。
儘管使用圖7A及圖7B之積體晶片封裝繪示該方法，但可使用該方法(具有或無修改)來形成圖6A及圖6B之任一者中之積體晶片封裝，圖3A、圖4及圖5之任一者中之3DIC 302，及圖1及圖2之任一者中之積體晶片102。此外，雖然參考該方法描述圖8至圖23、圖24A及圖24B所展示之剖面圖800至2300、2400A及2400B，但將明白，圖8至圖23、圖24A及圖24B所展示之結構不限於該方法且可獨立於該方法。
參考圖25，提供圖8至圖23、圖24A及圖24B之方法之一些實施例之一方塊圖2500。
在2502處，在一晶片基板上形成像素感測器及一隔離結構。參見例如圖8。
在2504處，在晶片基板上部分地形成一互連結構，其中互連結構包括上覆於晶片基板之一墊區之一對導電柱。參見例如圖9。
在2506處，在互連結構上形成一接合墊，其中接合墊上覆於墊區且突出至導電柱。參見例如圖10至圖12。
在2508處，圍繞接合墊完成互連結構，其中完成包括形成覆蓋接合墊之一鈍化層。參見例如圖13。
在2510處，將一積體晶片接合至互連結構。參見例如圖14。在替代實施例中，使用一支撐基板(參見例如圖1A及圖2A中之126)代替積體晶片。
在2512處，薄化晶片基板。參見例如圖15。
在2514處，圖案化晶片基板以形成上覆於墊區且暴露隔離結構之一第一墊開口。參見例如圖16。
在2516處，形成覆蓋晶片基板且加襯裡於第一墊開口之一緩衝層。參見例如圖17。
在2518處，形成延伸穿過晶片基板及互連結構而至積體晶片之TSV，同時在TSV上形成TSV墊。參見例如圖18至圖21。
在2520處，圖案化隔離結構及互連結構以形成暴露接合墊之一第二墊開口。參見例如圖22。
在2522處，形成堆疊於像素感測器上方之彩色濾光器及微透鏡。參見例如圖23。
在2524處，藉由導線接合或覆晶接合將接合墊接合至一封裝墊。參見例如圖24A及圖24B。
雖然圖25之方塊圖2500在本文中被繪示且描述為一系列動作或事件，但將明白，此等動作或事件之所繪示排序不應被解釋為限制意義。例如，一些動作可以不同順序發生及/或與除本文中所繪示及/或描述之彼等動作或事件以外之其他動作或事件同時發生。此外，可能不需要所有所繪示動作來實施本文中所描述之一或多個態樣或實施例，且本文中所描繪之一或多個動作可在一或多個單獨動作及/或階段中實行。
在一些實施例中，本申請案提供一種積體晶片，其包含：一基板；一互連結構，其鄰接該基板，其中該互連結構包含複數個導線及複數個通路，且其中該等導線及該等通路交替堆疊；及一墊，其在該互連結構中，其中該等導線及該等通路位於該墊與該基板之間，且其中該互連結構部分地界定延伸穿過該基板且暴露該墊之一墊開口。在一些實施例中，該積體晶片進一步包含位於該墊開口中且接觸該墊之一接合導線。在一些實施例中，該積體晶片進一步包含位於該墊開口中且接觸該墊之一導電凸塊。在一些實施例中，當在剖面中觀看時，該等導線及該等通路界定一第一導電柱及一第二導電柱，其中該第一導電柱及該第二導電柱分別位於該墊開口之相對側上且鄰接該墊。在一些實施例中，該等導線經分組成多個導線層級，包含一第一導線層級及一第二導線層級，其中該墊突出以在該第一導線層級處與該第一導電柱及該第二導電柱接觸，且其中該第一導線層級具有大於該第二導線層級之一厚度。在一些實施例中，該積體晶片進一步包含在該基板與該互連結構之間延伸至該基板中之一隔離結構，其中該隔離結構包含一介電質材料且部分地界定該墊開口。在一些實施例中，該積體晶片進一步包含位於該基板上該基板與該互連結構之間之像素感測器，其中該等像素感測器包含該基板中之光偵測器，且其中該等導線及該等通路界定自該等像素感測器延伸之導電路徑。在一些實施例中，該積體晶片進一步包含：一第二基板；一第二互連結構，其在該互連結構與該第二基板之間鄰接該第二基板，其中該第二互連結構包含複數個第二導線及複數個第二通路，且其中該等第二導線及該等第二通路交替堆疊；及一第一TSV，其延伸穿過該基板及該互連結構而至該等第二導線之一者。在一些實施例中，該積體晶片進一步包含延伸穿過該基板及該互連結構而至該等第二導線之該一者之一第二TSV，其中該第一TSV及該第二TSV分別位於該墊開口之相對側上。在一些實施例中，當在剖面中觀看時，該等第二導線及該等第二通路界定一第一導電柱及一第二導電柱，其中該第一導電柱及該第二導電柱自該等第二導線之該一者延伸至該第二基板且分別位於該墊開口之相對側上。
在一些實施例中，本申請案提供一種積體晶片封裝，其包含：一積體晶片，其包含一互連結構及一晶片墊，其中該晶片墊係在該互連結構中，其中該互連結構包含多個導線及多個通路，其中該等導線及該等通路交替堆疊且界定鄰接該晶片墊之一第一導電結構，且其中該互連結構界定延伸穿過該導電結構且暴露該晶片墊之一開口；一封裝基板；一封裝墊，其在該封裝基板中；及一第二導電結構，其自該晶片墊延伸至該封裝墊，且進一步電耦合該晶片墊及該封裝墊。在一些實施例中，該第二導電結構包含一接合導線。在一些實施例中，該第二導電結構包含一對導電凸塊，其中該等導電凸塊彼此疊置於該開口中。在一些實施例中，該封裝基板纏繞於該積體晶片之一頂部隅角且包含一懸伸部分，其中該懸伸部分容納該封裝墊且懸伸於該晶片墊及該第二導電結構之上。在一些實施例中，該積體晶片進一步包含：一晶片基板；及一STI結構，其在該晶片基板與該互連結構之間延伸至該晶片基板中，其中該STI結構部分地界定該開口。
在一些實施例中，本申請案提供另一積體晶片，其包含：一基板；一互連結構，其鄰接該基板，其中該互連結構包含複數個導線及複數個通路，且其中該等導線及該等通路交替堆疊；一墊，其在該互連結構中，其中該等導線及該等通路位於該墊與該基板之間；及一導電結構，其延伸穿過該基板而至該墊。在一些實施例中，該導電結構包含接觸該墊之一接合導線。在一些實施例中，該導電結構包含接觸該墊之一導電凸塊。在一些實施例中，當在剖面中觀看時，該等導線及該等通路界定一第一導電柱及一第二導電柱，其中該第一導電柱及該第二導電柱鄰接該墊，且其中導電結構位於該第一導電柱與該第二導電柱之間。在一些實施例中，該等導線經分組成多個導線層級，包含一第一導線層級及一第二導線層級，其中該墊突出以在該第一導線層級處與該第一導電柱及該第二導電柱接觸，且其中該第一導線層級具有大於該第二導線層級之一厚度。在一些實施例中，該互連結構進一步包含具有一互連介電質側壁之一互連介電質層，其中該積體晶片進一步包含：一隔離結構，其在該基板與該互連結構之間延伸至該基板中，其中該隔離結構包含一介電質材料且具有一隔離結構側壁，且其中該隔離結構側壁與該互連介電質側壁對準且面向該導電結構。在一些實施例中，該積體晶片進一步包含該基板上該基板與該互連結構之間的像素感測器，其中該等像素感測器包含該基板中之光偵測器，且其中該等導線及該等通路界定自該等像素感測器延伸之導電路徑。在一些實施例中，該積體晶片進一步包含：一第二基板；一第二互連結構，其在該互連結構與該第二基板之間鄰接該第二基板，其中該第二互連結構包含複數個第二導線及複數個第二通路，且其中該等第二導線及該等第二通路交替堆疊；及一第一TSV，其延伸穿過該基板及該互連結構而至該等第二導線之一者。在一些實施例中，該積體晶片進一步包含延伸穿過該基板及該互連結構而至該等第二導線之該一者之一第二TSV，其中該導電結構位於該第一TSV與該第二TSV之間。在一些實施例中，當在剖面中觀看時，該等第二導線及該等第二通路界定一第一導電柱及一第二導電柱，其中該第一導電柱及該第二導電柱自該等第二導線之該一者延伸至該第二基板，且其中該導電結構橫向位於該第一導電柱與該第二導電柱之間。
在一些實施例中，本申請案提供另一積體晶片，其包含：一鈍化層；一墊，其上覆於該鈍化層且凹入至該鈍化層中；一導電柱，其上覆於且接觸該墊，其中該導電柱在一第一閉合路徑中沿該墊之一周邊橫向延伸，且其中導電柱包含導線及通路之一交替堆疊；一半導體基板，其上覆於該導電柱；及一導電結構，其延伸穿過該半導體基板及該導電柱而至該墊。在一些實施例中，該墊具有突出至該導電柱之一向上突起，其中該向上突起在一第二閉合路徑中沿該墊之周邊橫向延伸。在一些實施例中，該導電柱之一頂部佈局係環形的。在一些實施例中，導線及通路之該交替堆疊包含一第一層級導線及一第二層級導線，其中該第一層級導線接觸該墊且具有一第一厚度，且其中該第二層級導線上覆於該第一層級導線且具有小於該第一厚度之一第二厚度。在一些實施例中，該第一層級導線及該第二層級導線各沿該墊之該周邊橫向延伸以完全環繞該導電結構。
在一些實施例中，本申請案提供一種方法，其包含：在一基板之一第一側上形成一互連結構，其中該互連結構包含複數個導線及複數個通路，且其中該等導線及該等通路自該基板交替堆疊至一頂部導線層級；在該互連結構上形成一墊，其中該墊突出以與該頂部導線層級接觸；自該基板之一第二側對該互連結構執行一蝕刻以形成延伸穿過該基板及該互連結構而至該墊之一開口。在一些實施例中，該方法進一步包含形成上覆於且接觸該墊及該互連結構之一鈍化層。在一些實施例中，該互連結構及該基板至少部分界定一第一積體晶片，其中該方法進一步包含：形成包含一第二互連結構及一第二基板之一第二積體晶片；及將該第一積體晶片及該第二積體晶片接合在一起，使得該互連結構及該第二互連結構位於該基板與該第二基板之間。在一些實施例中，該第二互連結構包含一導線，其中該方法進一步包含：對該基板、該互連結構及該第二互連結構執行一第二蝕刻以形成暴露該導線之兩個通路開口，其中該墊位於該等通路開口之間；及用導電材料填充該等通路開口以界定TSV。在一些實施例中，該方法進一步包含在該基板上形成像素感測器，其中該互連結構係在形成該等像素感測器之後形成且覆蓋該等像素感測器。
前述內容概述若干實施例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應明白，其等可容易使用本揭露作為設計或修改用於實行本文中所介紹之實施例之相同目的及/或達成相同優點之其他程序及結構之一基礎。熟習此項技術者亦應認知，此等等效構造不背離本揭露之精神及範疇，且其等可在不背離本揭露之精神及範疇之情況下在本文中作出各種改變、置換及更改。
100A:剖面圖 100B:頂部佈局 102:第一積體晶片 102b:背側 102f:前側 104:墊結構 106:第一晶片基板 106p:墊區 108:第一互連結構 110:第一互連介電質結構 111:第一鈍化層 112:第一導線 114:第一通路 116:接合墊 116p:突起 116p’:突起 118:第一導電柱 118’:導電結構 120:第二墊開口 122:第一隔離結構 124:緩衝層 126:支撐基板 200:放大剖面圖 202:像素感測器 204:光偵測器 206:傳送電晶體 208:集極區 210:帽蓋區 212:傳送閘極電極 214:傳送閘極介電質層 216:浮動擴散節點(FDN) 218:彩色濾光器 220:微透鏡 222:邏輯裝置 224:邏輯閘極電極 226:邏輯閘極介電質層 228:源極/汲極區 300:剖面圖 302:三維積體晶片(3DIC) 304:第二積體晶片 304b:背側 304f:前側 306:第二晶片基板 308:第二互連結構 310:第二互連介電質結構 311:第二鈍化層 312:第二導線 312c:共同導線 314:第二通路 316:第二導電柱 318:貫穿基板通路(TSV) 320:貫穿基板通路(TSV)墊 322:第二隔離結構 400:剖面圖 402:層間介電質(ILD)層 404:金屬間介電質(IMD)層 406:蝕刻停止層 500:放大剖面圖 502:混合接合結構 502a:第一混合接合結構 502b:第二混合接合結構 504:混合接合墊 504a:第一混合接合墊 504b:第二混合接合墊 506:混合接合通路 506a:第一混合接合通路 506b:第二混合接合通路 600A:剖面圖 600B:剖面圖 602:封裝基板 604:封裝墊 606:接合導線 608:導電凸塊 700A:放大剖面圖 700B:放大剖面圖 800:剖面圖 900:剖面圖 1000:剖面圖 1002:墊突起開口 1004:光阻劑遮罩 1006:蝕刻劑 1100:剖面圖 1102:接合墊層 1102i:凹痕 1200:剖面圖 1202:光阻劑遮罩 1204:蝕刻劑 1300:剖面圖 1400:剖面圖 1500:剖面圖 1600:剖面圖 1602:第一墊開口 1604:光阻劑遮罩 1606:蝕刻劑 1700:剖面圖 1702:硬遮罩層 1800:剖面圖 1802:貫穿基板通路(TSV)墊開口 1804:光阻劑遮罩 1806:蝕刻劑 1900:剖面圖 1902:貫穿基板通路(TSV)墊開口 1904:光阻劑遮罩 1906:蝕刻劑 2000:剖面圖 2002:貫穿基板通路(TSV)層 2100:剖面圖 2200:剖面圖 2202:光阻劑遮罩 2204:蝕刻劑 2300:剖面圖 2400A:剖面圖 2400B:剖面圖 2500:方塊圖 2502:步驟 2504:步驟 2506:步驟 2508:步驟 2510:步驟 2512:步驟 2514:步驟 2516:步驟 2518:步驟 2520:步驟 2522:步驟 2524:步驟 TbP:厚度 TbW:厚度 Tfcs:厚度 TP:厚度 Tw1:厚度 Tw2:厚度 Wpo:寬度
當結合附圖閱讀時，自下文詳細描述最好地理解本揭露之態樣。應注意，根據標準行業實踐，各種構件不一定按比例繪製。事實上，為清楚論述起見，可任意增大或減小各種構件之尺寸。
圖1A及圖1B繪示包括具有改善強度及接合性之一墊結構之積體晶片之一些實施例之各種視圖。
圖2繪示圖1A之積體晶片之一些實施例之一放大剖面圖，其中積體晶片包括一影像感測器。
圖3繪示包括圖1A之積體晶片之一三維積體晶片(3DIC)之一些實施例之一剖面圖。
圖4繪示圖3之3DIC中之一互連介電質結構之一些更詳細實施例之一剖面圖。
圖5繪示圖3之3DIC之一些實施例之一放大剖面圖，其中3DIC包括一影像感測器。
圖6A及圖6B繪示積體晶片封裝之一些實施例之剖面圖，其中圖3之3DIC藉由導線接合及覆晶接合電耦合至一封裝基板。
圖7A及圖7B繪示圖6A及圖6B之積體晶片封裝之一些實施例之放大剖面圖，其中積體晶片封裝包括圖5之3DIC。
圖8至圖23、圖24A及圖24B繪示用於形成包括具有改善強度及接合性之一墊結構之一積體晶片封裝之一方法之一些實施例之一系列剖面圖。
圖25繪示圖8至圖23、圖24A及圖24B之方法之一些實施例之一方塊圖。
102:第一積體晶片
104:墊結構
106:第一晶片基板
108:第一互連結構
110:第一互連介電質結構
111:第一鈍化層
116:接合墊
118:第一導電柱
120:第二墊開口
122:第一隔離結構
124:緩衝層
302:三維積體晶片(3DIC)
304:第二積體晶片
306:第二晶片基板
308:第二互連結構
310:第二互連介電質結構
311:第二鈍化層
312:第二導線
314:第二通路
318:貫穿基板通路(TSV)
320:貫穿基板通路(TSV)墊
322:第二隔離結構
600A:剖面圖
602:封裝基板
604:封裝墊
606:接合導線
TbW:厚度
Wpo:寬度

Claims (20)

  1. 一種積體晶片，其包括： 一基板； 一互連結構，其鄰接該基板，其中該互連結構包括複數個導線及複數個通路，且其中該等導線及該等通路交替堆疊； 一墊，其在該互連結構中，其中該等導線及該等通路位於該墊與該基板之間；及 一導電結構，其延伸穿過該基板而至該墊。
  2. 如請求項1之積體晶片，其中該導電結構包括接觸該墊之一接合導線。
  3. 如請求項1之積體晶片，其中該導電結構包括接觸該墊之一導電凸塊。
  4. 如請求項1之積體晶片，其中當在剖面中觀看時，該等導線及該等通路界定一第一導電柱及一第二導電柱，其中該第一導電柱及該第二導電柱鄰接該墊，且其中導電結構位於該第一導電柱與該第二導電柱之間。
  5. 如請求項4之積體晶片，其中該等導線經分組成多個導線層級，包含一第一導線層級及一第二導線層級，其中該墊突出以在該第一導線層級處與該第一導電柱及該第二導電柱接觸，且其中該第一導線層級具有大於該第二導線層級之一厚度。
  6. 如請求項1之積體晶片，其中該互連結構進一步包括具有一互連介電質側壁之一互連介電質層，且其中該積體晶片進一步包括： 一隔離結構，其在該基板與該互連結構之間延伸至該基板中，其中該隔離結構包括一介電質材料且具有一隔離結構側壁，且其中該隔離結構側壁與該互連介電質側壁對準且面向該導電結構。
  7. 如請求項1之積體晶片，其進一步包括： 像素感測器，其等位於該基板上該基板與該互連結構之間，其中該等像素感測器包括該基板中之光偵測器，且其中該等導線及該等通路界定自該等像素感測器延伸之導電路徑。
  8. 如請求項1之積體晶片，其進一步包括： 一第二基板； 一第二互連結構，其在該互連結構與該第二基板之間鄰接該第二基板，其中該第二互連結構包括複數個第二導線及複數個第二通路，且其中該等第二導線及該等第二通路交替堆疊；及 一第一貫穿基板通路(TSV)，其延伸穿過該基板及該互連結構而至該等第二導線之一者。
  9. 如請求項8之積體晶片，其進一步包括： 一第二TSV，其延伸穿過該基板及該互連結構而至該等第二導線之該一者，其中該導電結構位於該第一TSV與該第二TSV之間。
  10. 如請求項8之積體晶片，其中當在剖面中觀看時，該等第二導線及該等第二通路界定一第一導電柱及一第二導電柱，其中該第一導電柱及該第二導電柱自該等第二導線之該一者延伸至該第二基板，且其中該導電結構橫向位於該第一導電柱與該第二導電柱之間。
  11. 一種積體晶片，其包括： 一鈍化層； 一墊，其上覆於該鈍化層且凹入至該鈍化層中； 一導電柱，其上覆於且接觸該墊，其中該導電柱在一第一閉合路徑中沿該墊之一周邊橫向延伸，且其中導電柱包括導線及通路之一交替堆疊； 一半導體基板，其上覆於該導電柱；及 一導電結構，其延伸穿過該半導體基板及該導電柱而至該墊。
  12. 如請求項11之積體晶片，其中該墊具有突出至該導電柱之一向上突起，且其中該向上突起在一第二閉合路徑中沿該墊之該周邊橫向延伸。
  13. 如請求項11之積體晶片，其中該導電柱之一頂部佈局係環形的。
  14. 如請求項11之積體晶片，其中導線及通路之該交替堆疊包括一第一層級導線及一第二層級導線，其中該第一層級導線接觸該墊且具有一第一厚度，且其中該第二層級導線上覆於該第一層級導線且具有小於該第一厚度之一第二厚度。
  15. 如請求項14之積體晶片，其中該第一層級導線及該第二層級導線各沿該墊之該周邊橫向延伸以完全環繞該導電結構。
  16. 一種製造積體晶片的方法，其包括： 在一基板之一第一側上形成一互連結構，其中該互連結構包括複數個導線及複數個通路，且其中該等導線及該等通路自該基板交替堆疊至一頂部導線層級； 在該互連結構上形成一墊，其中該墊突出以與該頂部導線層級接觸；及 自該基板之一第二側對該互連結構執行一蝕刻以形成延伸穿過該基板及該互連結構而至該墊之一開口。
  17. 如請求項16之方法，其進一步包括： 形成上覆於且接觸該墊及該互連結構之一鈍化層。
  18. 如請求項16之方法，其中該互連結構及該基板至少部分地界定一第一積體晶片，且其中該方法進一步包括： 形成包括一第二互連結構及一第二基板之一第二積體晶片；及 將該第一積體晶片及該第二積體晶片接合在一起，使得該互連結構及該第二互連結構位於該基板與該第二基板之間。
  19. 如請求項18之方法，其中該第二互連結構包括一導線，且其中該方法進一步包括： 對該基板、該互連結構及該第二互連結構執行一第二蝕刻以形成暴露該導線之兩個通路開口，其中該墊位於該等通路開口之間；及 用導電材料填充該等通路開口以界定貫穿基板通路(TSV)。
  20. 如請求項16之方法，其進一步包括： 在該基板上形成像素感測器，其中該互連結構係在該等像素感測器之該形成之後形成且覆蓋該等像素感測器。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10903142B2 (en) * 2018-07-31 2021-01-26 Intel Corporation Micro through-silicon via for transistor density scaling
CN110023956A (zh) * 2019-02-28 2019-07-16 深圳市汇顶科技股份有限公司 光学图像采集单元、光学图像采集系统和电子设备
US11282769B2 (en) * 2020-06-11 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Oversized via as through-substrate-via (TSV) stop layer
JP2022045192A (ja) 2020-09-08 2022-03-18 キオクシア株式会社 半導体装置およびその製造方法
CN114765125A (zh) * 2021-01-12 2022-07-19 联华电子股份有限公司 集成电路结构及其制作方法
CN113066781B (zh) * 2021-03-23 2024-01-26 浙江集迈科微电子有限公司 转接板堆叠模组、三维模组和堆叠工艺

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362531B1 (en) 2000-05-04 2002-03-26 International Business Machines Corporation Recessed bond pad
US7741716B1 (en) * 2005-11-08 2010-06-22 Altera Corporation Integrated circuit bond pad structures
JP4609497B2 (ja) * 2008-01-21 2011-01-12 ソニー株式会社 固体撮像装置とその製造方法、及びカメラ
JP4655137B2 (ja) * 2008-10-30 2011-03-23 ソニー株式会社 半導体装置
JP5442394B2 (ja) 2009-10-29 2014-03-12 ソニー株式会社 固体撮像装置とその製造方法、及び電子機器
US8283754B2 (en) * 2010-08-13 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with metal pad
US8664736B2 (en) * 2011-05-20 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad structure for a backside illuminated image sensor device and method of manufacturing the same
US9013022B2 (en) * 2011-08-04 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips
US9773732B2 (en) * 2013-03-06 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for packaging pad structure
JP6120094B2 (ja) 2013-07-05 2017-04-26 ソニー株式会社 固体撮像装置およびその製造方法、並びに電子機器
TWI676279B (zh) 2013-10-04 2019-11-01 新力股份有限公司 半導體裝置及固體攝像元件
JP2015076502A (ja) 2013-10-09 2015-04-20 ソニー株式会社 半導体装置およびその製造方法、並びに電子機器
JP6200835B2 (ja) * 2014-02-28 2017-09-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
TWI676280B (zh) * 2014-04-18 2019-11-01 日商新力股份有限公司 固體攝像裝置及具備其之電子機器
US9704827B2 (en) * 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure
CN108370423B (zh) * 2016-01-18 2021-04-20 索尼公司 固态摄像元件和电子设备
US10297631B2 (en) 2016-01-29 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Metal block and bond pad structure
US10109666B2 (en) * 2016-04-13 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for backside illuminated (BSI) image sensors

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