CN114765125A - 集成电路结构及其制作方法 - Google Patents

集成电路结构及其制作方法 Download PDF

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Publication number
CN114765125A
CN114765125A CN202110034672.4A CN202110034672A CN114765125A CN 114765125 A CN114765125 A CN 114765125A CN 202110034672 A CN202110034672 A CN 202110034672A CN 114765125 A CN114765125 A CN 114765125A
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China
Prior art keywords
layer
dielectric layer
aluminum
copper
integrated circuit
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CN202110034672.4A
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Inventor
陈艺夫
任驰
刘宜欣
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202110034672.4A priority Critical patent/CN114765125A/zh
Priority to US17/160,400 priority patent/US11901318B2/en
Publication of CN114765125A publication Critical patent/CN114765125A/zh
Priority to US18/398,204 priority patent/US20240128214A1/en
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Abstract

本发明公开一种集成电路结构及其制作方法，其中该集成电路结构包含一基底，其上包含一电路区域；一铜互连结构，设置在所述基底上，其中，所述铜互连结构包含被一介电层覆盖的一最上层铜层；一铝接垫层，设置在所述介电层上；以及一金属层，设置在所述电路区域上并且位于所述最上层铜层和所述铝接垫层之间。

Description

集成电路结构及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种具有屏蔽层(shield layer)的集成电路(IC)结构及其制作方法。
背景技术
集成电路(IC)芯片通常包括多层(例如3～12层)金属互连结构，其被设置在基底(例如，硅基底)上。这些金属互连结构可以是以深次微米(例如，小于100nm)设计规则所制作的高密度金属图案，例如铜镶嵌互连结构。在铜镶嵌互连结构之上，另有单一层由铝金属所构成的接垫(bonding pad)或用来扇出(fan out)输出输入(input/output，I/O)端点的重布线层(RDL)。
IC芯片可能遭受各种安全性攻击，其中未授权方试图截取在IC芯片中处理或存储的机密信息。过去，为了保护IC芯片并阻止施加到IC芯片上的攻击，主要是在由铝金属所构成的接垫层中设置一屏蔽层。然而，随着高效能运算芯片和人工智能芯片的发展，为了加大频宽(bandwidth)，结果是IC芯片上的I/O端点数量大幅增加，这导致要在单一层铝金属层上同时制作出屏蔽层和接垫变得十分困难。
发明内容
本发明的主要目的在于提供一种改良的集成电路结构及其制作方法，以解决上述现有技术的不足和缺点。
本发明一方面提供一种集成电路结构，包含一基底，其上包含一电路区域；一铜互连结构，设置在所述基底上，其中，所述铜互连结构包含被一介电层覆盖的一最上层铜层；一铝接垫层，设置在所述介电层上；以及一金属层，设置在所述电路区域上并且位于所述最上层铜层和所述铝接垫层之间。
根据本发明实施例，所述金属层是一铝屏蔽金属层。
根据本发明实施例，所述铝屏蔽金属层通过一钨通孔电连接到所述最上层铜层。
根据本发明实施例，所述钨通孔的宽度为
Figure BDA0002893671380000021
微米。
根据本发明实施例，所述介电层包含一下介电层和一上介电层，其中所述钨通孔设置在所述下介电层中。
根据本发明实施例，所述上介电层覆盖所述铝屏蔽金属层。
根据本发明实施例，所述铝屏蔽金属层的宽度约为
Figure BDA0002893671380000022
微米。
根据本发明实施例，所述上介电层和所述下介电层是由相同的介电材料所组成的。
根据本发明实施例，所述上介电层和所述下介电层包含氧化硅。
根据本发明实施例，所述铝接垫层通过一铝通孔电连接到所述金属层。
根据本发明实施例，所述的集成电路结构另包含一钝化层，部分覆盖所述铝接垫层并且部分覆盖所述介电层。
根据本发明实施例，所述钝化层包括一磷硅玻璃层和一氮化硅层。
本发明另一方面提供一种形成集成电路结构的方法，包含：提供一基底，其上包含一电路区域；在所述基底上形成一铜互连结构，其中所述铜互连结构包含被一介电层覆盖的一最上层铜层；在所述电路区域内的所述最上层铜层上形成一金属层；以及在所述介电层上形成一铝接垫层。
根据本发明实施例，所述金属层是一铝屏蔽金属层。
根据本发明实施例，所述铝屏蔽金属层通过一钨通孔电连接到所述最上层铜层。
根据本发明实施例，所述钨通孔的宽度为
Figure BDA0002893671380000023
微米。
根据本发明实施例，在所述电路区域内的所述最上层铜层上形成所述金属层包含：形成一下介电层；在所述下介电层中形成所述钨通孔；在所述下介电层上形成所述铝屏蔽金属层；以及在所述铝屏蔽金属层和所述下介电层上形成所述上介电层。
根据本发明实施例，所述上介电层比所述下介电层厚。
根据本发明实施例，所述上介电层和所述下介电层是由相同的介电材料所组成的。
根据本发明实施例，所述的方法另包含：形成一钝化层，部分覆盖所述铝接垫层并且部分覆盖所述介电层。
附图说明
图1为本发明实施例所绘示的集成电路结构的部分剖视图；
图2为铝屏蔽金属层的上视图；
图3为钨通孔、铝绕线图案和最上层铜层的局部布局和相关尺寸的示意图；
图4至图7为本发明实施例所绘示的形成集成电路结构的方法示意图。
主要元件符号说明：
100 基底
110～118 介电层
118L 下介电层
118U 上介电层
120 钝化层
121 磷硅玻璃层
122 氮化硅层
AL 铝接垫层
AP、ARP 接垫图案
ARL 重布线层
AV、ARV 铝通孔
C 插塞
CRP 电路区域
CR 电路区域
D1、D2 电路元件
DD 掺杂区
DF 导电区
DP、DI 铜互连结构
OP、OPP 开孔
PC 插塞
PM1、PM2、PM3、M1、M2、M3 铜金属层
PV1、PV2、V1、V2 铜金属通孔
S1、S2 距离
SL 铝屏蔽金属层
SLR 铝绕线图案
SLP 铝接垫
W1、W2 宽度
WH、ARVH、AVH 通孔
WV 钨通孔
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人员得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1，其为依据本发明实施例所绘示的集成电路结构的部分剖视图，如图1所示，本发明集成电路结构1包含一基底100，例如硅基底。在基底100上可以有一电路区域CRP和一电路区域CR。根据本发明实施例，电路区域CRP可以是存储有机密信息而需要被保护的电路区域，例如，嵌入式存储器区域，但不限于此。根据本发明实施例，例如，电路区域CR可以是逻辑核心(logic core)电路区域或其它功能电路区块，但不限于此。
根据本发明实施例，在电路区域CRP和电路区域CR内的基底100上可以分别形成有至少一电路元件D1和至少一电路元件D2。根据本发明实施例，例如，电路元件D1可以是嵌入式闪存存储单元，而电路元件D2可以是场效晶体管(field effect transistor)，但不限于此。本领域技术人员应能理解图1中的电路元件D1和电路元件D2的数量和结构仅为例示说明。
根据本发明实施例，在基底100上另设置有多层介电层110～118，例如，氧化硅、氮化硅或低介电常数(low-k)材料层等。举例来说，介电层110可以是硅氧层，介电层111和113可以是掺杂碳氮化硅(SiCN)层，介电层112可以是氟硅玻璃(fluorosilicate glass，FSG)层，介电层114和116可以是硅氧层，介电层115和117可以是氮化硅层，但不限于此。
根据本发明实施例，在电路区域CRP内的多层介电层110～118中形成有至少一铜互连结构DP。根据本发明实施例，例如，铜互连结构DP可以包含铜金属层PM1、PM2和PM3，其中铜金属层PM1可以通过插塞PC电连接至基底100上的导电区DF，铜金属层PM2可以通过铜金属通孔PV1电连接至铜金属层PM1，而铜金属层PM3可以通过铜金属通孔PV2电连接至铜金属层PM2。本领域技术人员应能理解图1中的铜互连结构DP的金属层数量和结构仅为例示说明。
根据本发明实施例，铜金属层PM1和插塞PC可以形成在介电层110中，铜金属层PM2和铜金属通孔PV1可以形成在介电层111和112中，铜金属层PM3和铜金属通孔PV2可以形成在介电层113～116中。根据本发明实施例，铜互连结构DP可以通过铜镶嵌(copperdamascene)制作工艺形成，由于铜镶嵌制作工艺为公知技术，故其细节不另赘述。在此实施例中，铜金属层PM3是铜互连结构DP的最上层铜层。在完成铜金属层PM3的化学机械研磨(CMP)后，最后会以介电层117将铜金属层PM3的铜表面覆盖住，以避免其氧化。
同样的，在电路区域CR内的多层介电层110～118中可以形成有至少一铜互连结构DI。根据本发明实施例，例如，铜互连结构DI可以包含铜金属层M1、M2和M3，其中铜金属层M1可以通过插塞C电连接至基底100上的掺杂区DD，铜金属层M2可以通过铜金属通孔V1电连接至铜金属层M1，而铜金属层M3可以通过铜金属通孔V2电连接至铜金属层M2。
根据本发明实施例，铜互连结构DP和铜互连结构DI的最上层铜层：铜金属层PM3和铜金属层M3，是被介电层118覆盖住的。根据本发明实施例，介电层118可以包含氧化硅层。根据本发明实施例，介电层可以包含一下介电层118L和一上介电层118U。根据本发明实施例，上介电层118L和下介电层118U可以是由相同的介电材料所组成的。根据本发明实施例，例如，上介电层118L和下介电层118U都包含氧化硅。在其它实施例中，上介电层118L和下介电层118U可以是由不同的介电材料所组成的。根据本发明实施例，上介电层118U比下介电层118L厚。
根据本发明实施例，在介电层118上设置有一铝接垫层AL。例如，铝接垫层AL在电路区域CR内可以包含一接垫图案AP，经由形成在介电层118和介电层117中的铝通孔AV电连接至铜金属层M3。例如，铝接垫层AL在电路区域CRP内可以包含一接垫图案ARP和一重布线层ARL，而铝接垫层AL经由形成在上介电层118U中的铝通孔ARV电连接至一铝屏蔽金属层SL。根据本发明实施例，铝屏蔽金属层SL直接设置在电路区域CRP上方，并且位于最上层铜层PM3和铝接垫层AL之间，用来保护电路区域CRP。根据本发明实施例，铝屏蔽金属层SL可以包含至少一铝绕线图案SLR和至少一铝接垫SLP，而铝通孔ARV直接设置在铝接垫SLP上。
图2例示铝屏蔽金属层SL的上视图。根据本发明实施例，如图2所示，铝屏蔽金属层SL可以是由多圈同心圆状的铝绕线图案SLR所构成，其范围可以与电路区域CRP重叠，但不限于此。铝绕线SLR的布局图案可以依据实际设计需求而定。本领域技术人员应能理解图2中的铝绕线SLR数量和布局仅为例示说明。如图2所示，例如，用来与铝通孔ARV电连接的铝接垫SLP可以被设置在铝屏蔽金属层SL的同一侧边上，但不限于此。
根据本发明实施例，如图1所示，集成电路结构1可以另包含一钝化层120，部分覆盖铝接垫层AL并且部分覆盖介电层118。根据本发明实施例，钝化层120可以包括一磷硅玻璃层121和一氮化硅层122，但不限于此。钝化层120中可以包含一开孔OP，显露出部分的接垫图案AP，以及一开孔OPP，显露出部分的接垫图案ARP。
根据本发明实施例，如图1所示，铝屏蔽金属层SL的铝绕线图案SLR可以通过至少一钨通孔WV电连接到最上层铜层PM3。根据本发明实施例，钨通孔WV设置在下介电层118L中。由于连接铝绕线图案SLR和最上层铜层PM3之间的导通孔的尺寸较小，而铝金属制作工艺的填孔能力或阶梯覆盖(step coverage)能力较差，为了避免铝金属制作工艺无法完全填满如此小的导通孔，导致缺陷问题，故本发明采用钨通孔来电连接铝绕线图案SLR和最上层铜层PM3。
图3例示钨通孔WV、铝绕线图案SLR和最上层铜层PM3的局部布局和相关尺寸。根据本发明实施例，如图3所示，钨通孔WV的宽度W1约为
Figure BDA0002893671380000061
微米，钨通孔WV之间的距离S1约为0.7～1.5微米。此外，铝绕线图案SLR的宽度(线宽)W2约为
Figure BDA0002893671380000062
微米，铝绕线图案SLR之间的距离S2约为0.5～2微米。
请参阅图4至图7，其为依据本发明实施例所绘示的形成集成电路结构的方法示意图，其中，相同的区域、层或元件仍沿用相同的符号来表示。如图4所示，首先提供基底100，其上包含电路区域CRP和电路区域CR。接着，分别在电路区域CRP和电路区域CR内的基底100上形成铜互连结构DP和铜互连结构DI，其中铜互连结构DP包含被介电层117覆盖的最上层铜层PM3，铜互连结构DI包含被介电层117覆盖的最上层铜层M3。本领域技术人员应能理解图4中的铜互连结构DP和DI的金属层数量和结构仅为例示说明。
根据本发明实施例，在基底100上依序以化学气相沉积(chemical vapordeposition，CVD)制作工艺沉积多层介电层110～118，例如，氧化硅、氮化硅或低介电常数材料层等。举例来说，介电层110可以是硅氧层，介电层111和113可以是掺杂碳氮化硅层，介电层112可以是氟硅玻璃层，介电层114和116可以是硅氧层，介电层115和117可以是氮化硅层，但不限于此。
根据本发明实施例，铜互连结构DP分别形成在电路区域CRP内的多层介电层110～118中。根据本发明实施例，例如，铜互连结构DP可以包含铜金属层PM1、PM2和PM3，其中铜金属层PM1可以通过插塞PC电连接至基底100上的导电区DF，铜金属层PM2可以通过铜金属通孔PV1电连接至铜金属层PM1，而铜金属层PM3可以通过铜金属通孔PV2电连接至铜金属层PM2。
根据本发明实施例，铜金属层PM1和插塞PC可以形成在介电层110中，铜金属层PM2和铜金属通孔PV1可以形成在介电层111和112中，铜金属层PM3和铜金属通孔PV2可以形成在介电层113～116中。根据本发明实施例，铜互连结构DP可以通过铜镶嵌制作工艺形成，由于铜镶嵌制作工艺为公知技术，故其细节不另赘述。在此实施例中，在完成铜金属层PM3的化学机械研磨后，最后会以介电层117将铜金属层PM3的铜表面覆盖住，以避免其氧化。
如图5所示，接着可以进行化学气相沉积制作工艺，在介电层117的表面上全面沉积下介电层118L，例如，硅氧层。接着，进行光刻及蚀刻制作工艺，在电路区域CRP内的下介电层118L中形成至少一通孔WH，然后，再进行钨金属沉积制作工艺，例如，以化学气相沉积方法，在通孔WH内填满钨金属层，再进行化学机械研磨制作工艺，研磨掉通孔WH以外的多余钨金属层，如此在下介电层118L中形成钨通孔WV。根据本发明实施例，钨通孔WV的宽度为
Figure BDA0002893671380000071
微米。
如图6所示，接着进行铝金属沉积制作工艺，在下介电层118L上和钨通孔WV上全面沉积铝金属层。根据本发明实施例，例如，铝金属层的厚度可以介于0.3～0.7微米，但不限于此。然后，再进行光刻及蚀刻制作工艺，将铝金属层图案化，形成铝屏蔽金属层SL。根据本发明实施例，铝屏蔽金属层SL直接设置在电路区域CRP上方，用来保护电路区域CRP。根据本发明实施例，铝屏蔽金属层SL可以包含至少一铝绕线图案SLR和至少一铝接垫SLP。根据本发明实施例，铝屏蔽金属层SL通过钨通孔WV电连接到最上层铜层PM3。接着，在铝屏蔽金属层SL和下介电层118L上沉积上介电层118U。根据本发明实施例，上介电层118U比下介电层118L厚。根据本发明实施例，上介电层118U和下介电层118L可以是由相同的介电材料所组成的。
如图7所示，接着进行光刻及蚀刻制作工艺，分别在电路区域CRP和电路区域CR内的介电层118中形成通孔ARVH和通孔AVH，其中，通孔ARVH仅形成在上介电层118U中，而通孔AVH则是贯穿上介电层118U、下介电层118L和介电层117。根据本发明实施例，通孔ARVH和通孔AVH分别显露出部分的铝接垫SLP和铜金属层M3。接着，进行铝金属沉积制作工艺，在通孔ARVH和通孔AVH内和介电层118上形成铝金属层，其厚度大于铝屏蔽金属层SL的厚度，接着以光刻和蚀刻制作工艺图案化铝金属层，形成铝接垫层AL。例如，铝接垫层AL在电路区域CR内可以包含接垫图案AP，经由形成在介电层118和介电层117中的铝通孔AV电连接至铜金属层M3，铝接垫层AL在电路区域CRP内可以包含接垫图案ARP和重布线层ARL，而铝接垫层AL经由形成在上介电层118L中的铝通孔ARV电连接至铝屏蔽金属层SL。
根据本发明实施例，最后沉积钝化层120，部分覆盖铝接垫层AL并且部分覆盖介电层118。根据本发明实施例，钝化层120可以包括磷硅玻璃层121和氮化硅层122，但不限于此。钝化层120中可以包含开孔OP，显露出部分的接垫图案AP，以及开孔OPP，显露出部分的接垫图案ARP。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种集成电路结构，其特征在于，包含：
基底，其上包含电路区域；
铜互连结构，设置在所述基底上，其中，所述铜互连结构包含被介电层覆盖的最上层铜层。
铝接垫层，设置在所述介电层上；以及
金属层，设置在所述电路区域上并且位于所述最上层铜层和所述铝接垫层之间。
2.根据权利要求1所述的集成电路结构，其中所述金属层是铝屏蔽金属层。
3.根据权利要求2所述的集成电路结构，其中所述铝屏蔽金属层通过钨通孔电连接到所述最上层铜层。
4.根据权利要求3所述的集成电路结构，其中所述钨通孔的宽度为
Figure FDA0002893671370000012
Figure FDA0002893671370000013
微米。
5.根据权利要求3所述的集成电路结构，其中所述介电层包含下介电层和上介电层，其中所述钨通孔设置在所述下介电层中。
6.根据权利要求5所述的集成电路结构，其中所述上介电层覆盖所述铝屏蔽金属层。
7.根据权利要求5所述的集成电路结构，其中所述铝屏蔽金属层的宽度约为
Figure FDA0002893671370000011
微米。
8.根据权利要求5所述的集成电路结构，其中所述上介电层和所述下介电层是由相同的介电材料所组成的。
9.根据权利要求5所述的集成电路结构，其中所述上介电层和所述下介电层包含氧化硅。
10.根据权利要求1所述的集成电路结构，其中所述铝接垫层通过铝通孔电连接到所述金属层。
11.根据权利要求1所述的集成电路结构，其中另包含：
钝化层，部分覆盖所述铝接垫层并且部分覆盖所述介电层。
12.根据权利要求11所述的集成电路结构，其中所述钝化层包括磷硅玻璃层和氮化硅层。
13.一种形成集成电路结构的方法，包含：
提供基底，其上包含电路区域；
在所述基底上形成铜互连结构，其中所述铜互连结构包含被介电层覆盖的最上层铜层；
在所述电路区域内的所述最上层铜层上形成金属层；以及
在所述介电层上形成铝接垫层。
14.根据权利要求13所述的方法，其中所述金属层是铝屏蔽金属层。
15.根据权利要求14所述的方法，其中所述铝屏蔽金属层通过钨通孔电连接到所述最上层铜层。
16.根据权利要求15所述的方法，其中所述钨通孔的宽度为
Figure FDA0002893671370000021
微米。
17.根据权利要求15所述的方法，其中在所述电路区域内的所述最上层铜层上形成所述金属层包含：
形成下介电层；
在所述下介电层中形成所述钨通孔；
在所述下介电层上形成所述铝屏蔽金属层；以及
在所述铝屏蔽金属层和所述下介电层上形成所述上介电层。
18.根据权利要求17所述的方法，其中所述上介电层比所述下介电层厚。
19.根据权利要求17所述的方法，其中所述上介电层和所述下介电层是由相同的介电材料所组成的。
20.根据权利要求13所述的方法，其中另包含：
形成钝化层，部分覆盖所述铝接垫层并且部分覆盖所述介电层。
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