CN109411443A - 垂直堆叠晶圆及其形成方法 - Google Patents

垂直堆叠晶圆及其形成方法 Download PDF

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CN109411443A
CN109411443A CN201810929331.1A CN201810929331A CN109411443A CN 109411443 A CN109411443 A CN 109411443A CN 201810929331 A CN201810929331 A CN 201810929331A CN 109411443 A CN109411443 A CN 109411443A
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wafer
tsv
dielectric medium
metal wire
front side
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CN109411443B (zh
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卢克·G·英格兰
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Abstract

本发明涉及垂直堆叠晶圆及其形成方法，揭示集成电路堆叠及其形成方法。在一个实施例中，该集成电路堆叠可包括：多个垂直堆叠晶圆，各晶圆包括后侧及前侧，各晶圆的该后侧包括位于衬底内的半导体穿孔(TSV)，且各晶圆的该前侧包括位于第一介电质内的金属线，其中，该金属线与各晶圆内的该TSV连接；以及无机介电质，介于该多个垂直堆叠晶圆内的相邻晶圆之间；其中，该多个垂直堆叠晶圆以前对后取向堆叠，以使一个晶圆的该后侧上的该TSV与相邻晶圆的该前侧上的该金属线通过延伸穿过介于它们之间的该无机介电质电性连接。

Description

垂直堆叠晶圆及其形成方法
技术领域
本发明涉及垂直堆叠晶圆，尤其，本发明涉及通过混合-氧化物接合以前对后(front-to-back)取向垂直堆叠的晶圆及其形成方法。
背景技术
一般来说，在集成电路(integrated circuit；IC)芯片/裸片中可设计并嵌入多个装置/组件(例如，晶体管、二极管等)，接着将该芯片置于封装件(例如，塑料壳)中或用作裸芯片以置于电子装置的印刷电路板(printed circuit board；PCB)上。除晶体管级的传统技术节点微缩以外，正越来越多地利用三维(three-dimensional；3D)IC芯片堆叠以继续使用当前的半导体制造技术(例如，28纳米、22纳米等)来创建3D芯片上系统(system-on-chip；SoC)装置并为满足各种电子装置的性能、功率及带宽要求提供解决方案。3D SoC装置可包括不同技术节点的数个逻辑、存储器(memory)、模拟(analog)或其它芯片，该些芯片可通过使用半导体穿孔(through-semiconductor-via；TSV)架构彼此连接。通常，TSV是蚀刻至半导体层中并用导电材料(例如，铜(Cu))填充的垂直过孔，以提供用以在该些垂直堆叠IC芯片之间或IC芯片与IC封装衬底之间传输电子信号或功率供应的连接性。
在3D SoC装置中，可划分单独SoC功能块于单独IC芯片上，以于3D IC封装期间连接，其中，在该3D配置中较短的线长可提高性能并降低装置的总体功耗。此外，线长的缩短减少所需的后端工艺(back end of line；BEOL)金属层(也就是，在主动装置层以后的连接层)的总数。在3D SoC装置的同质应用中，划分单个技术节点内的功能块，从而导致半导体晶圆上较小的裸片/芯片尺寸，以增加良率以及每个晶圆的装置效率。此类应用可扩展现有技术以进一步制造于当前可用的/已购买的制造工具组上，从而导致14纳米技术节点的扩展并推迟对降低技术节点(例如，10纳米微缩)的需求。在3D SoC装置的异质应用中，可基于可微缩性进行区块划分，其中，将较高可微缩的数字(digital)核心及知识产权(IP)微缩至先进技术节点。可能不会很好地微缩的装置例如状态随机访问存储器(state randomaccess memory；SRAM)、输入/输出(I/O)及其它模拟装置可在较老的技术上制造。由于针对系统的部分使用较老技术的可能性，此类应用可导致较高的总体良率以及降低的成本。
3D SoC装置/IC芯片堆叠可通过垂直对齐的半导体晶圆的面对面(face-to-face；F2F)接合形成，在每个晶圆上包括IC芯片阵列，其中，接合后的3D IC芯片可通过相邻的接合3D IC芯片之间的切割道彼此隔开。用于3D SoC装置的当前工业方法包括呈F2F配置的晶圆接合，其中，在完成该接合以后，在晶圆的其中之一(例如，底部晶圆)中蚀刻TSV(后TSV方法)。不过，后TSV(TSV-last)方法需要复杂的对准、设计及制程技术。另外，由于自IC衬底的背侧蚀刻TSV可能是困难的，因此，使用后TSV方法的3D SoC装置的TSV结构及质量可能受到负面影响，例如，当到达TSV接触点时引起“爆裂(blowout)”。
3D SoC装置/IC芯片也可通过垂直对齐的半导体晶圆的面对背(face-to-back；F2B)接合来形成。针对F2B 3D SoC装置的当前方法包括使用标准的覆晶互连。此方法包括在位于晶圆的顶侧上的垫(pad)上沉积焊接凸块并将该垫与另一个晶圆上的相应垫对齐。垫一经对齐，即回流该焊料，以完成该互连结构。不过，对于缩小的芯片及焊接结构的间距，此类方法导致增加的电容负载、不良的热性能，以及困难的互连良率。
发明内容
本发明的第一态样涉及一种集成电路堆叠。该集成电路堆叠包括：第一晶圆，以前对后取向附着至第二晶圆，其中，各晶圆包括后侧及前侧，各晶圆的该后侧包括位于衬底内的半导体穿孔(through-semiconductor-via；TSV)，且各晶圆的该前侧包括位于第一介电质内的金属线，其中，该金属线与各相应晶圆内的该TSV连接；以及第二介电质，介于该第一晶圆的该衬底与该第二晶圆的该第一介电质之间，其中，该第一晶圆的该TSV自该第一晶圆的该衬底延伸穿过该第二介电质并与该第二晶圆的该第一介电质内的该金属线电性连接。
本发明的第二态样涉及一种形成集成电路堆叠的方法。该方法可包括：以前对后取向将第一晶圆与第二晶圆附着，该附着包括通过混合-氧化物接合将位于该第二晶圆的前侧上的第一介电质内的金属线附着至位于第一晶圆的后侧上的衬底内的半导体穿孔(TSV)。
本发明的第三态样涉及一种集成电路堆叠。该集成电路堆叠可包括：多个垂直堆叠晶圆，各晶圆包括后侧及前侧，各晶圆的该后侧包括位于衬底内的半导体穿孔(TSV)，且各晶圆的该前侧包括位于第一介电质内的金属线，其中，该金属线与各晶圆内的该TSV连接；以及无机介电质，介于该多个垂直堆叠晶圆内的相邻晶圆之间；其中，该多个垂直堆叠晶圆以前对后取向堆叠，以使一个晶圆的该后侧上的该TSV与相邻晶圆的该前侧上的该金属线通过延伸穿过介于它们之间的该无机介电质电性连接。
从下面有关本发明的实施例的更详细说明将清楚本发明的上述及其它特征。
附图说明
通过参照下面的附图来详细说明本发明的实施例，该些附图中类似的附图标记表示类似的元件，且其中：
图1至图8显示经历依据本发明的方法的实施例的集成电路堆叠的剖视图，其中，图8显示依据本发明的所得集成电路堆叠。
图9至图10显示依据本发明的另一个实施例的集成电路堆叠的剖视图。
应当注意，本发明的附图并非按比例绘制。该些附图意图仅显示本发明的典型态样，因此不应当被视为限制本发明的范围。在该些附图中，类似的附图标记表示该些附图之间类似的元件。
具体实施方式
本发明涉及垂直堆叠晶圆，尤其，本发明涉及通过混合-氧化物接合以前对后取向垂直堆叠的晶圆及其形成方法。本发明的实施例包括混合-氧化物接合结构，其中，位于一个晶圆的前侧上的衬底内的半导体穿孔(through-semiconductor-via；TSV)与位于另一个相邻晶圆的后侧上的介电质内的金属线电性连接。该TSV延伸穿过介于该两个晶圆之间的无机介电质，以建立合适的连接。因此，此结构无需向该集成电路堆叠增加多余的电容及热阻的微柱互连及聚合物底部填充层。另外，此结构无需传统上被添加至晶圆的后侧的额外金属层。
如本文中所述，依据本发明的实施例的方法可包括以前对后取向附着第一晶圆与第二晶圆。更具体地说，该附着可包括通过混合-氧化物接合将位于该第二晶圆的前侧上的第一介电质内的金属线附着至位于第一晶圆的后侧上的衬底内的半导体穿孔(TSV)。现在请参照图1，方法可包括提供包括第一晶圆110的初级集成电路(IC)100。晶圆110可包括位于介电质130内的金属线128，以形成晶圆110的前侧132。线128与介电质130一起定义后端工艺(back-end-of-the-line；BEOL)层。另外，晶圆110可包括位于衬底120内的TSV 114，其与晶圆110的第一线路层128连接。如图所示，衬底120可包括能够被加工成晶体管结构的任意当前已知或以后开发的材料，且可包括例如块体半导体层、绝缘体上半导体(semiconductor-on-insulator；SOI)衬底等。衬底120可包括任意当前已知或以后开发的材料，其可包括但不限于硅、锗、碳化硅，以及基本由具有由式AlX1GaX2InX3AsY1PY2NY3SbY4定义的组成的一种或多种III-V族化合物半导体组成的材料，其中，X1、X2、X3、Y1、Y2、Y3及Y4表示相对比例，分别大于或等于0且X1+X2+X3+Y1+Y2+Y3+Y4＝1(1是总的相对摩尔量)。其它合适的衬底包括具有组成ZnA1CdA2SeB1TeB2的II-VI族化合物半导体，其中，A1、A2、B1及B2是相对比例，分别大于或等于零，且A1+A2+B1+B2＝1(1是总的摩尔量)。而且，可应变衬底120的全部或其部分。
介电质130可包括例如以下至少其中之一：氮化硅(Si3N4)、氧化硅(SiO2)、氟化SiO2(FSG)、氢化碳氧化硅(SiCOH)、多孔SiCOH、硼-磷-硅酸盐玻璃(BPSG)、倍半硅氧烷、包括硅(Si)、碳(C)、氧(O)原子的碳(C)掺杂氧化物(也就是，有机硅酸盐)，以及其它低介电常数(<3.9)材料，或其层。
TSV 114及金属线128可分别包括导电衬里及导电填充物(为简洁起见，本文中未单独显示)。导电衬里可包括例如以下至少其中之一：氮化钛、氮化钽、氮化钨、钽、钛，或其它热稳定材料。该导电填充物可包括例如以下至少其中之一：钛、钨、钽、铝、铜，或其合金。此外，TSV 114还可基本上被现有技术所已知但为简洁起见未显示的绝缘衬里围绕。该绝缘衬里可包括例如氧化物，如二氧化硅或氧化铪，或氮化物，如氮化硅。尽管这里未显示，但衬底120可包括前端工艺(front-end-of-the-line；FEOL)结构，例如晶体管、电阻器、电容器等，TSV 114向其提供电性连接。晶圆110可通过传统的沉积、蚀刻及平坦化技术形成。
现在请参照图2，可将晶圆110翻转并附着至临时操作晶圆140，该临时操作晶圆可形成于晶圆110的前侧132上。临时操作晶圆140可包括例如玻璃、块体硅，或牺牲硅。在一些实施例中，例如，若将玻璃或块体硅用于临时操作晶圆140，则可使用接合层142(例如粘结剂或胶体)以将临时操作晶圆140附着至晶圆110。若将牺牲硅用于临时操作晶圆140，则可通过临时操作晶圆140的牺牲硅与晶圆110的介电质130之间的直接介电质接合来附着牺牲硅。在此情况下，接合层142是在组成上类似位于前侧132上的介电质130的介电材料。通过接合层142与介电质130之间的悬空键(dangling bonds)接合，此实施例中的接合层142的介电材料促进操作晶圆140与晶圆110的介电质130接合。如本文中将说明的那样，在将所需数目的晶圆附着在一起并形成所得IC堆叠以后，可移除临时操作晶圆140。临时操作晶圆140向晶圆110提供机械支持，从而可操作晶圆110以进行额外处理。
如图3中所示，可执行蚀刻或研磨以显露或暴露TSV 114。也就是说，(通过蚀刻或研磨)可移除衬底120的部分，以显露或暴露位于晶圆100的后侧122上的TSV 114。该蚀刻或研磨可包括例如机械研磨，以及随后的毯覆干式或湿式蚀刻。例如，晶圆100可以约750微米(um)的厚度开始。被移除的衬底120的量可取决于衬底120内的TSV 114的深度。在一个例子中，可使用机械蚀刻以蚀刻衬底120至TSV 114约3微米至约5微米内。随后，可使用毯覆湿式或干式蚀刻移除衬底120的额外部分，以暴露TSV 114。不过，应当理解，依据自晶圆110的前侧132所蚀刻的TSV 114的深度，可移除衬底120的任意所需量。若具有围绕TSV 114的绝缘衬里，则此蚀刻可暴露围绕TSV 114的该绝缘衬里。
“蚀刻”通常是指自衬底(或形成于该衬底上的结构)移除材料，且常常通过在适当位置的掩膜执行，从而可自该衬底的特定区域选择性移除材料，同时保留该衬底的其它区域中的材料不受影响。通常有两类蚀刻，(i)湿式蚀刻以及(ii)干式蚀刻。湿式蚀刻可使用经选择能够选择性溶解给定材料(例如氧化物)同时使另一种材料(例如多晶硅)保持相对完好的化学剂(例如酸)执行。选择性蚀刻特定材料的能力对于许多半导体制程是至关重要的。湿式蚀刻通常会等向性蚀刻同质材料(例如，氧化物)，但湿式蚀刻也可非等向性蚀刻单晶材料(例如，硅晶圆)。可利用等离子体执行干式蚀刻。通过调节该等离子体的参数，可以数种模式操作等离子体系统。普通等离子体产生中性或带电的高能自由基，其在晶圆的表面反应。由于中性粒子从所有角度攻击晶圆，因此此制程是等向性的。离子研磨(ionmilling)或溅镀蚀刻(sputter etching)用大致从一个方向接近晶圆的惰性气体的高能离子轰击晶圆，因此此制程为高度非等向性的。反应离子蚀刻(reactive-ion etching；RIE)操作于介于溅镀蚀刻与等离子体蚀刻之间的条件下，且可被用以产生深而窄的特征，例如STI(浅沟槽隔离)沟槽。
现在请参照图4，在晶圆110的衬底120及TSV 114上可形成介电质150。介电质150可通过例如沉积形成。本文中所使用的“沉积”可包括适于沉积的任意当前已知或以后开发的技术，包括但不限于例如：化学气相沉积(chemical vapor deposition；CVD)、低压CVD(low-pressure CVD；LPCVD)、等离子体增强型CVD(plasma-enhanced CVD；PECVD)、半大气压CVD(semi-atmosphere CVD；SACVD)高密度等离子体CVD(high density plasma CVD；HDPCVD)、快速加热CVD(rapid thermal CVD；RTCVD)、超高真空CVD(ultra-high vacuumCVD；UHVCVD)、限制反应处理CVD(limited reaction processing CVD；LRPCVD)、金属有机CVD(metalorganic CVD；MOCVD)、溅镀沉积、离子束沉积、电子束沉积、激光辅助沉积、热氧化、热氮化、旋涂方法、物理气相沉积(physical vapor deposition；PVD)、原子层沉积(atomic layer deposition；ALD)、化学氧化、分子束外延(molecular beam epitaxy；MBE)、镀覆，以及蒸镀。更具体地说，介电质150可通过低温(小于约400℃)化学气相沉积技术形成。介电质150可沉积至大于约0.5微米(um)的厚度。介电质150可包括例如无机介电材料，如氢化碳氧化硅(hydrogenated silicon oxycarbide；SiCOH)、有机硅酸盐玻璃(organosilicate glass；OSG)、氧化硅(SiO2)、氮化硅(SiN)、氟化SiO2(flourinated SiO2；FSG)、甲基倍半硅氧烷(methylsilesquoxane；MSQ)，或其多孔版本。另外，可将介电质150平坦化至晶圆110的TSV 114。在此平坦化期间，也可移除围绕TSV 114的任意绝缘衬里。因此，可将介电质150及任意绝缘衬里平坦化至TSV114的导电衬里。因此，暴露TSV 114的导电部分。
平坦化可指使表面更平坦(也就是，更平及/或光滑)的各种制程。化学机械抛光(chemical-mechanical-polishing；CMP)是目前一种传统的平坦化制程，其通过化学反应与机械力的组合来平坦化表面。CMP使用包括研磨及腐蚀性化学成分的浆料以及通常具有比晶圆大的直径的抛光垫及固定环。通过动态抛光头将该垫与晶圆压合在一起并通过塑料固定环固定到位。以不同旋转轴(也就是，不同心)旋转该动态抛光头。这移除材料并往往平整掉任意“形貌”，从而使该晶圆平整且平坦。当前其它传统的平坦化技术可包括：(i)氧化；(ii)化学蚀刻；(iii)通过离子注入损伤的锥形控制；(iv)低熔点玻璃膜的沉积；(v)再溅镀沉积膜，以使其平整；(vi)光敏聚酰亚胺(photosensitive polyimide；PSPI)膜；(vii)新树脂；(viii)低粘性液体环氧树脂；(ix)旋涂玻璃(spin-on glass；SOG)材料；气体团簇离子束；以及/或者(x)牺牲回蚀刻。
现在请参照图5，可将第二晶圆210附着至晶圆110，以形成集成电路(IC)堆叠200。晶圆210可基本类似晶圆110，因此包括类似的编号方案，以使200中类似的号码与类似晶圆110中的类似编号结构的晶圆210中的结构对应。除位于晶圆210的介电质230内的金属线228以外，在介电质230内也可设置导电垫252。导电垫252可包括与晶圆210的前侧232基本齐平的表面，以使导电垫252暴露于晶圆210的前侧232。与TSV 114、214及金属线128、228类似，导电垫可包括导电衬里及导电填充物。导电垫252的该导电衬里可包括例如以下至少其中之一：氮化钛、氮化钽、氮化钨、钽、钛，或其它热稳定材料。导电垫252的该导电填充物可包括例如以下至少其中之一：钛、钨、钽、铝、铜，或其合金。
可以前对后取向将晶圆210附着至晶圆110。也就是说，可将晶圆210的前侧232附着至晶圆110的后侧122。在此附着期间，可将晶圆210的导电垫252与位于晶圆110的后侧122内的暴露TSV 114对齐。例如，可使用混合-氧化物接合制程来接合相对晶圆110、210中的TSV114与导电垫252。混合-氧化物接合制程包括平坦化介电及导电表面的晶圆接合，例如，位于晶圆110上的介电质150与位于晶圆210的后侧232上的介电质230的接合。为完成初始接合，可通过等离子体或湿式清洗预处理两个晶圆110、210的介电表面，接着使晶圆110、210接触，以使介电质130、150的悬空键彼此吸引。这些制程步骤可在室温或升温下执行。可完成随后的热退火，以增强该介电接合并驱动在两个相对导电结构(例如，导电垫252与TSV114)之间的扩散，从而形成单个导电互连结构。以此方式，该退火通过导电垫252电性连接第一晶圆110的TSV 114与第二晶圆210的金属线228。例如，可执行在约250℃至约350℃的热退火约1.5小时。不过，此例并非意图限制，依据IC堆叠200的所需应用，可使用其它温度及定时参数。
仍请参照图5，集成堆叠200可包括通过混合-氧化物接合以前对后取向附着至晶圆210的晶圆110。各晶圆110、210可包括后侧122、222及前侧132、232。各晶圆110、210的后侧122、222可包括位于衬底120、220内的一个或多个TSV 114、214。各晶圆110、210的前侧132、232可包括位于介电质130、230内的一条或多条金属线128、228。位于介电质130内的金属线128可与位于晶圆110的衬底120内的TSV 114连接。位于介电质230内的金属线228可与位于晶圆210的衬底220内的TSV 214连接。介电质150可设于晶圆110的衬底120与晶圆210的介电质230之间。介电质150可包括无机介电材料，例如以下至少其中之一：氢化碳氧化硅(SiCOH)、有机硅酸盐玻璃(OSG)、氧化硅(SiO2)、氮化硅(SiN)、氟化SiO2(FSG)、甲基倍半硅氧烷(MSQ)，或其多孔版本。晶圆110的TSV 114可自衬底120延伸穿过介电质150并通过位于晶圆210的介电质230内的导电垫252与金属线228电性连接。
现在请参照图6，针对需要附着的任意数目的晶圆可重复该制程。也就是说，可蚀刻衬底220以暴露晶圆210的TSV 214并可在其上方形成介电质250。介电质250可包括关于介电质150所列出的任意介电材料。可平坦化介电质250(以及任意绝缘衬里(未显示))，以暴露TSV 214的导电部分，如关于图4所述的那样。如图7中所示，可将第三晶圆310附着至晶圆210，以形成IC堆叠300。晶圆310可基本类似晶圆110、210，并因此包括类似的编号方案，以使300中类似的号码与类似晶圆110、210中的类似编号结构的晶圆310中的结构对应。除位于晶圆310的介电质330内的金属线328以外，在介电质330内也可设置导电垫352。导电垫352可包括与晶圆310的前侧332基本齐平的表面，以使导电垫352暴露于晶圆310的前侧332。
可以前对后取向将晶圆310附着至晶圆210。也就是说，可将晶圆310的前侧332附着至晶圆210的后侧222。在此附着期间，可将晶圆310的导电垫352与位于晶圆210的后侧222内的暴露TSV 214对齐。例如，可使用混合-氧化物接合制程来接合相对晶圆210、310中的TSV214与导电垫352。为完成初始接合，可通过等离子体或湿式清洗预处理两个晶圆210、310的介电表面(例如，介电质250与介电质330)，接着使晶圆210、310接触，以使介电质250、330的悬空键彼此吸引。这些制程步骤可在室温或升温下执行。可完成随后的热退火，以增强该介电接合并驱动在两个相对导电结构(例如，导电垫352与TSV 214)之间的扩散，从而形成单个导电互连结构。例如，可执行在约250℃至约350℃的热退火约1.5小时。不过，此例并非意图限制，依据IC堆叠200的所需应用，可使用其它温度及定时参数。不过，若将多个晶圆垂直堆叠成单个IC堆叠，可在将所需数目的晶圆彼此附着以后执行单个退火，以避免因过度退火而损伤其中的结构。
图8显示移除临时操作晶圆140(图7)以后的所得IC堆叠400。当附着所需数目的晶圆形成IC堆叠400时，可自晶圆110的前侧132移除临时操作晶圆140。若临时操作晶圆140包括玻璃且通过粘结剂142附着(图7)，则可通过清洗移除临时操作晶圆140及粘结剂142。若临时操作晶圆140包括牺牲硅而没有粘结剂，则可执行背面研磨并接着执行湿式或干式蚀刻，以移除该牺牲硅，从而暴露晶圆110的介电质130。
IC堆叠400可包括通过混合-氧化物接合附着的多个垂直堆叠晶圆110、210、310。各晶圆110、210、310可包括后侧122、222、322以及前侧132、232、332。各晶圆110、210、310的后侧122、222、322可包括位于衬底120、220、320内的一个或多个TSV 114、214、314。各晶圆110、210、310的前侧132、232、332可包括位于介电质130、230、330内的一条或多条金属线128、228、328。金属线128、228、328可与位于各晶圆内的TSV 114、214、314连接。更具体地说，并参照图8，金属线128可与位于晶圆110内的TSV 114连接，金属线228可与位于晶圆210内的TSV 214连接，以及金属线328可与位于晶圆310内的TSV 314连接。介电质150、250可介于相邻晶圆110、210、310之间。更具体地说，并参照图8，介电质150可介于晶圆110与晶圆210之间，且介电质250可介于晶圆210与晶圆310之间。可以前对后取向堆叠垂直堆叠晶圆110、210、310，以使位于晶圆110、210的后侧122、222上的TSV 114、214与位于相邻晶圆210、310的前侧232、332上的金属线228、328通过延伸穿过介于它们之间的介电质150、250电性连接。介电质150、250可包括无机材料，例如以下至少其中之一：氢化碳氧化硅(SiCOH)、有机硅酸盐玻璃(OSG)、氧化硅(SiO2)、氮化硅(SiN)、氟化SiO2(FSG)、甲基倍半硅氧烷(MSQ)，或其多孔版本。介电质150、250可具有与位于各晶圆的后侧122、222上的TSV 114、214的表面共面的表面。
更具体地说，并参照图8，位于晶圆110的后侧122上的TSV 114通过延伸穿过介电质150并与位于晶圆210内的导电垫252连接而与位于晶圆210的前侧232上的金属线228电性连接。此外，位于晶圆210的后侧222上的TSV 214通过延伸穿过介电质250并与位于晶圆310内的导电垫352连接而与位于晶圆310的前侧332上的金属线328电性连接。尽管未显示，但这同样适用于晶圆310的TSV 314与可能需要附着的另一个相邻晶圆。应当理解，堆叠400可包括任意数目的晶圆，而不背离本发明的态样。
仍请参照图8，在堆叠400内的最底部晶圆的后侧(例如晶圆110的前侧132)上可形成一个或多个微柱390。微柱390可包括传统的焊接凸块，其可促进堆叠400与另一个IC芯片、装置或堆叠(未显示)的连接。微柱390可在移除临时操作晶圆140(图7)以后形成，如图8中所示，或者可在形成临时操作晶圆140之前设于晶圆110上。若在形成微柱390以后形成临时操作晶圆140，则可能有必要包括足够厚度的粘结剂142(图7)，以基本上包围微柱390。
在另一个实施例中，如图9中所示，在如上关于图4所述形成介电质150以后，在另一个介电质504内可形成多个导电垫502。导电垫502可包括电性连接各TSV 114的作用(active)导电垫502a以及未与IC结构100内的任意其它结构例如TSV 114电性连接的非作用导电垫502b。导电垫502可包括任意当前已知或以后开发的导电垫材料，例如用于导电垫252的材料。
仍请参照图9，介电质504可沉积于晶圆110的后侧122上的介电质150以及暴露于其中的TSV 114上方。导电垫502可例如通过传统的单或双镶嵌制程形成于介电质504中。现有技术所已知的单镶嵌制程将包括在单个层内形成沟槽或开口，用填充材料填充该沟槽或开口，并平坦化，接着在另一层中重复该制程。相比之下，双镶嵌制程允许形成延伸于不止一层内的沟槽或开口，同时填充延伸于不止一层内的该沟槽或开口，并平坦化。在任一制程中，可使用掩膜控制形成该沟槽或开口的位置。
在下方设置有TSV 114的位置处的介电质504内可形成作用导电垫502a。以此方式，作用导电垫502a可提供将位于第一晶圆110内的TSV 114与位于第二晶圆210内的金属线230及导电垫252连接的途径。此外，在介电质504内可形成一个或多个非作用导电垫502b，以在该镶嵌制程期间帮助保持并控制平坦化。非作用导电垫502b之所以如此命名是因为它们不与IC结构100内的其它结构电性连接。
现在请参照图10，可将第二晶圆210附着至晶圆110，以形成集成电路(IC)堆叠500。如上关于图5所述，可将晶圆210附着至晶圆110。不过，在此实施例中，晶圆210的导电垫252及/或金属线228通过位于介电质504内的导电垫502与位于晶圆110内的TSV 114电性连接。此外，该混合-氧化物接合发生于位于晶圆110的后侧上的介电质504及其中的导电垫502与位于晶圆210的前侧232上的介电质230及导电垫252或金属线228之间。可如上关于图6至图8所述继续依据此实施例的该制程。
与传统IC堆叠相比，本发明提供通过混合-氧化物接合以前对后取向附着晶圆，而无需在各晶圆之间的微柱或底部填充层。因此，减小多余电容及热阻。此外，本发明的TSV在晶圆附着之前形成于或设于各晶圆内。因此，无需在晶圆附着以后延伸穿过整个堆叠形成单个TSV。另外，本发明的接合界面包括位于第一晶圆的后侧上的衬底内的TSV与位于第二相邻晶圆的前侧上的介电质内的BEOL结构通过设于它们之间的一个或多个介电质以及/或者导电垫相接。
如上所述的方法可用于集成电路芯片的制造中。制造者可以原始晶圆形式(也就是，作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得的集成电路芯片。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，接着将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为(a)中间产品例如母板的部分，或者作为(b)最终产品的部分。该最终产品可为包括集成电路芯片的任意产品，涉及范围从玩具及其它低端应用直至具有显示器、键盘或其它输入装置以及中央处理器的先进电脑产品。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制本发明。本文中所使用的术语“第一”、“第二”等不表示任意顺序、数量或重要性，而是用以区别元件。除非上下文中另外明确指出，否则本文中所使用的单数形式“一个”以及“该”也意图包括复数形式。另外，应当理解，术语“包括”用于本说明书中时表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件，和/或其群组。“可选的”或“可选地”是指后续所述事件或情况可能发生或者可能不发生，且该说明包括事件发生的情况以及其不发生的情况。
这里在说明书及权利要求书各处所使用的近似语言可用以修饰任意量化表达，可允许该量化表达变动而不会导致与其相关的基本功能的改变。因此，由一个或多个术语例如“约”及“基本上”修饰的值不限于所指定的精确值。在至少一些情况下，该近似语言可对应用以测量该值的仪器的精度。在这里以及说明书及权利要求书各处，范围限制可组合和/或互换，此类范围被识别并包括包含于其中的所有子范围，除非上下文或语言另外指出。应用于一范围的特定值的“约”适用于两个值，且除非依赖于测量该值的仪器的精度，否则可表示所述值的+/-10％。本文中所使用的“基本上”是指提供本发明的相同技术效果的主要、大部分、完全指定的或任意轻微的偏离。
随附的权利要求中的所有方式或步骤加功能元素的相应结构、材料、动作及等同意图包括结合具体请求保护的其它请求保护的元素执行该功能的任意结构、材料或动作。本发明的说明用于示例及说明目的，而非意图详尽无遗或限于所揭露形式的揭露。许多修改及变更将对于本领域的普通技术人员显而易见，而不背离本发明的范围及精神。实施例经选择及说明以最佳解释本发明的原理及实际应用，并使本领域的普通技术人员能够理解本发明针对各种实施例具有适合所考虑的特定应用的各种变更。

Claims (20)

1.一种集成电路堆叠，包括：
第一晶圆，以前对后取向附着至第二晶圆，其中，各晶圆包括后侧及前侧，各晶圆的该后侧包括位于衬底内的半导体穿孔(TSV)，且各晶圆的该前侧包括位于第一介电质内的金属线，其中，该金属线与各相应晶圆内的该TSV连接；以及
第二介电质，介于该第一晶圆的该衬底与该第二晶圆的该第一介电质之间，
其中，该第一晶圆的该TSV自该第一晶圆的该衬底延伸穿过该第二介电质并与该第二晶圆的该第一介电质内的该金属线电性连接。
2.如权利要求1所述的集成电路堆叠，其中，该第二介电质包括无机介电材料。
3.如权利要求2所述的集成电路堆叠，其中，该无机介电材料包括以下至少其中之一：氢化碳氧化硅(SiCOH)、有机硅酸盐玻璃(OSG)、氧化硅(SiO2)、氟化SiO2(FSG)、甲基倍半硅氧烷(MSQ)，或其多孔版本。
4.如权利要求1所述的集成电路堆叠，其中，该第一晶圆与该第二晶圆通过混合-氧化物接合附着。
5.如权利要求1所述的集成电路堆叠，还包括：
微柱结构，与该第一晶圆的该后侧上的该金属线连接。
6.如权利要求1所述的集成电路堆叠，还包括：
第三晶圆，附着至该第二晶圆，该第三晶圆包括后侧及前侧，该第三晶圆的该后侧包括位于衬底内的TSV，且该第三晶圆的该前侧包括位于第三介电质内的金属线，其中，该第三晶圆的该金属线与该第三晶圆中的该TSV连接；以及
第四介电质，设于该第二晶圆的该衬底与该第三晶圆的该第三介电质之间，
其中，该第二晶圆的该TSV自该第二晶圆的该衬底延伸穿过该第四介电质并与该第三晶圆的该第三介电质中的该金属线电性连接。
7.如权利要求1所述的集成电路堆叠，还包括：
第三介电质，设于该第二介电质与该第二晶圆的该第一介电质之间；以及
作用导电垫，设于该第三介电质内，提供自该第一晶圆的该TSV与该第二晶圆的该金属线的电性连接。
8.如权利要求6所述的集成电路堆叠，还包括：
导电垫，设于该第二晶圆中的该第一介电质内并提供该第一晶圆的该TSV与该第二晶圆的该金属线之间的电性连接。
9.如权利要求1所述的集成电路堆叠，其中，各晶圆的该TSV包括多个TSV且各晶圆的该金属线包括多条金属线，其中，各自晶圆内的该多条金属线的各金属线与该各自晶圆内的该多个TSV的相应TSV连接，以及
其中，该第一晶圆的该多个TSV的各TSV自该第一晶圆的该衬底延伸穿过该第二介电质并与该第二晶圆的该多条金属线的各自金属线电性连接。
10.一种形成集成电路堆叠的方法，该方法包括：
以前对后取向将第一晶圆与第二晶圆附着，该附着包括通过混合-氧化物接合将位于该第二晶圆的前侧上的第一介电质内的金属线附着至位于第一晶圆的后侧上的衬底内的半导体穿孔(TSV)。
11.如权利要求10所述的方法，其中，该附着包括：
提供该第一晶圆，其包括位于该第一晶圆的该后侧上的该衬底内的该TSV以及位于该第一晶圆的前侧上的第二介电质内的金属线；
蚀刻该第一晶圆的该衬底，以暴露位于该第一晶圆的该后侧上的该TSV；
在该第一晶圆的该衬底上形成第三介电质并平坦化该第三介电质至该第一晶圆的该TSV；以及
将位于该第一晶圆上的该第三介电质与位于该第二晶圆的该前侧上的该第一介电质接合。
12.如权利要求11所述的方法，其中，该附着还包括：
执行退火以将该第一晶圆的该TSV与该第二晶圆的该金属线电性连接。
13.如权利要求11所述的方法，还包括：
在所述形成该第三介电质以后并在该接合之前：
在位于该第一晶圆上的该第三介电质上方形成第四介电质；以及
在该第四介电质内形成作用导电垫及非作用导电垫，该作用导电垫提供该第一晶圆的该TSV与该第二晶圆的该金属线之间的电性连接，且该非作用导电垫与该第一晶圆的该TSV及该第二晶圆的该金属线电性断开，
其中，该接合包括接合位于该第一晶圆上的该第四介电质与位于该第二晶圆的该前侧上的该第一介电质。
14.如权利要求11所述的方法，还包括：
在所述提供该第一晶圆以后且在所述蚀刻该衬底之前，在该第一晶圆的该前侧上形成微柱结构，以使该微柱结构与位于该第一晶圆的该前侧上的该第二介电质内的该金属线连接。
15.如权利要求11所述的方法，还包括：
在所述附着之后在该第一晶圆的该前侧上形成微柱结构，该微柱结构与位于该第一晶圆的该前侧内的第二介电质内的金属线连接。
16.一种集成电路堆叠，包括：
多个垂直堆叠晶圆，各晶圆包括后侧及前侧，各晶圆的该后侧包括位于衬底内的半导体穿孔(TSV)，且各晶圆的该前侧包括位于第一介电质内的金属线，其中，该金属线与各晶圆内的该TSV连接；以及
无机介电质，介于该多个垂直堆叠晶圆内的相邻晶圆之间；
其中，该多个垂直堆叠晶圆以前对后取向堆叠，以使一个晶圆的该后侧上的该TSV与相邻晶圆的该前侧上的该金属线通过延伸穿过介于它们之间的该无机介电质电性连接。
17.如权利要求16所述的集成电路堆叠，其中，各该多个垂直堆叠晶圆通过混合-氧化物接合附着至该多个垂直堆叠晶圆中的相邻晶圆。
18.如权利要求16所述的集成电路堆叠，还包括：
微柱结构，与位于该垂直堆叠晶圆的最底部晶圆的该前侧上的该金属线连接。
19.如权利要求16所述的集成电路堆叠，其中，该无机介电质包括以下至少其中之一：氢化碳氧化硅(SiCOH)、有机硅酸盐玻璃(OSG)、氧化硅(SiO2)、氟化SiO2(FSG)、甲基倍半硅氧烷(MSQ)，或其多孔版本。
20.如权利要求16所述的集成电路堆叠，其中，该无机介电质与各晶圆的该后侧上的该TSV齐平。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
CN111725147A (zh) * 2019-03-21 2020-09-29 南亚科技股份有限公司 半导体封装结构及其制备方法
WO2021031419A1 (zh) * 2019-08-22 2021-02-25 武汉新芯集成电路制造有限公司 第一晶圆及其形成方法、晶圆堆叠结构
CN112736069A (zh) * 2019-10-28 2021-04-30 南亚科技股份有限公司 晶粒组件及其制备方法
WO2021168948A1 (zh) * 2020-02-25 2021-09-02 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法
US11211348B2 (en) 2019-08-22 2021-12-28 Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. First wafer, fabricating method thereof and wafer stack
WO2022116280A1 (zh) * 2020-12-01 2022-06-09 武汉新芯集成电路制造有限公司 半导体器件的制作方法及半导体器件

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
EP3493209A1 (en) * 2017-11-29 2019-06-05 IMEC vzw An assembly of integrated circuit modules and method for identifying the modules
JP7201387B2 (ja) * 2018-10-23 2023-01-10 株式会社ダイセル 半導体装置製造方法
JP7224138B2 (ja) 2018-10-23 2023-02-17 株式会社ダイセル 半導体装置製造方法
CN112913015B (zh) 2018-10-23 2024-01-16 株式会社大赛璐 半导体装置制造方法
KR20210072181A (ko) 2019-12-06 2021-06-17 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR20220014364A (ko) * 2020-07-23 2022-02-07 삼성전자주식회사 반도체 패키지
KR20220058683A (ko) 2020-10-29 2022-05-10 삼성전자주식회사 반도체 패키지
FR3142038A1 (fr) * 2022-11-15 2024-05-17 Stmicroelectronics (Crolles 2) Sas Procédé de fabrication d’un dispositif électronique

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335261A (zh) * 2007-06-27 2008-12-31 台湾积体电路制造股份有限公司 层叠集成电路及半导体元件
CN101542701A (zh) * 2008-06-05 2009-09-23 香港应用科技研究院有限公司 基于硅通孔的三维晶圆叠层的键合方法
CN101582407A (zh) * 2008-05-14 2009-11-18 台湾积体电路制造股份有限公司 制造半导体衬底叠层的系统、结构和方法
CN101740421A (zh) * 2008-11-17 2010-06-16 中芯国际集成电路制造(上海)有限公司 晶圆及制作方法、系统级封装结构及封装方法
CN101814453A (zh) * 2010-04-08 2010-08-25 复旦大学 一种用于硅通孔互连中的硅片对准方法
CN102024782A (zh) * 2010-10-12 2011-04-20 北京大学 三维垂直互联结构及其制作方法
US20110170266A1 (en) * 2010-01-08 2011-07-14 Ibm Corporation 4d device process and structure
US20120049344A1 (en) * 2010-08-25 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
US20140124946A1 (en) * 2012-11-07 2014-05-08 International Business Machines Corporation Enhanced capture pads for through semiconductor vias

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648131A (en) * 1969-11-07 1972-03-07 Ibm Hourglass-shaped conductive connection through semiconductor structures
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7385283B2 (en) 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
US8502373B2 (en) * 2008-05-05 2013-08-06 Qualcomm Incorporated 3-D integrated circuit lateral heat dissipation
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US8298914B2 (en) 2008-08-19 2012-10-30 International Business Machines Corporation 3D integrated circuit device fabrication using interface wafer as permanent carrier
FI120447B (fi) * 2008-08-21 2009-10-30 Kone Corp Hissijärjestelmä sekä hissiryhmän ohjausmenetelmä
US9406561B2 (en) 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US8048794B2 (en) * 2009-08-18 2011-11-01 International Business Machines Corporation 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport
US8400781B2 (en) * 2009-09-02 2013-03-19 Mosaid Technologies Incorporated Using interrupted through-silicon-vias in integrated circuits adapted for stacking
US8159060B2 (en) 2009-10-29 2012-04-17 International Business Machines Corporation Hybrid bonding interface for 3-dimensional chip integration
US8258619B2 (en) * 2009-11-12 2012-09-04 International Business Machines Corporation Integrated circuit die stacks with translationally compatible vias
TW201145493A (en) * 2010-06-01 2011-12-16 Chipmos Technologies Inc Silicon wafer structure and multi-chip stack structure
KR20120057693A (ko) 2010-08-12 2012-06-07 삼성전자주식회사 적층 반도체 장치 및 적층 반도체 장치의 제조 방법
KR101692955B1 (ko) * 2010-10-06 2017-01-05 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
TWI496271B (zh) * 2010-12-30 2015-08-11 Ind Tech Res Inst 晶圓級模封接合結構及其製造方法
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
JP5932324B2 (ja) 2011-12-21 2016-06-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその試験方法
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9553080B1 (en) 2015-09-18 2017-01-24 Globalfoundries Inc. Method and process for integration of TSV-middle in 3D IC stacks

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335261A (zh) * 2007-06-27 2008-12-31 台湾积体电路制造股份有限公司 层叠集成电路及半导体元件
CN101582407A (zh) * 2008-05-14 2009-11-18 台湾积体电路制造股份有限公司 制造半导体衬底叠层的系统、结构和方法
CN101542701A (zh) * 2008-06-05 2009-09-23 香港应用科技研究院有限公司 基于硅通孔的三维晶圆叠层的键合方法
CN101740421A (zh) * 2008-11-17 2010-06-16 中芯国际集成电路制造(上海)有限公司 晶圆及制作方法、系统级封装结构及封装方法
US20110170266A1 (en) * 2010-01-08 2011-07-14 Ibm Corporation 4d device process and structure
CN101814453A (zh) * 2010-04-08 2010-08-25 复旦大学 一种用于硅通孔互连中的硅片对准方法
US20120049344A1 (en) * 2010-08-25 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP with Discrete Semiconductor Components Mounted Under and Over Semiconductor Die
CN102024782A (zh) * 2010-10-12 2011-04-20 北京大学 三维垂直互联结构及其制作方法
US20140124946A1 (en) * 2012-11-07 2014-05-08 International Business Machines Corporation Enhanced capture pads for through semiconductor vias

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725147A (zh) * 2019-03-21 2020-09-29 南亚科技股份有限公司 半导体封装结构及其制备方法
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
US11031377B2 (en) 2019-04-15 2021-06-08 Yangtze Memory Technologies Co., Ltd. Integration of three-dimensional NAND memory devices with multiple functional chips
US11923339B2 (en) 2019-04-15 2024-03-05 Yangtze Memory Technologies Co., Ltd. Integration of three-dimensional NAND memory devices with multiple functional chips
WO2021031419A1 (zh) * 2019-08-22 2021-02-25 武汉新芯集成电路制造有限公司 第一晶圆及其形成方法、晶圆堆叠结构
US11211348B2 (en) 2019-08-22 2021-12-28 Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. First wafer, fabricating method thereof and wafer stack
CN112736069A (zh) * 2019-10-28 2021-04-30 南亚科技股份有限公司 晶粒组件及其制备方法
CN112736069B (zh) * 2019-10-28 2024-03-29 南亚科技股份有限公司 晶粒组件及其制备方法
WO2021168948A1 (zh) * 2020-02-25 2021-09-02 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法
WO2022116280A1 (zh) * 2020-12-01 2022-06-09 武汉新芯集成电路制造有限公司 半导体器件的制作方法及半导体器件

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