TWI677075B - 垂直堆疊晶圓及其形成方法 - Google Patents

垂直堆疊晶圓及其形成方法 Download PDF

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TWI677075B
TWI677075B TW107121314A TW107121314A TWI677075B TW I677075 B TWI677075 B TW I677075B TW 107121314 A TW107121314 A TW 107121314A TW 107121314 A TW107121314 A TW 107121314A TW I677075 B TWI677075 B TW I677075B
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Taiwan
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wafer
dielectric
tsv
front side
integrated circuit
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TW107121314A
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TW201911535A (zh
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盧克Ｇ 英格蘭
Luke G. England
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美商格芯（美國）集成電路科技有限公司
Globalfoundries Us Inc.
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Abstract

本揭露關於積體電路堆疊及其形成方法。在一個實施例中，該積體電路堆疊可包括：多個垂直堆疊晶圓，各晶圓包括後側及前側，各晶圓的該後側包括位於基板內的半導體穿孔(through-semiconductor-via；TSV)，且各晶圓的該前側包括位於第一介電質內的金屬線，其中，該金屬線與各晶圓內的該TSV連接；以及無機介電質，介於該多個垂直堆疊晶圓內的相鄰晶圓之間；其中，該多個垂直堆疊晶圓以前對後取向堆疊，以使一個晶圓的該後側上的該TSV與相鄰晶圓的該前側上的該金屬線通過延伸穿過介於它們之間的該無機介電質電性連接。

Description

垂直堆疊晶圓及其形成方法
本揭露關於垂直堆疊晶圓，尤其，本揭露關於通過混合-氧化物接合以前對後取向垂直堆疊的晶圓及其形成方法。
一般來說，在積體電路(integrated circuit；IC)晶片中可設計並嵌入多個裝置/元件(例如，電晶體、二極體等)，接著將該晶片置於封裝件(例如，塑膠殼)中或用作裸晶片以置於電子裝置的印刷電路板(printed circuit board；PCB)上。除電晶體級的傳統技術節點微縮以外，正越來越多地利用三維(three-dimensional；3D)IC晶片堆疊以繼續使用當前的半導體製造技術(例如，28奈米、22奈米等)來創建3D晶片上系統(system-on-chip；SoC)裝置並為滿足各種電子裝置的性能、功率及頻寬要求提供解決方案。3D SoC裝置可包括不同技術節點的數個邏輯、記憶體、類比或其它晶片，該些晶片可通過使用半導體穿孔(through-semiconductor-via；TSV)架構彼此連接。通常，TSV是蝕刻至半導體層中並用導電材料(例如，銅(Cu))填 充的垂直穿孔，以提供用以在該些垂直堆疊IC晶片之間或IC晶片與IC封裝基板之間傳輸電子信號或功率供應的連線性。
在3D SoC裝置中，可劃分單獨SoC功能塊於單獨IC晶片上，以於3D IC封裝期間連接，其中，在該3D配置中較短的線長可提高性能並降低裝置的總體功耗。此外，線長的縮短減少所需的後端工藝(back end of line；BEOL)金屬層(也就是，在主動裝置層以後的連接層)的總數。在3D SoC裝置的同質應用中，劃分單個技術節點內的功能塊，從而導致半導體晶圓上較小的晶片尺寸，以增加良率以及每個晶圓的裝置效率。此類應用可擴展現有技術以進一步製造於當前可用的/已購買的製造工具組上，從而導致14奈米技術節點的擴展並推遲對降低技術節點(例如，10奈米微縮)的需求。在3D SoC裝置的異質應用中，可基於可微縮性進行區塊劃分，其中，將較高可微縮的數位核心及智慧財產權(IP)微縮至先進技術節點。可能不會很好地微縮的裝置例如狀態隨機存取記憶體(state random access memory；SRAM)、輸入/輸出(I/O)及其它類比裝置可在較老的技術上製造。由於針對系統的部分使用較老技術的可能性，此類應用可導致較高的總體良率以及降低的成本。
3D SoC裝置/IC晶片堆疊可通過垂直對齊的半導體晶圓的面對面(face-to-face；F2F)接合形成，在每個晶圓上包括IC晶片陣列，其中，接合後的3D IC晶片可通 過相鄰的接合3D IC晶片之間的切割道彼此隔開。用於3D SoC裝置的當前工業方法包括呈F2F配置的晶圓接合，其中，在完成該接合以後，在晶圓的其中之一(例如，底部晶圓)中蝕刻TSV(後TSV方法)。不過，後TSV方法需要複雜的對準、設計及製程技術。另外，由於自IC基板的背側蝕刻TSV可能是困難的，因此，使用後TSV方法的3D SoC裝置的TSV結構及品質可能受到負面影響，例如，當到達TSV接觸點時引起“爆裂(blowout)”。
3D SoC裝置/IC晶片也可通過垂直對齊的半導體晶圓的面對背(face-to-back；F2B)接合來形成。針對F2B 3D SoC裝置的當前方法包括使用標準的覆晶互連。此方法包括在位於晶圓的頂側上的墊(pad)上沉積焊接凸塊並將該墊與另一個晶圓上的相應墊對齊。墊一經對齊，即回流該焊料，以完成該互連結構。不過，對於縮小的晶片及焊接結構的間距，此類方法導致增加的電容負載、不良的熱性能，以及困難的互連良率。
本揭露的第一態樣關於積體電路堆疊。該積體電路堆疊包括：第一晶圓，以前對後取向附著至第二晶圓，其中，各晶圓包括後側及前側，各晶圓的該後側包括位於基板內的半導體穿孔(through-semiconductor-via；TSV)，且各晶圓的該前側包括位於第一介電質內的金屬線，其中，該金屬線與各相應晶圓內的該TSV連接；以及第二介電質，介於該第一晶圓的該基板與該第二晶圓的該第一 介電質之間，其中，該第一晶圓的該TSV自該第一晶圓的該基板延伸穿過該第二介電質並與該第二晶圓的該第一介電質內的該金屬線電性連接。
本揭露的第二態樣關於一種形成積體電路堆疊的方法。該方法可包括：以前對後取向將第一晶圓與第二晶圓附著，該附著包括通過混合-氧化物接合將位於該第二晶圓的前側上的第一介電質內的金屬線附著至位於第一晶圓的後側上的基板內的半導體穿孔(TSV)。
本揭露的第三態樣關於積體電路堆疊。該積體電路堆疊可包括：多個垂直堆疊晶圓，各晶圓包括後側及前側，各晶圓的該後側包括位於基板內的半導體穿孔(TSV)，且各晶圓的該前側包括位於第一介電質內的金屬線，其中，該金屬線與各晶圓內的該TSV連接；以及無機介電質，介於該多個垂直堆疊晶圓內的相鄰晶圓之間；其中，該多個垂直堆疊晶圓以前對後取向堆疊，以使一個晶圓的該後側上的該TSV與相鄰晶圓的該前側上的該金屬線通過延伸穿過介於它們之間的該無機介電質電性連接。
從下面有關本揭露的實施例的更詳細說明將清楚本揭露的上述及其它特徵。
100‧‧‧初級積體電路(IC)、IC結構或晶圓
110‧‧‧晶圓或第一晶圓
114、214、314‧‧‧半導體穿孔(TSV)
120、220、320‧‧‧基板
122、222、322‧‧‧後側
128、228、328‧‧‧金屬線
130、150、230、250、330、504‧‧‧介電質
132、232、332‧‧‧前側
140‧‧‧臨時操作晶圓
142‧‧‧接合層或黏著劑
200、500‧‧‧積體電路(IC)堆疊
210‧‧‧晶圓或第二晶圓
252、502‧‧‧導電墊
300、400‧‧‧積體電路(IC)堆疊
310‧‧‧晶圓或第三晶圓
352‧‧‧導電墊
390‧‧‧微柱
502a‧‧‧作用導電墊
502b‧‧‧非作用導電墊
通過參照下面的附圖來詳細說明本揭露的實施例，該些附圖中類似的附圖標記表示類似的元件，且其中：第1圖至第8圖顯示經歷依據本揭露的方法 的實施例的積體電路堆疊的剖視圖，其中，第8圖顯示依據本揭露的所得積體電路堆疊。
第9圖至第10圖顯示依據本揭露的另一個實施例的積體電路堆疊的剖視圖。
應當注意，本揭露的附圖並非按比例繪製。該些附圖意圖僅顯示本揭露的典型態樣，因此不應當被視為限制本揭露的範圍。在該些附圖中，類似的附圖標記表示該些附圖之間類似的元件。
本揭露關於垂直堆疊晶圓，尤其，本揭露關於通過混合-氧化物接合以前對後取向垂直堆疊的晶圓及其形成方法。本揭露的實施例包括混合-氧化物接合結構，其中，位於一個晶圓的前側上的基板內的半導體穿孔(through-semiconductor-via；TSV)與位於另一個相鄰晶圓的後側上的介電質內的金屬線電性連接。該TSV延伸穿過介於該兩個晶圓之間的無機介電質，以建立合適的連接。因此，此結構無需向該積體電路堆疊增加多餘的電容及熱阻的微柱互連及聚合物底部填充層。另外，此結構無需傳統上被添加至晶圓的後側的額外金屬層。
如本文中所述，依據本揭露的實施例的方法可包括以前對後取向附著第一晶圓與第二晶圓。更具體地說，該附著可包括通過混合-氧化物接合將位於該第二晶圓的前側上的第一介電質內的金屬線附著至位於第一晶圓的後側上的基板內的半導體穿孔(TSV)。現在請參照第1圖，方法可包括提供包括第一晶圓110的初級積體電路(IC)100。晶圓110可包括位於介電質130內的金屬線128，以形成晶圓110的前側132。金屬線128與介電質130一起定義後端工藝(back-end-of-the-line；BEOL)層。另外，晶圓110可包括位於基板120內的TSV 114，其與晶圓110的金屬線128連接。如圖所示，基板120可包括能夠被加工成電晶體結構的任意當前已知或以後開發的材料，且可包括例如塊體半導體層、絕緣體上半導體(semiconductor-on-insulator；SOI)基板等。基板120可包括任意當前已知或以後開發的材料，其可包括但不限於矽、鍺、碳化矽，以及基本由具有由式AlX1GaX2InX3AsY1PY2NY3SbY4定義的組成的一種或多種III-V族化合物半導體組成的材料，其中，X1、X2、X3、Y1、Y2、Y3及Y4表示相對比例，分別大於或等於0且X1+X2+X3+Y1+Y2+Y3+Y4=1(1是總的相對摩爾量)。其它合適的基板包括具有組成ZnA1CdA2SeB1TeB2的II-VI族化合物半導體，其中，A1、A2、B1及B2是相對比例，分別大於或等於零，且A1+A2+B1+B2=1(1是總的摩爾量)。而且，可應變基板120的全部或其部分。
介電質130可包括例如以下至少其中之一：氮化矽(Si3N4)、氧化矽(SiO2)、氟化SiO2(FSG)、氫化碳氧化矽(SiCOH)、多孔SiCOH、硼-磷-矽酸鹽玻璃(BPSG)、倍半矽氧烷、包括矽(Si)、碳(C)、氧(O)原子的碳(C)摻雜氧化物(也就是，有機矽酸鹽)，以及其它低介電常數(<3.9)材料，或其層。
TSV 114及金屬線128可分別包括導電襯墊(liner)及導電填充物(為簡潔起見，本文中未單獨顯示)。導電襯墊可包括例如以下至少其中之一：氮化鈦、氮化鉭、氮化鎢、鉭、鈦，或其它熱穩定材料。該導電填充物可包括例如以下至少其中之一：鈦、鎢、鉭、鋁、銅，或其合金。此外，TSV 114還可基本上被現有技術所已知但為簡潔起見未顯示的絕緣襯墊圍繞。該絕緣襯墊可包括例如氧化物，如二氧化矽或氧化鉿，或氮化物，如氮化矽。儘管這裡未顯示，但基板120可包括前端工藝(front-end-of-the-line；FEOL)結構，例如電晶體、電阻器、電容器等，TSV 114向其提供電性連接。晶圓110可通過傳統的沉積、蝕刻及平坦化技術形成。
現在請參照第2圖，可將晶圓110翻轉並附著至臨時操作(handle)晶圓140，該臨時操作晶圓可形成於晶圓110的前側132上。臨時操作晶圓140可包括例如玻璃、塊體矽、或犧牲矽。在一些實施例中，例如，若將玻璃或塊體矽用於臨時操作晶圓140，則可使用接合層142例如黏著劑或膠體以將臨時操作晶圓140附著至晶圓110。若將犧牲矽用於臨時操作晶圓140，則可通過臨時操作晶圓140的犧牲矽與晶圓110的介電質130之間的直接介電質接合來附著犧牲矽。在此情況下，接合層142是在組成上類似位於前側132上的介電質130的介電材料。通過接合層142與介電質130之間的懸空鍵接合，此實施例中的接合層142的介電材料促進操作晶圓140與晶圓110的介 電質130接合。如本文中將說明的那樣，在將所需數目的晶圓附著在一起並形成所得IC堆疊以後，可移除臨時操作晶圓140。臨時操作晶圓140向晶圓110提供機械支援，從而可操作晶圓110以進行額外處理。
如第3圖中所示，可執行蝕刻或研磨以顯露或暴露TSV 114。也就是說，(通過蝕刻或研磨)可移除基板120的部分，以顯露或暴露位於晶圓100的後側122上的TSV 114。該蝕刻或研磨可包括例如機械研磨，以及隨後的毯覆乾式或濕式蝕刻。例如，晶圓100可以約750微米(um)的厚度開始。被移除的基板120的量可取決於基板120內的TSV 114的深度。在一個例子中，可使用機械蝕刻以蝕刻基板120至TSV 114約3微米至約5微米內。隨後，可使用毯覆濕式或乾式蝕刻移除基板120的額外部分，以暴露TSV 114。不過，應當理解，依據自晶圓110的前側132所蝕刻的TSV 114的深度，可移除基板120的任意所需量。若具有圍繞TSV 114的絕緣襯墊，則此蝕刻可暴露圍繞TSV 114的該絕緣襯墊。
“蝕刻”通常是指自基板(或形成於該基板上的結構)移除材料，且常常通過在適當位置的遮罩執行，從而可自該基板的特定區域選擇性移除材料，同時保留該基板的其它區域中的材料不受影響。通常有兩類蝕刻，(i)濕式蝕刻以及(ii)乾式蝕刻。濕式蝕刻可使用經選擇能夠選擇性溶解給定材料(例如氧化物)同時使另一種材料(例如多晶矽)保持相對完好的化學劑(例如酸)執行。選擇性蝕刻特 定材料的能力對於許多半導體製程是至關重要的。濕式蝕刻通常會等向性蝕刻同質材料(例如，氧化物)，但濕式蝕刻也可非等向性蝕刻單晶材料(例如，矽晶圓)。可利用電漿執行乾式蝕刻。通過調節該電漿的參數，可以數種模式操作電漿系統。普通電漿產生中性或帶電的高能自由基，其在晶圓的表面反應。由於中性粒子從所有角度攻擊晶圓，因此此製程是等向性的。離子研磨(ion milling)或濺鍍蝕刻(sputter etching)用大致從一個方向接近晶圓的惰性氣體的高能離子轟擊晶圓，因此此製程為高度非等向性的。反應離子蝕刻(reactive-ion etching；RIE)操作於介於濺鍍蝕刻與電漿蝕刻之間的條件下，且可被用以產生深而窄的特徵，例如STI(淺溝槽隔離)溝槽。
現在請參照第4圖，在晶圓110的基板120及TSV 114上可形成介電質150。介電質150可通過例如沉積形成。本文中所使用的“沉積”可包括適於沉積的任意當前已知或以後開發的技術，包括但不限於例如：化學氣相沉積(chemical vapor deposition；CVD)、低壓CVD(low-pressure CVD；LPCVD)、電漿增強型CVD(plasma-enhanced CVD；PECVD)、半大氣壓CVD(semi-atmosphere CVD；SACVD)高密度電漿CVD(high density plasma CVD；HDPCVD)、快速加熱CVD(rapid thermal CVD；RTCVD)、超高真空CVD(ultra-high vacuum CVD；UHVCVD)、限制反應處理CVD(limited reaction processing CVD；LRPCVD)、金屬有機CVD(metalorganic CVD；MOCVD)、濺鍍沉積、離子束沉積、電子束沉積、鐳射輔助沉積、熱氧化、熱氮化、旋塗方法、物理氣相沉積(physical vapor deposition；PVD)、原子層沉積(atomic layer deposition；ALD)、化學氧化、分子束外延(molecular beam epitaxy；MBE)、鍍覆，以及蒸鍍。更具體地說，介電質150可通過低溫(小於約400℃)化學氣相沉積技術形成。介電質150可沉積至大於約0.5微米(um)的厚度。介電質150可包括例如無機介電材料，如氫化碳氧化矽(SiCOH)、有機矽酸鹽玻璃(OSG)、氧化矽(SiO2)、氮化矽(SiN)、氟化SiO2(FSG)、甲基倍半矽氧烷(MSQ)，或其多孔版本。另外，可將介電質150平坦化至晶圓110的TSV 114。在此平坦化期間，也可移除圍繞TSV 114的任意絕緣襯墊。因此，可將介電質150及任意絕緣襯墊平坦化至TSV 114的導電襯墊。因此，暴露TSV 114的導電部分。
平坦化可指使表面更平坦(也就是，更平及/或光滑)的各種製程。化學機械拋光(chemical-mechanical-polishing；CMP)是目前一種傳統的平坦化製程，其通過化學反應與機械力的組合來平坦化表面。CMP使用包括研磨及腐蝕性化學成分的漿料以及通常具有比晶圓大的直徑的拋光墊及固定環。通過動態拋光頭將該墊與晶圓壓合在一起並通過塑膠固定環固定到位。以不同旋轉軸(也就是，不同心)旋轉該動態拋光頭。這移除材料並往往平整掉任意“形貌”，從而使該晶圓平整且平坦。當前其它傳統的平坦化技術可包括：(i)氧化；(ii)化學蝕刻；(iii)通過離子注入 損傷的錐形控制；(iv)低熔點玻璃膜的沉積；(v)再濺鍍沉積膜，以使其平整；(vi)光敏聚醯亞胺(photosensitive polyimide；PSPI)膜；(vii)新樹脂；(viii)低黏性液體環氧樹脂；(ix)旋塗玻璃(spin-on glass；SOG)材料；氣體團簇離子束；以及/或者(x)犧牲回蝕刻。
現在請參照第5圖，可將第二晶圓210附著至晶圓110，以形成積體電路(IC)堆疊200。晶圓210可基本類似晶圓110，因此包括類似的編號方案，以使200中類似的號碼與類似晶圓110中的類似編號結構的晶圓210中的結構對應。除位於晶圓210的介電質230內的金屬線228以外，在介電質230內也可設置導電墊252。導電墊252可包括與晶圓210的前側232基本齊平的表面，以使導電墊252暴露於晶圓210的前側232。與TSV 114、214及金屬線128、228類似，導電墊可包括導電襯墊及導電填充物。導電墊252的該導電襯墊可包括例如以下至少其中之一：氮化鈦、氮化鉭、氮化鎢、鉭、鈦，或其它熱穩定材料。導電墊252的該導電填充物可包括例如以下至少其中之一：鈦、鎢、鉭、鋁、銅，或其合金。
可以前對後取向將晶圓210附著至晶圓110。也就是說，可將晶圓210的前側232附著至晶圓110的後側122。在此附著期間，可將晶圓210的導電墊252與位於晶圓110的後側122內的暴露TSV 114對齊。例如，可使用混合-氧化物接合製程來接合相對晶圓110、210中的TSV 114與導電墊252。混合-氧化物接合製程包括平坦化 介電及導電表面的晶圓接合，例如，位於晶圓110上的介電質150與位於晶圓210的後側232上的介電質230的接合。為完成初始接合，可通過電漿或濕式清洗預處理兩個晶圓110、210的介電表面，接著使晶圓110、210接觸，以使介電質130、150的懸空鍵彼此吸引。這些製程步驟可在室溫或升溫下執行。可完成隨後的熱處理，以增強該介電接合並驅動在兩個相對導電結構(例如，導電墊252與TSV 114)之間的擴散，從而形成單個導電互連結構。以此方式，該退火通過導電墊252電性連接第一晶圓110的TSV 114與第二晶圓210的金屬線228。例如，可執行在約250℃至約350℃的熱退火約1.5小時。不過，此例並非意圖限制，依據IC堆疊200的所需應用，可使用其它溫度及定時參數。
仍請參照第5圖，積體堆疊200可包括通過混合-氧化物接合以前對後取向附著至晶圓210的晶圓110。各晶圓110、210可包括後側122、222及前側132、232。各晶圓110、210的後側122、222可包括位於基板120、220內的一個或多個TSV 114、214。各晶圓110、210的前側132、232可包括位於介電質130、230內的一條或多條金屬線128、228。位於介電質130內的金屬線128可與位於晶圓110的基板120內的TSV 114連接。位於介電質230內的金屬線228可與位於晶圓210的基板220內的TSV 214連接。介電質150可設於晶圓110的基板120與晶圓210的介電質230之間。介電質150可包括無機介電材料， 例如以下至少其中之一：氫化碳氧化矽(SiCOH)、有機矽酸鹽玻璃(OSG)、氧化矽(SiO2)、氮化矽(SiN)、氟化SiO2(FSG)、甲基倍半矽氧烷(MSQ)，或其多孔版本。晶圓110的TSV 114可自基板120延伸穿過介電質150並通過位於晶圓210的介電質230內的導電墊252與金屬線228電性連接。
現在請參照第6圖，針對需要附著的任意數目的晶圓可重複該製程。也就是說，可蝕刻基板220以暴露晶圓210的TSV 214並可在其上方形成介電質250。介電質250可包括關於介電質150所列出的任意介電材料。可平坦化介電質250(以及任意絕緣襯墊(未顯示))，以暴露TSV 214的導電部分，如關於第4圖所述的那樣。如第7圖中所示，可將第三晶圓310附著至晶圓210，以形成IC堆疊300。晶圓310可基本類似晶圓110、210，並因此包括類似的編號方案，以使300中類似的號碼與類似晶圓110、210中的類似編號結構的晶圓310中的結構對應。除位於晶圓310的介電質330內的金屬線328以外，在介電質330內也可設置導電墊352。導電墊352可包括與晶圓310的前側332基本齊平的表面，以使導電墊352暴露於晶圓310的前側332。
可以前對後取向將晶圓310附著至晶圓210。也就是說，可將晶圓310的前側332附著至晶圓210的後側222。在此附著期間，可將晶圓310的導電墊352與位於晶圓210的後側222內的暴露TSV 214對齊。例如，可 使用混合-氧化物接合製程來接合相對晶圓210、310中的TSV 214與導電墊352。為完成初始接合，可通過電漿或濕式清洗預處理兩個晶圓210、310的介電表面(例如，介電質250與介電質330)，接著使晶圓210、310接觸，以使介電質250、330的懸空鍵彼此吸引。這些製程步驟可在室溫或升溫下執行。可完成隨後的熱處理，以增強該介電接合並驅動在兩個相對導電結構(例如，導電墊352與TSV 214)之間的擴散，從而形成單個導電互連結構。例如，可執行在約250℃至約350℃的熱退火約1.5小時。不過，此例並非意圖限制，依據IC堆疊200的所需應用，可使用其它溫度及定時參數。不過，若將多個晶圓垂直堆疊成單個IC堆疊，可在將所需數目的晶圓彼此附著以後執行單個退火，以避免因過度退火而損傷其中的結構。
第8圖顯示移除臨時操作晶圓140(第7圖)以後的所得IC堆疊400。當附著所需數目的晶圓形成IC堆疊400時，可自晶圓110的前側132移除臨時操作晶圓140。若臨時操作晶圓140包括玻璃且通過黏著劑142附著(第7圖)，則可通過清洗移除臨時操作晶圓140及黏著劑142。若臨時操作晶圓140包括犧牲矽而沒有黏著劑，則可執行背面研磨並接著執行濕式或乾式蝕刻，以移除該犧牲矽，從而暴露晶圓110的介電質130。
IC堆疊400可包括通過混合-氧化物接合附著的多個垂直堆疊晶圓110、210、310。各晶圓110、210、310可包括後側122、222、322以及前側132、232、332。 各晶圓110、210、310的後側122、222、322可包括位於基板120、220、320內的一個或多個TSV 114、214、314。各晶圓110、210、310的前側132、232、332可包括位於介電質130、230、330內的一條或多條金屬線128、228、328。金屬線128、228、328可與位於各晶圓內的TSV 114、214、314連接。更具體地說，並參照第8圖，金屬線128可與位於晶圓110內的TSV 114連接，金屬線228可與位於晶圓210內的TSV 214連接，以及金屬線328可與位於晶圓310內的TSV 314連接。介電質150、250可介於相鄰晶圓110、210、310之間。更具體地說，並參照第8圖，介電質150可介於晶圓110與晶圓210之間，且介電質250可介於晶圓210與晶圓310之間。可以前對後取向堆疊垂直堆疊晶圓110、210、310，以使位於晶圓110、210的後側122、222上的TSV 114、214與位於相鄰晶圓210、310的前側232、332上的金屬線228、328通過延伸穿過介於它們之間的介電質15、250電性連接。介電質150、250可包括無機材料，例如以下至少其中之一：氫化碳氧化矽(SiCOH)、有機矽酸鹽玻璃(OSG)、氧化矽(SiO2)、氮化矽(SiN)、氟化SiO2(FSG)、甲基倍半矽氧烷(MSQ)，或其多孔版本。介電質150、250可具有與位於各晶圓的後側122、222上的TSV 114、214的表面共面的表面。
更具體地說，並參照第8圖，位於晶圓110的後側122上的TSV 114通過延伸穿過介電質150並與位於晶圓210內的導電墊252連接而與位於晶圓210的前側 232上的金屬線228電性連接。此外，位於晶圓210的後側222上的TSV 214通過延伸穿過介電質250並與位於晶圓310內的導電墊352連接而與位於晶圓310的前側332上的金屬線328電性連接。儘管未顯示，但這同樣適用於晶圓310的TSV 314與可能需要附著的另一個相鄰晶圓。應當理解，堆疊400可包括任意數目的晶圓，而不背離本揭露的態樣。
仍請參照第8圖，在堆疊400內的最底部晶圓的後側(例如晶圓110的前側132)上可形成一個或多個微柱390。微柱390可包括傳統的焊接凸塊，其可促進堆疊400與另一個IC晶片、裝置或堆疊(未顯示)的連接。微柱390可在移除臨時操作晶圓140(第7圖)以後形成，如第8圖中所示，或者可在形成臨時操作晶圓140之前設於晶圓110上。若在形成微柱390以後形成臨時操作晶圓140，則可能有必要包括足夠厚度的黏著劑142(第7圖)，以基本上包圍微柱390。
在另一個實施例中，如第9圖中所示，在如上關於第4圖所述形成介電質150以後，在另一個介電質504內可形成多個導電墊502。導電墊502可包括電性連接各TSV 114的作用導電墊502a以及未與IC結構100內的任意其它結構例如TSV 114電性連接的非作用導電墊502b。導電墊502可包括任意當前已知或以後開發的導電墊材料，例如用於導電墊252的材料。
仍請參照第9圖，介電質504可沉積於晶圓 110的後側122上的介電質150以及暴露於其中的TSV 114上方。導電墊502可例如通過傳統的單或雙鑲嵌製程形成於介電質504中。現有技術所已知的單鑲嵌製程將包括在單個層內形成溝槽或開口，用填充材料填充該溝槽或開口，並平坦化，接著在另一層中重複該製程。相比之下，雙鑲嵌製程允許形成延伸於不止一層內的溝槽或開口，同時填充延伸於不止一層內的該溝槽或開口，並平坦化。在任一製程中，可使用遮罩控制形成該溝槽或開口的位置。
在下方設置有TSV 114的位置處的介電質504內可形成作用導電墊502a。以此方式，作用導電墊502a可提供將位於第一晶圓110內的TSV 114與位於第二晶圓210內的金屬線230及導電墊252連接的途徑。此外，在介電質504內可形成一個或多個非作用導電墊502b，以在該鑲嵌製程期間幫助保持並控制平坦化。非作用導電墊502b之所以如此命名是因為它們不與IC結構100內的其它結構電性連接。
現在請參照第10圖，可將第二晶圓210附著至晶圓110，以形成積體電路(IC)堆疊500。如上關於第5圖所述，可將晶圓210附著至晶圓110。不過，在此實施例中，晶圓210的導電墊252及/或金屬線228通過位於介電質504內的導電墊502與位於晶圓110內的TSV 114電性連接。此外，該混合-氧化物接合發生於位於晶圓110的後側上的介電質504及其中的導電墊502與位於晶圓210的前側232上的介電質230及導電墊252或金屬線228之 間。可如上關於第6圖至第8圖所述繼續依據此實施例的該製程。
與傳統IC堆疊相比，本揭露提供通過混合-氧化物接合以前對後取向附著晶圓，而無需在各晶圓之間的微柱或底部填充層。因此，減小多餘電容及熱阻。此外，本揭露的TSV在晶圓附著之前形成於或設於各晶圓內。因此，無需在晶圓附著以後延伸穿過整個堆疊形成單個TSV。另外，本揭露的接合介面包括位於第一晶圓的後側上的基板內的TSV與位於第二相鄰晶圓的前側上的介電質內的BEOL結構通過設於它們之間的一個或多個介電質以及/或者導電墊相接。
如上所述的方法可用於積體電路晶片的製造中。製造者可以原始晶圓形式(也就是，作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。在後一種情況中，該晶片設於單晶片封裝件中(例如塑膠承載件，其具有附著至主機板或其它更高層次承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，接著將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置整合，作為(a)中間產品例如主機板的部分，或者作為(b)最終產品的部分。該最終產品可為包括積體電路晶片的任意產品，關於範圍從玩具及其它低端應用直至具有顯示器、鍵盤或其它輸入裝置以及中央處理器的先進電腦產品。
本文中所使用的術語僅是出於說明特定實施例的目的，並非意圖限制本揭露。本文中所使用的術語“第一”、“第二”等不表示任意順序、數量或重要性，而是用以區別元件。除非上下文中另外明確指出，否則本文中所使用的單數形式“一個”以及“該”也意圖包括複數形式。另外，應當理解，術語“包括”用於本說明書中時表明所述特徵、整體、步驟、操作、元件和/或組件的存在，但不排除存在或添加一個或多個其它特徵、整體、步驟、操作、元件、組件，和/或其群組。“可選的”或“可選地”是指後續所述事件或情況可能發生或者可能不發生，且該說明包括事件發生的情況以及其不發生的情況。
這裡在說明書及申請專利範圍各處所使用的近似語言可用以修飾任意量化表達，可允許該量化表達變動而不會導致與其相關的基本功能的改變。因此，由一個或多個術語例如“約”及“基本上”修飾的值不限於所指定的精確值。在至少一些情況下，該近似語言可對應用以測量該值的儀器的精度。在這裡以及說明書及申請專利範圍各處，範圍限制可組合和/或互換，此類範圍被識別並包括包含於其中的所有子範圍，除非上下文或語言另外指出。應用於一範圍的特定值的“約”適用於兩個值，且除非依賴於測量該值的儀器的精度，否則可表示所述值的+/-10%。本文中所使用的“基本上”是指提供本揭露的相同技術效果的主要、大部分、完全指定的或任意輕微的偏離。
隨附的申請專利範圍中的所有方式或步驟加 功能元素的相應結構、材料、動作及等同意圖包括結合具體請求保護的其它請求保護的元素執行該功能的任意結構、材料或動作。本揭露的說明用於示例及說明目的，而非意圖詳盡無遺或限於所揭露形式的揭露。許多修改及變更將對於本領域的普通技術人員顯而易見，而不背離本揭露的範圍及精神。實施例經選擇及說明以最佳解釋本揭露的原理及實際應用，並使本領域的普通技術人員能夠理解本揭露針對各種實施例具有適合所考慮的特定應用的各種變更。

Claims (20)

  1. 一種積體電路堆疊，包括：第一晶圓，以前對後取向附著至第二晶圓，其中，各晶圓包括後側及前側，各晶圓的該後側包括位於基板內的半導體穿孔(through-semiconductor-via；TSV)，且各晶圓的該前側包括位於第一介電質內的金屬線，其中，該金屬線與各相應晶圓內的該TSV連接；以及第二介電質，介於該第一晶圓的該基板與該第二晶圓的該第一介電質之間，其中，該第一晶圓的該TSV自該第一晶圓的該基板延伸穿過該第二介電質並與該第二晶圓的該第一介電質內的該金屬線電性連接。
  2. 如申請專利範圍第1項所述的積體電路堆疊，其中，該第二介電質包括無機介電材料。
  3. 如申請專利範圍第2項所述的積體電路堆疊，其中，該無機介電材料包括以下至少其中之一：氫化碳氧化矽(SiCOH)、有機矽酸鹽玻璃(OSG)、氧化矽(SiO 2)、氟化SiO 2(FSG)、甲基倍半矽氧烷(MSQ)，或其多孔版本。
  4. 如申請專利範圍第1項所述的積體電路堆疊，其中，該第一晶圓與該第二晶圓通過混合-氧化物接合附著。
  5. 如申請專利範圍第1項所述的積體電路堆疊，進一步包括：微柱結構，與該第一晶圓的該後側上的該金屬線連接。
  6. 如申請專利範圍第1項所述的積體電路堆疊，進一步包括：第三晶圓，附著至該第二晶圓，該第三晶圓包括後側及前側，該第三晶圓的該後側包括位於基板內的TSV，且該第三晶圓的該前側包括位於第三介電質內的金屬線，其中，該第三晶圓的該金屬線與該第三晶圓中的該TSV連接；以及第四介電質，設於該第二晶圓的該基板與該第三晶圓的該第三介電質之間，其中，該第二晶圓的該TSV自該第二晶圓的該基板延伸穿過該第四介電質並與該第三晶圓的該第三介電質中的該金屬線電性連接。
  7. 如申請專利範圍第1項所述的積體電路堆疊，進一步包括：第三介電質，設於該第二介電質與該第二晶圓的該第一介電質之間；以及作用導電墊，設於該第三介電質內，提供自該第一晶圓的該TSV與該第二晶圓的該金屬線的電性連接。
  8. 如申請專利範圍第6項所述的積體電路堆疊，進一步包括：導電墊，設於該第二晶圓中的該第一介電質內並提供該第一晶圓的該TSV與該第二晶圓的該金屬線之間的電性連接。
  9. 如申請專利範圍第1項所述的積體電路堆疊，其中，各 晶圓的該TSV包括多個TSV且各晶圓的該金屬線包括多條金屬線，其中，各晶圓內的該多條金屬線的各金屬線與該晶圓內的該多個TSV的相應TSV連接，以及其中，該第一晶圓的該多個TSV的各TSV自該第一晶圓的該基板延伸穿過該第二介電質並與該第二晶圓的該多條金屬線的相應金屬線電性連接。
  10. 一種形成積體電路堆疊的方法，該方法包括：以前對後取向將第一晶圓與第二晶圓附著，該附著包括通過混合-氧化物接合將位於該第二晶圓的前側上的第一介電質內的金屬線附著至位於第一晶圓的後側上的基板內的半導體穿孔(TSV)。
  11. 如申請專利範圍第10項所述的方法，其中，該附著包括：提供該第一晶圓，該第一晶圓包括位於該第一晶圓的該後側上的該基板內的該TSV以及位於該第一晶圓的前側上的第二介電質內的金屬線；蝕刻該第一晶圓的該基板，以暴露位於該第一晶圓的該後側上的該TSV；在該第一晶圓的該基板上形成第三介電質並平坦化該第三介電質至該第一晶圓的該TSV；以及將位於該第一晶圓上的該第三介電質與位於該第二晶圓的該前側上的該第一介電質接合。
  12. 如申請專利範圍第11項所述的方法，其中，該附著進一步包括： 執行退火以將該第一晶圓的該TSV與該第二晶圓的該金屬線電性連接。
  13. 如申請專利範圍第11項所述的方法，進一步包括：在所述形成該第三介電質以後並在該接合之前：在位於該第一晶圓上的該第三介電質上方形成第四介電質；以及在該第四介電質內形成作用導電墊及非作用導電墊，該作用導電墊提供該第一晶圓的該TSV與該第二晶圓的該金屬線之間的電性連接，且該非作用導電墊與該第一晶圓的該TSV及該第二晶圓的該金屬線電性斷開，其中，該接合包括接合位於該第一晶圓上的該第四介電質與位於該第二晶圓的該前側上的該第一介電質。
  14. 如申請專利範圍第11項所述的方法，進一步包括：在所述提供該第一晶圓以後且在所述蝕刻該基板之前，在該第一晶圓的該前側上形成微柱結構，以使該微柱結構與位於該第一晶圓的該前側上的該第二介電質內的該金屬線連接。
  15. 如申請專利範圍第11項所述的方法，進一步包括：在所述附著之後在該第一晶圓的該前側上形成微柱結構，該微柱結構與位於該第一晶圓的該前側內的第二介電質內的金屬線連接。
  16. 一種積體電路堆疊，包括：多個垂直堆疊晶圓，各晶圓包括後側及前側，各晶 圓的該後側包括位於基板內的半導體穿孔(TSV)，且各晶圓的該前側包括位於第一介電質內的金屬線，其中，該金屬線與各晶圓內的該TSV連接；以及無機介電質，介於該多個垂直堆疊晶圓內的相鄰晶圓之間；其中，該多個垂直堆疊晶圓以前對後取向堆疊，以使一個晶圓的該後側上的該TSV與相鄰晶圓的該前側上的該金屬線通過延伸穿過介於它們之間的該無機介電質電性連接。
  17. 如申請專利範圍第16項所述的積體電路堆疊，其中，各該多個垂直堆疊晶圓通過混合-氧化物接合附著至該多個垂直堆疊晶圓中的相鄰晶圓。
  18. 如申請專利範圍第16項所述的積體電路堆疊，進一步包括：微柱結構，與位於該垂直堆疊晶圓的最底部晶圓的該前側上的該金屬線連接。
  19. 如申請專利範圍第16項所述的積體電路堆疊，其中，該無機介電質包括以下至少其中之一：氫化碳氧化矽(SiCOH)、有機矽酸鹽玻璃(OSG)、氧化矽(SiO 2)、氟化SiO 2(FSG)、甲基倍半矽氧烷(MSQ)，或其多孔版本。
  20. 如申請專利範圍第16項所述的積體電路堆疊，其中，該無機介電質與各晶圓的該後側上的該TSV齊平。
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