CN101814453B - 一种用于硅通孔互连中的硅片对准方法 - Google Patents

一种用于硅通孔互连中的硅片对准方法 Download PDF

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CN101814453B
CN101814453B CN201010141746.6A CN201010141746A CN101814453B CN 101814453 B CN101814453 B CN 101814453B CN 201010141746 A CN201010141746 A CN 201010141746A CN 101814453 B CN101814453 B CN 101814453B
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silicon chip
chip
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王鹏飞
孙清清
丁士进
张卫
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Fudan University
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract

本发明属于高集成度封装技术领域，具体公开了一种用于硅通孔互连中的硅片对准方法。该方法包括在多个硅片进行堆叠互连时，采用电学方法对进行堆叠互连的上下硅片进行对准校正，这样，就可以提高硅片对准的精度，减小互连电阻。通过本发明所述方法制成的集成电路芯片具有高速度和低功耗的性能。

Description

一种用于硅通孔互连中的硅片对准方法
技术领域
本发明属于高集成度封装技术领域，具体涉及一种硅通孔互连封装方法。
背景技术
随着微电子技术的不断发展，芯片制造工艺细微化，促使集成电路封装技术不断发展，并逐渐形成一门相对独立的科技产业。现在，三维封装技术已被认为是未来集成电路封装的发展趋势，而且，三维封装技术已经由芯片级的堆叠芯片封装(stacked die)或者堆叠封装(package on package)技术发展到了晶圆级的硅通孔(Through Silicon Via，TSV)互连封装技术。
硅通孔互连技术是通过在硅片和硅片之间制作垂直通孔，然后在硅片正面和背面形成互连微焊点，这样，多个硅片就可以直接堆叠起来而不用外部引线互连。硅通孔互连技术可以分为先通孔式(via first)和后通孔式(via last)两种。先通孔式技术就是在硅片上集成电路制造完成之前形成互连通孔，这种技术可以是在芯片制造的最初几步内形成硅通孔互连，也可以是在BEOL(Back-end of Line)之前形成硅通孔互连。后通孔式技术则是在BEOL或者整个集成电路制造完成之后再进行硅通孔互连。硅通孔内的填充材料包括一个绝缘层和一个用于导电的金属层或者高掺杂的多晶硅。考虑到降低互连电阻，提高芯片工作频率，多传感系统的硅通孔三维封装中采用铜作为硅通孔互连金属比较有利。与以往的IC封装键合和使用凸点的堆叠技术不同，硅通孔互连技术能够使芯片在三维方向堆叠的密度最大，外形尺寸最小，并且大大改善了芯片速度和低功耗的性能。
作为当前最先进的晶圆级封装技术，硅通孔互连技术现在还处于开发的早期阶段，存在着不少技术难点，比如晶圆减薄技术、硅片对准技术、深孔刻蚀技术和深孔铜填充工艺和设备等都需要重新开发。进行堆叠时，硅片的对准与否会影响硅片之间的互连电阻，进而影响芯片的工作频率，从而使芯片的三维叠层不能在更广的领域中得到应用。
发明内容
本发明的目的在于提出一种用于硅通孔互连中的硅片对准方法，以减小堆叠时硅片之间的互连电阻，提高芯片的工作频率，使得芯片的三维叠层能够在更广的领域中得到应用。
为达到本发明的上述目的，本发明提出了一种采用电学方法对进行堆叠互连的上下硅片进行辅助对准的方法，具体步骤包括：
提供两个或多个完成通硅孔结构的硅片；
在所述硅片的正面和背面形成互连微焊点；
将所述硅片进行堆叠互连；
采用电学方法对堆叠互连的上下硅片进行对准校正。
进一步地，所述硅片的硅通孔结构包括至少一个导电层和一个将所述导电层和所述硅通孔表面隔离的绝缘层，所述的绝缘层为二氧化硅、氮化硅或者为他们之间相混合的绝缘物质，所述的导电层为铝、铜或者高掺杂的多晶硅。所述的电学方法为惠斯登电桥法或者其它电学方法。
本发明所提出的硅片对准方法，具有实施方法简单、可以提高硅片对准的精度、减小互连电阻等优点。采用本发明所述技术制成的集成电路芯片具有高速度和低功耗的性能。
附图说明
图1为已完成硅通孔结构和互连焊点的两个硅片。
图2为图1所示两个硅片接触后的示意图。
图3a至图3c为本发明提供的一种使用惠斯登电桥法对图2所示接触后的硅片进行校正对准的原理示意图。
具体实施方式
下面将参照附图对本发明的一个示例性实施方式作详细说明。参考图是本发明的理想化实施例的示意图，以下实施例仅是说明性的，本发明不受以下实施例的限制。
提供两个已完成硅通孔结构和互连焊点的硅片，图1为所提供硅片的侧视图。如图1所示，硅片2中，所示20为硅部分，所示21为硅通孔和互连焊点部分；硅片3中，所示30为硅部分，所示31为硅通孔和互连焊点部分。
接下来，将硅片2和和硅片3进行堆叠互连，如图2所示。
在硅片2和硅片3进行接触时，硅片2和硅片3可能会出现对准偏差，这样就会影响互连电阻，进而影响集成电路的性能。通过大家熟知的惠斯登电桥测量电阻的方法，可以对硅片2和硅片3进行对准校正。
在图2所示结构中引入测量节点a、b、c和d，则在节点a和节点b之间存在电阻R1，节点b和节点c之间存在电阻R2，节点a和节点d之间存在电阻R3，节点d和节点c之间存在电阻R4，如图3a所示，图3b为图3a所示结构的正视图。
在节点a和节点c之间加一个电源U和开关K，在节点b和节点d之间加电压测量计G，这样就构成了一个惠斯登电桥电路，其等效电路如图3c所示。
当硅片2和硅片3精确对准时，有R1*R4＝R2*R3，根据惠斯登平衡电桥测量电阻的原理，此时节点b和节点d具有相同的电位。因此，通过调节硅片2和硅片3，使电压测量计G的测量值显示为零时，硅片2和硅片3可达到精确对准。
如上所述，在不偏离本发明精神和范围的情况下，还可以构成许多有很大差别的实施例。应当理解，除了如所附的权利要求所限定的，本发明不限于在说明书中所述的具体实例。

Claims (4)

1.一种用于硅通孔互连中的硅片对准方法，其特征在于具体步骤包括：
提供两个或多个完成硅通孔结构的硅片；
在所述硅片的正面和背面形成互连焊点；
将所述硅片进行堆叠互连；
采用惠斯登电桥法对堆叠互连的上下硅片进行对准校正。
2.根据权利要求1所述的硅片对准方法，其特征在于，所述硅片的硅通孔结构包括至少一个导电层和一个将所述导电层和所述硅通孔表面隔离的绝缘层。
3.根据权利要求2所述的硅片对准方法，其特征在于，所述的绝缘层为二氧化硅、氮化硅或者为他们之间相混合的绝缘物质。
4.根据权利要求2所述的硅片对准方法，其特征在于，所述的导电层为铝、铜或者掺杂的多晶硅。
CN201010141746.6A 2010-04-08 2010-04-08 一种用于硅通孔互连中的硅片对准方法 Expired - Fee Related CN101814453B (zh)

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KR102337617B1 (ko) 2013-01-23 2021-12-08 루돌프 테크놀로지스 인코퍼레이티드 Tsv 마이크로 제조 프로세스 및 제품들의 특성화
CN103500721B (zh) * 2013-10-21 2016-01-27 上海华力微电子有限公司 量测通孔与下层金属线对准偏差的方法
CN105742226B (zh) * 2014-12-09 2019-05-21 中国科学院微电子研究所 半导体器件制造方法
US9583490B2 (en) 2015-01-20 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Inverters and manufacturing methods thereof
US9406697B1 (en) 2015-01-20 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and manufacturing methods thereof
US10163864B1 (en) * 2017-08-16 2018-12-25 Globalfoundries Inc. Vertically stacked wafers and methods of forming same
CN113823576B (zh) * 2020-06-18 2023-07-04 中芯国际集成电路制造(北京)有限公司 一种半导体测试结构及其形成方法
CN113611686A (zh) * 2021-07-06 2021-11-05 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） 半导体测试结构及其制造方法、测试方法
CN115295524B (zh) * 2022-10-08 2023-02-03 合肥本源量子计算科技有限责任公司 一种硅通孔互联结构和量子计算机

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