WO2011124091A1 - 一种用于硅通孔互连中的硅片对准方法 - Google Patents

一种用于硅通孔互连中的硅片对准方法 Download PDF

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Publication number
WO2011124091A1
WO2011124091A1 PCT/CN2011/000608 CN2011000608W WO2011124091A1 WO 2011124091 A1 WO2011124091 A1 WO 2011124091A1 CN 2011000608 W CN2011000608 W CN 2011000608W WO 2011124091 A1 WO2011124091 A1 WO 2011124091A1
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silicon
silicon wafer
resistors
wafers
alignment
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PCT/CN2011/000608
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English (en)
French (fr)
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王鹏飞
孙清清
丁士进
张卫
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复旦大学
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Publication of WO2011124091A1 publication Critical patent/WO2011124091A1/zh
Priority to US13/304,149 priority Critical patent/US20120309118A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the invention belongs to the field of high integration packaging technology, and in particular relates to a through silicon via interconnection packaging method. Background technique
  • the through-silicon via interconnection technique is to make vertical vias between the silicon wafer and the silicon wafer, and then form interconnect micro solder joints on the front and back sides of the silicon wafer, so that multiple silicon wafers can be stacked directly without external Lead interconnects.
  • the through-silicon via interconnection technology can be divided into two types: via f i rs t and via las t.
  • the first through-hole technology is to form interconnect vias before the silicon integrated circuit is fabricated. This technique can be used to form through-silicon via interconnects in the first few steps of chip fabrication, or it can be in BE0L (Back-end). A line of silicon via interconnects were formed before.
  • the post via technology is a TSV interconnect after the BE0L or the entire integrated circuit is fabricated.
  • the fill material in the through silicon vias includes an insulating layer and a metal layer for conduction or highly doped polysilicon. Considering the reduction of the interconnect resistance and the increase of the chip operating frequency, it is advantageous to use copper as the through-silicon interconnect metal in the through-hole three-dimensional package of the multi-sensor system. Unlike previous IC package bonding and bump-based stacking techniques, through-silicon via interconnect technology enables the chip to be stacked in the most three-dimensional direction with the highest density, smallest form factor, and greatly improved chip speed and low power consumption.
  • the object of the present invention is to provide a silicon wafer alignment method for a silicon via interconnection to reduce the interconnection resistance between the silicon wafers during stacking, and to increase the operating frequency of the chip, so that the three-dimensional stack of the chip can Applied in a wider field.
  • the present invention provides a method for electrically assisting the alignment of upper and lower silicon wafers for stack interconnection, and the specific steps include:
  • the alignment of the upper and lower silicon wafers of the stacked interconnects is electrically corrected.
  • the through silicon via structure of the silicon wafer includes at least one conductive layer and an insulating layer separating the conductive layer from the surface of the through silicon via, the insulating layer being silicon dioxide, silicon nitride or For the insulating material mixed between them, the conductive layer is aluminum, copper or highly doped polysilicon.
  • the electrical method is a Wheatstone balanced bridge method, which specifically includes: forming a contact resistance after the bottom solder joint of the upper silicon wafer and the top solder joint of the lower silicon wafer, wherein each two resistors are connected in series, The electrical node between the two resistors is A, and then two sets of resistors connected in series are connected in parallel; a voltage is applied across the two series resistors in parallel, and the voltage difference between the two nodes A of the two series resistors is compared The voltage difference between the two nodes A measured when the upper and lower silicon wafers are completely aligned is 0 V; the smaller the voltage difference between the two nodes A, the better the alignment of the upper and lower silicon wafers. .
  • the silicon wafer alignment method proposed by the invention has the advantages of simple implementation method, high precision of silicon wafer alignment, and reduced interconnection resistance.
  • Integrated circuit chips fabricated using the techniques of the present invention have high speed and low power consumption performance.
  • BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows two silicon wafers having completed through-silicon via structures and interconnect pads.
  • Figure 2 is a schematic view of the two silicon wafers shown in Figure 1 after contact.
  • 3a to 3d are schematic diagrams showing the principle of correcting alignment of the contacted silicon wafer shown in FIG. 2 by using the Wheatstone bridge method. The best way to implement the invention
  • Figure 1 is a schematic diagram of the structure of the provided silicon wafer.
  • 20 is a silicon portion
  • 21 is a through-silicon via and an interconnect pad portion, wherein a silicon via portion is located between the silicon 20, and is located on the front side of the silicon 20 and The back side (upper and lower in the figure) is the interconnection pad portion;
  • 30 is a silicon portion, and 31 is a through-silicon via and an interconnect pad portion, which is located between the silicon 30.
  • the through silicon via portions are located on the front and back sides of the silicon 30 (upper and lower in the figure) as interconnecting pads.
  • the silicon wafer 2 and the silicon wafer 3 are stacked and interconnected as shown in FIG.
  • alignment defects may occur between the silicon wafer 2 and the silicon wafer 3, which may affect the interconnection resistance, thereby affecting the performance of the integrated circuit.
  • the alignment of the silicon wafer 2 and the silicon wafer 3 can be performed by the well-known method of measuring the resistance of the Wheatstone bridge.
  • each measurement node a, b, c and d is selected, then there is a resistor R1 between the node a and the node b, and a resistor R2 exists between the node b and the node c, and the node a and the node d There is a resistor R3 between them, and there is a resistor R4 between the node d and the node c.
  • the distribution of each measurement node a, b, c, d is shown in Fig. 3c.
  • Figs. 3a and b the specific position of each node on the silicon wafer can be understood.
  • Fig. 3b and Fig. 3b respectively show the silicon wafer stack interconnection structure seen from two different directions.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

一种用于硅通孔互连中的硅片对准方法 技术领域
本发明属于高集成度封装技术领域，具体涉及一种硅通孔互连封装方法。 背景技术
随着微电子技术的不断发展， 芯片制造工艺细微化， 促使集成电路封装 技术不断发展， 并逐渐形成一门相对独立的科技产业。 现在， 三维封装技术 已被认为是未来集成电路封装的发展趋势, 而且， 三维封装技术已经由芯片 级的堆叠芯片封装 ( s tacked die )或者堆叠封装 ( ackage on package )技 术发展到了晶圆级的硅通孔 ( Through Si l icon Via , TSV ) 互连封装技术。
. 硅通孔互连技术是通过在硅片和硅片之间制作垂直通孔， 然后在硅片正 面和背面形成互连微焊点， 这样， 多个硅片就可以直接堆叠起来而不用外部 引线互连。硅通孔互连技术可以分为先通孔式 （via f i rs t)和后通孔式 （via las t)两种。 先通孔式技术就是在硅片上集成电路制造完成之前形成互连通 孔， 这种技术可以是在芯片制造的最初几步内形成硅通孔互连， 也可以是在 BE0L ( Back-end of Line )之前形成硅通孔互连。 后通孔式技术则是在 BE0L 或者整个集成电路制造完成之后再进行硅通孔互连。 硅通孔内的填充材料包 括一个绝缘层和一个用于导电的金属层或者高掺杂的多晶硅。 考虑到降低互 连电阻， 提高芯片工作频率， 多传感系统的硅通孔三维封装中采用铜作为硅 通孔互连金属比较有利。 与以往的 IC封装键合和使用凸点的堆叠技术不同， 硅通孔互连技术能够使芯片在三维方向堆叠的密度最大， 外形尺寸最小， 并 且大大改善了芯片速度和低功耗的性能。
作为当前最先进的晶圆级封装技术， 硅通孔互连技术现在还处于开发的 早期阶段， 存在着不少技术难点， 比如晶圆减薄技术、 硅片对准技术、 深孔 刻蚀技术和深孔铜填充工艺和设备等都需要重新开发。 进行堆叠时， 硅片的 对准与否会影响硅片之间的互连电阻， 进而影响芯片的工作频率， 从而使芯 片的三维叠层不能在更广的领域中得到应用。 发明的公开
本发明的目的在于提出一种用于硅通孔互连中的硅片对准方法， 以减小 堆叠时硅片之间的互连电阻， 提高芯片的工作频率， 使得芯片的三维叠层能 够在更广的领域中得到应用。
为达到本发明的上述目的， 本发明提出了一种采用电学方法对进行堆叠 互连的上下硅片进行辅助对准的方法， 具体步骤包括：
提供两个或多个完成通硅孔结构的硅片；
分别在所述硅片的正面和背面形成互连微焊点；
将所述硅片进行堆叠互连；
采用电学方法对堆叠互连的上下硅片进行对准校正。
进一步地， 所述硅片的硅通孔结构包括至少一个导电层和一个将所述导 电层和所述硅通孔表面隔离的绝缘层， 所述的绝缘层为二氧化硅、 氮化硅或 者为他们之间相混合的绝缘物质， 所述的导电层为铝、 铜或者高掺杂的多晶 硅。
所述的电学方法为惠斯登平衡电桥法， 具体包括： 上硅片的底部焊点和 下硅片的顶部焊点接触后形成 4个接触电阻，其中，每两个电阻串联成一组， 两电阻之间的电学节点为 A, 之后将两组串联的电阻并联； 在所述并联的两 串电阻两端施加一个电压，并比较所述的两串电阻中的两个节点 A的电压差， 在上下硅片完全对准时所测得的所述的两个节点 A的电压差为 0 V； 所述两 个节点 A的电压差越小， 则上下硅片对准越好。。
本发明所提出的硅片对准方法， 具有实施方法简单、 可以提高硅片对准 的精度、 减小互连电阻等优点。 采用本发明所述技术制成的集成电路芯片具 有高速度和低功耗的性能。 附图的筒要说明 图 1为已完成硅通孔结构和互连焊点的两个硅片。
图 2为图 1所示两个硅片接触后的示意图。
图 3a至图 3d为本发明提供的一种使用惠斯登电桥法对图 2所示接触后 的硅片进行校正对准的原理示意图。 实现本发明的最佳方式
下面将参照附图对本发明的一个示例性实施方式作详细说明。 参考图是 本发明的理想化实施例的示意图， 以下实施例仅是说明性的， 本发明不受以 下实施例的限制。
提供两个已完成硅通孔结构和互连焊点的硅片， 图 1为所提供硅片的结 构示意图。 如图 1所示， 硅片 2中， 所示 20为硅部分， 所示 21为硅通孔和 互连焊点部分， 其中位于硅 20之间的为硅通孔部分， 位于硅 20正面和背面 (图中的上面和下面）的为互连焊点部分； 硅片 3中， 所示 30为硅部分， 所 示 31为硅通孔和互连焊点部分， 其中位于硅 30之间的为硅通孔部分， 位于 硅 30正面和背面 （图中的上面和下面） 的为互连焊点部分。
接下来， 将硅片 2和和硅片 3进行堆叠互连， 如图 2所示。
在硅片 2和硅片 3进行接触时， 硅片 2和硅片 3可能会出现对准偏差， 这样就会影响互连电阻， 进而影响集成电路的性能。 通过大家熟知的惠斯登 电桥测量电阻的方法， 可以对硅片 2和硅片 3进行对准校正。
在图 2所示结构中选取四个测量节点 a、 b、 c和 d， 则在节点 a和节点 b 之间存在电阻 Rl，节点 b和节点 c之间存在电阻 R2 , 节点 a和节点 d之间存 在电阻 R3，节点 d和节点 c之间存在电阻 R4。 各测量节点 a、 b、 c、 d的分布 如图 3c所示， 结合图 3a和 b， 可以理解各节点在硅片上的具体位置。 其中， 图 和 3b分别表示从两个不同方向看到的硅片堆叠互连结构。
在节点 a和节点 c之间加一个电源 U和开关 K , 在节点 b和节点 d之间 加电压测量计 G， 这样就构成了一个惠斯^^电桥电路， 其等效电路如图 3c所 示。
当硅片 2和硅片 3精确对准时， 有 R1 *R4=R2 *R3 , 根据惠斯登平衡电桥 测量电阻的原理， 此时节点 b和节点 d具有相同的电位。 因此， 通过调节硅 片 2和硅片 3， 使电压测量计 G的测量值显示为零时， 硅片 2和硅片 3可达 到精确对准。
如上所述， 在不偏离本发明精神和范围的情况下， 还可以构成许多有很 大差别的实施例。 应当理解， 除了如所附的权利要求所限定的， 本发明不限 于在说明书中所述的具体实例。

Claims

权利要求
1、 一种用于硅通孔互连中的硅片对准方法， 其特征在于具体步骤包括： 提供两个或多个完成通硅孔结构的硅片；
分别在所述硅片的正面和背面形成互连焊点；
将所述硅片进行堆叠互连；
釆用电学方法对堆叠互连的上下硅片进行对准校正。
2、根据权利要求 1所述的硅片对准方法， 其特征在于， 所述硅片的硅通 孔结构包括至少一个导电层和一个将所述导电层和所述硅通孔表面隔离的绝 缘层。
3、根据权利要求 2所述的硅片对准方法， 其特征在于， 所述的绝缘层为 二氧化硅、 氮化硅或者为它们之间相混合的绝缘物质。
4、根据权利要求 2所述的硅片对准方法， 其特征在于， 所述的导电层为 铝、 铜或者掺杂的多晶硅。
5、根据权利要求 1所述的硅片对准方法， 其特征在于， 所述的电学方法 为惠斯登平衡电桥法， 具体包括： 上硅片的底部焊点和下硅片的顶部焊点接 触后形成 4个接触电阻， 其中， 每两个电阻串联成一组， 两电阻之间的电学 节点为 A, 之后将两组串联的电阻并联； 在所述并联的两串电阻两端施加一 个电压， 并比较所述的两串电阻中的两个节点 A的电压差， 在上下硅片完全 对准时所测得的所述的两个节点 A的电压差为 0 V； 所述两个节点 A的电压 差越小， 则上下硅片对准越好。
PCT/CN2011/000608 2010-04-08 2011-04-08 一种用于硅通孔互连中的硅片对准方法 WO2011124091A1 (zh)

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CN101814453B (zh) * 2010-04-08 2012-03-21 复旦大学 一种用于硅通孔互连中的硅片对准方法
WO2014116878A1 (en) * 2013-01-23 2014-07-31 Rudolph Technologies, Inc. Characterizing tsv microfabrication process and products
CN103500721B (zh) * 2013-10-21 2016-01-27 上海华力微电子有限公司 量测通孔与下层金属线对准偏差的方法
CN105742226B (zh) * 2014-12-09 2019-05-21 中国科学院微电子研究所 半导体器件制造方法
US9583490B2 (en) 2015-01-20 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Inverters and manufacturing methods thereof
US9406697B1 (en) 2015-01-20 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and manufacturing methods thereof
US10163864B1 (en) * 2017-08-16 2018-12-25 Globalfoundries Inc. Vertically stacked wafers and methods of forming same
CN113823576B (zh) * 2020-06-18 2023-07-04 中芯国际集成电路制造(北京)有限公司 一种半导体测试结构及其形成方法
CN113611686B (zh) * 2021-07-06 2024-06-18 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） 半导体测试结构及其制造方法、测试方法
CN115295524B (zh) * 2022-10-08 2023-02-03 合肥本源量子计算科技有限责任公司 一种硅通孔互联结构和量子计算机

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101271873A (zh) * 2007-03-19 2008-09-24 台湾积体电路制造股份有限公司 半导体晶粒与封装结构
CN101379892A (zh) * 2008-03-27 2009-03-04 香港应用科技研究院有限公司 基于硅通孔的电子元件堆叠的脉冲激光键合方法
US7514276B1 (en) * 2008-08-12 2009-04-07 International Business Machines Corporation Aligning stacked chips using resistance assistance
CN101656197A (zh) * 2008-08-19 2010-02-24 台湾积体电路制造股份有限公司 硅通孔键合结构
CN101814453A (zh) * 2010-04-08 2010-08-25 复旦大学 一种用于硅通孔互连中的硅片对准方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0578899B1 (en) * 1992-07-15 1996-12-27 STMicroelectronics S.r.l. Process for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process
KR100273317B1 (ko) * 1998-11-04 2000-12-15 김영환 반도체 소자 제조 공정에서 미스얼라이먼트 측정을 위한 테스트패턴의 구조와 그 측정방법
JP2001144253A (ja) * 1999-11-12 2001-05-25 Nec Corp 半導体装置のチェックパターン
CN101295002B (zh) * 2007-04-24 2010-09-29 中芯国际集成电路制造(上海)有限公司 互连线失效检测方法
US8492238B2 (en) * 2008-08-14 2013-07-23 Board Of Regents, The University Of Texas System Method and apparatus for fabricating piezoresistive polysilicon by low-temperature metal induced crystallization
EP2341214A1 (en) * 2009-12-29 2011-07-06 Welltec A/S Thermography logging tool

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101271873A (zh) * 2007-03-19 2008-09-24 台湾积体电路制造股份有限公司 半导体晶粒与封装结构
CN101379892A (zh) * 2008-03-27 2009-03-04 香港应用科技研究院有限公司 基于硅通孔的电子元件堆叠的脉冲激光键合方法
US7514276B1 (en) * 2008-08-12 2009-04-07 International Business Machines Corporation Aligning stacked chips using resistance assistance
CN101656197A (zh) * 2008-08-19 2010-02-24 台湾积体电路制造股份有限公司 硅通孔键合结构
CN101814453A (zh) * 2010-04-08 2010-08-25 复旦大学 一种用于硅通孔互连中的硅片对准方法

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