TWI751702B - 半導體元件及其製造方法 - Google Patents
半導體元件及其製造方法 Download PDFInfo
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- TWI751702B TWI751702B TW109131823A TW109131823A TWI751702B TW I751702 B TWI751702 B TW I751702B TW 109131823 A TW109131823 A TW 109131823A TW 109131823 A TW109131823 A TW 109131823A TW I751702 B TWI751702 B TW I751702B
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- semiconductor element
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- 238000000034 method Methods 0.000 title claims abstract description 53
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- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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Abstract
本案提供一種半導體元件及其製造方法,其中金屬化層位於基板上方,並且電源網格線位於金屬化層內。訊號墊位於金屬化層內並且由電源網格線圍繞。將訊號外部連接電連接至訊號墊。
Description
本揭示案是關於一種半導體元件及其製造方法。
由於各種電子部件(例如,電晶體、二極體、電阻器、電容器等等)的整合密度的持續提高,半導體工業已經經歷了快速生長。在很大程度上,此種整合密度的提高來自最小特徵尺寸的重複減小(例如,將半導體製程節點朝低於20nm節點縮小),此允許更多部件整合進給定區域中。隨著近來對小型化、更高速度及更大帶寬以及更低功耗及潛時的需求的增長,對半導體晶片的更小及更具創造性的封裝技術的需求亦增長。
隨著半導體技術進一步發展,堆疊的半導體元件(例如,3D積體電路(3D integrated circuits;3DIC))已經呈現為有效地進一步減小半導體元件的實體尺寸。在堆疊的半導體元件中,主動電路(諸如,邏輯電路、記憶體、處理器電路等)製造於不同半導體晶圓上。兩個或更多個半導體晶圓可安裝在彼此頂上,以進一步減小半導體
元件的形狀因數。然而,需要進一步改進,以進一步減小尺寸並改進元件的工作特性。
根據一實施例,一種半導體元件包括:在基板上方的金屬化層;位於金屬化層內的電源網格線;位於金屬化層並由電源網格線圍繞的第一訊號墊;及電連接至第一訊號墊的訊號外部連接。
根據另一實施例,半導體元件包括:第一半導體元件的訊號連接;第一半導體元件的通孔,通孔與訊號連接及金屬化層的第一導電部分兩者實體接觸;及在金屬化層內的電源網格,其中電源網格的第一單線圍繞第一導電部分。
根據另一實施例,一種製造半導體元件的方法,包括以下步驟:在第一半導體基板上方形成第一金屬化層,第一金屬化層包括具有第一線的電源網格及訊號連接器,第一線在第一方向上具有第一寬度,訊號連接器與第一線的至少兩側相鄰,訊號連接器具有小於第一方向上的第一寬度的第二寬度;以及形成與訊號連接器電連接的接合墊金屬跡線。
2-2’:線
100:第一半導體元件
101:基板
102:基板導通介層窗
103:主動元件
105:層間介電質層
107:金屬化層
109:介電層
111:頂端金屬層
112:導電特徵
113:介電接合層
115:接合墊通孔跡線
117:接合墊金屬跡線
119:電源網格金屬跡線
121:金屬化層接合墊
201:孔
300:第二半導體元件
302:第二基板
303:第二主動元件
305:第二層間介電質層
307:第二金屬化層
311:第二頂端金屬層
313:第二介電接合層
315:第二接合墊通孔跡線
317:第二接合墊金屬跡線
319:第二電源網格金屬跡線
321:第二金屬化層接合墊
401:線
403:線
405:線
601:步驟
603:步驟
605:步驟
607:步驟
609:步驟
611:步驟
613:步驟
615:步驟
Tk1:厚度
D1,D2,D3,D4:距離
L1,L2:重疊長度/長度
S1,S2:間距
W1,W2,W3:寬度
1-1’,2-2’:線
當結合附圖閱讀時,根據以下詳細描述可更好地理解本揭示案的態樣。應注意,根據工業標準實踐,各種特
徵未按比例繪製。事實上,為論述清楚,各特徵的尺寸可任意地增加或縮小。
第1圖圖示根據一些實施例的第一半導體元件。
第2圖為根據一些實施例的電源網格的俯視圖。
第3圖圖示根據一些實施例的第一半導體元件至第二半導體元件的接合。
第4圖圖示根據一些實施例的可實現的改進。
第5圖圖示根據一些實施例的錯位電源網格金屬跡線。
第6A圖至第6B圖圖示根據一些實施例的流程圖。
以下揭示內容提供許多不同實施例或實例,以便實施發明的不同特徵。下文描述部件及佈置的特定實例以簡化本揭示。當然,此等實例僅為實例且不意欲為限制性。舉例而言,在隨後描述中第一特徵形成在第二特徵上方或在第二特徵上可包括第一特徵及第二特徵形成為直接接觸的實施例,以及亦可包括額外特徵可形成在第一特徵及第二特徵之間,使得第一特徵及第二特徵可不直接接觸的實施例。另外,本揭示案在各實例中可重複元件符號及/或字母。此重複為出於簡單清楚的目的,且本身不指示所論述各實施例及/或配置之間的關係。
另外,空間相對術語,諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者,在此可為便於描述而使用,以描述諸圖中所圖示的一個元件或特徵與另
一(些)元件或(多個)特徵的關係。除圖形中描繪的取向外,空間相對術語意欲包含元件在使用或操作中的不同取向。設備可以不同方式取向(旋轉90度或為其他取向)並且可因此同樣地解釋在此使用的空間相對描述詞。
以下關於將想法結合進三維積體電路(3DIC)結構中的特定實施例來描述實施例。然而,實施例並不限於本文描述的明確實施例,並且可結合進各種應用中。
現參考第1圖,圖示第一半導體元件100,具有:基板101、延伸穿過基板101的基板導通介層窗(through substrate via,TSV)102、在基板101上的主動元件103、在主動元件103上方的層間介電質(interlayer dielectric,ILD)層105、及在層間介電質層105上方的金屬化層107。在一實施例中,第一半導體元件100可為半導體晶圓的部分(未完全圖示,因為半導體晶圓的剩餘部分遠離第1圖所示結構延伸),例如對於基板上晶圓上晶片(chip on wafer on substrate;CoWoS)實施例。在其他實施例中,第一半導體元件100可與半導體晶圓分隔,諸如已經形成並單一化。可使用任何適合的實施例。
基板101可包括摻雜或未摻雜的塊狀矽,或絕緣體上矽(silicon-on-insulator;SOI)基板的主動層。通常,SOI基板包括具有半導體材料的層,該等半導體材料為諸如矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator;SGOI)、或上述的組合。
可使用的其他基板包括多層基板、梯度基板、或混合取向(hybrid orientation)基板。另外,製程中此時的基板101可為半導體晶圓的部分(半導體晶圓的整個晶圓未在第1圖中圖示),此部分將在稍後步驟中進行單一化。
在基板101內,基板導通介層窗102可形成為延伸穿過基板101,以提供從基板101的第一側至基板101的第二側的資料訊號的快速通道。在一實施例中,基板導通介層窗102可藉由初始形成進入基板101的矽穿孔(through silicon via;TSV)開口而形成。矽穿孔開口可藉由施加合適的光阻劑並使其顯影,以及移除基板101暴露至期望深度的部分而形成。矽穿孔開口可形成以延伸進基板101中達一深度,此深度大於基板101的最終期望高度。因此,當深度取決於整體設計時,深度可在約20μm與約200μm之間,諸如約50μm的深度。
一旦矽穿孔開口已經在基板101內形成,則矽穿孔開口可內襯有襯墊。襯墊可為例如由正矽酸乙酯(TEOS)或氮化矽形成,儘管可使用任何適合的介電質材料。襯墊可使用電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition;PECVD)製程形成,儘管可使用其他適合製程,諸如物理氣相沉積或熱製程。另外,襯墊可形成至在約0.1μm與約5μm之間,諸如約1μm的厚度。
一旦襯墊已經沿著矽穿孔開口的側壁及底部形成,則阻障層可形成並且矽穿孔開口的剩餘部分可填充第一導
電材料。第一導電材料可包含銅,儘管可利用其他適合材料,諸如鋁、合金、摻雜多晶矽、上述的組合等。第一導電材料可藉由將銅電鍍在晶種層上、填充及溢出矽穿孔開口而形成。一旦矽穿孔開口已經填滿,則多餘襯墊、阻障層、晶種層及矽穿孔開口外的第一導電材料可經由平坦化製程(諸如化學機械研磨(chemical mechanical polishing;CMP))而移除,儘管可使用任何適當移除製程。
一旦矽穿孔開口已經填滿,則減薄基板101的第二側以暴露基板導通介層窗102的開口,並由導電材料形成延伸穿過基板101的基板導通介層窗102。在一實施例中,減薄基板101的第二側可留下暴露的基板導通介層窗102。減薄基板101的第二側可藉由平坦化製程(諸如CMP或蝕刻)而執行。
主動元件103在第1圖中表示為單一電晶體。然而,如熟習此技藝者將認識到,各種主動元件(諸如電容器、電阻器、電感器等)可用以生成第一半導體元件100的設計的期望結構及功能要求。主動元件103可使用任何適當方法在基板101內或基板101的表面上形成。
層間介電質層105可包括諸如硼磷矽玻璃(boron phosphorous silicate glass;BPSG)的材料,儘管可使用任何適當介電質。層間介電質層105可使用諸如電漿強化化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)的製程而形成,儘管可使
用諸如低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)等其他製程。層間介電質層105可形成至在約100Å與約3,000Å之間的厚度。
金屬化層107可形成於基板101、主動元件103、及層間介電質層105上方,並且經設計以連接不同主動元件103以形成功能電路系統。儘管在第1圖中圖示為兩層,但金屬化層107由介電質材料及導電材料的交替層形成,並且可經由任何適當製程(諸如沉積、鑲嵌、雙重鑲嵌等等)而形成。在一實施例中,可能存在藉由層間介電質層105與基板101分隔的十三個金屬化層,但金屬化層107的確切數目取決於第一半導體元件100的設計。
作為金屬化層107的部分,頂端金屬層111形成為金屬化層107內的最頂層。在一實施例中,頂端金屬層111為第十三個金屬化層,並且包括介電層109及在介電層109內形成的導電特徵112。頂端金屬層111可藉由初始將介電層109沉積於金屬化層107的下層的頂表面上方(例如,金屬化層107的第十二個層上方)而形成。介電層109可藉由化學氣相沉積(chemical vapor deposition;CVD)、物理氣相沉積(physical vapor deposition;PVD)等而沉積。介電層可包括介電質材料(諸如,氧化矽、SiCOH等等),並且可形成至第一厚度Tk1,第一厚度Tk1在約2μm與約4μm之間,諸如約3μm。然而,可利用任何適合材料、厚度及沉積方法。
一旦介電層109已經形成,則可蝕刻介電層109
以形成開口,此些開口暴露金屬化層107的下層的頂表面。在一實施例中,介電層109可使用例如通孔優先雙重鑲嵌製程而蝕刻,藉此利用第一遮罩及蝕刻製程來將通孔圖案至少部分地圖案化及蝕刻成介電層109。一旦蝕刻通孔圖案,則利用第二遮罩及蝕刻製程來將溝槽圖案圖案化及蝕刻成介電層109,其中蝕刻溝槽圖案的步驟進一步將通孔圖案延伸穿過介電層109以暴露下層(例如,金屬化層107的第十二個金屬化層)。
然而,儘管描述通孔優先雙重鑲嵌結構,此僅意指說明性的而不意欲對實施例的限制。相反,可利用任何一種或多種適合的製程來形成頂端金屬層111的通孔開口及溝槽開口。例如,可使用溝槽優先雙重鑲嵌製程,或者甚至多個單鑲嵌製程。所有此種製程完全意欲包括在實施例的範疇內。
一旦已經形成通孔開口及溝槽開口,導電特徵112可藉由使用例如鍍敷製程在通孔開口及溝槽開口中沉積導電材料而形成。在一實施例中,導電特徵112可包括導電溝槽及導電通孔,此些導電通孔將導電溝槽連接至下層結構(例如,金屬化層107的第十二個層)。在一實施例中,導電材料可為銅、銅合金、鋁、鋁合金、上述的組合等。然而,可利用任何合適材料及任何合適的形成製程。
一旦通孔開口及溝槽開口已經由導電材料填充及/或溢出,則導電特徵112可藉由從通孔開口及溝槽開口外部移除多餘材料而形成。在一實施例中,移除可使用平坦
化製程(諸如,化學機械研磨(CMP)製程)而執行。然而,可使用任何適當的移除製程。
在一實施例中,形成在介電層109內形成的導電特徵112以在頂端金屬層111內產生多個導電結構,該多個導電結構在第一半導體元件100及第二半導體元件300(在第1圖中未圖示,但下文關於第3圖圖示並進一步描述)的互連中執行單獨的功能。在一個實施例中,導電特徵112將在頂端金屬層111內形成電源網格金屬跡線119與金屬化層接合墊121兩者。在一實施例中,金屬化層接合墊121用以幫助將電訊號(非電源及接地)從下金屬化層107按路線傳遞至上接合墊金屬跡線117(下文進一步描述),以便電訊號可隨後按路線傳遞至第二半導體元件300或從第二半導體元件300接收電訊號。
另外,電源網格金屬跡線119形成電源網格的部分,此電源網格的部分將用以在第一半導體元件100與第二半導體元件300之間供應電源連接及接地連接。藉由在第一半導體元件100與第二半導體元件300之間供應電力,未穿過3DIC堆疊(例如,第一半導體元件100、第二半導體元件、及堆疊內的任何其他半導體元件的堆疊)佈線的額外連接不是必需的並且可省略的。此種省略可進一步減少堆疊需要的表面面積,從而導致較小的整體元件。
儘管圖示電源網格金屬跡線119及金屬化層接合墊121,但此意欲為說明性的而不意欲限制。相反,任何適當數目的其他結構亦可位於金屬化層107的頂端金屬層
111內。所有此種結構及結構組合可利用,並且所有此種組合完全意圖包括在實施例的範疇內。
然而,藉由堆疊第一半導體元件100及第二半導體元件300(或甚至堆疊未單獨圖示的更多半導體元件),整體功耗是習用二維設計的至少雙倍(例如,位於堆疊內的半導體元件的數目的n倍)或更多倍,從而排除習用的二維電源網格設計。
考慮到功耗的增大,電源網格在一些實施例中可將個別電源網格金屬跡線119佈置成一系列位於頂端金屬層111內的條紋。從電源網格角度,個別條紋將理想地連續延伸跨過第一半導體元件100的整個接合表面。然而,金屬化層接合墊121的存在及將金屬化層接合墊121連接至接合墊金屬跡線117(例如,用以將訊號傳遞至第二半導體元件300及從第二半導體元件300傳遞訊號)的需求,阻止了理想情況的完全實現,因為用於訊號的金屬化層接合墊121的引入將會將電源網格金屬跡線119斷成具有減小的長度的個別段。若此沒有被適當地處理(如下文關於第2圖進一步描述),則電源網格金屬跡線119的總電阻將增大並且將導致整個電源網格中的更高壓降。
第1圖另外圖示介電接合層113在金屬化層107上方的形成。介電接合層113可用於熔接(亦稱作氧化物至氧化物接合),作為混合接合(hybrid bond)的部分(如下文關於第3圖進一步描述)。根據一些實施例,介電接合層113由含矽介電質材料(諸如氧化矽、氮化矽等)形
成。可使用任何適當方法,諸如CVD、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDPCVD)、PVD、原子層沉積(atomic layer deposition,ALD)等,將介電接合層113沉積至約0.65μm與約6μm之間的厚度,諸如約5.5μm。然而,可使用任何適合材料、沉積製程及厚度。
一旦形成,可平坦化介電接合層113以提供平坦表面用於進一步處理。在一實施例中,可使用平坦化製程(諸如CMP)平坦化介電接合層113。然而,亦可使用任何其他適當的平坦化製程。
一旦已經形成介電接合層113,則形成介電接合層113中的開口以暴露金屬化層接合墊121(如第1圖中圖示)及電源網格金屬跡線119(在第1圖中未單獨圖示)的導電部分,為形成接合墊通孔跡線(bond pad via trace;BPVT)115作準備。在一實施例中,將光阻劑施加在介電接合層113的頂表面上方,並接著使用光阻劑及一或多種蝕刻劑來蝕刻介電接合層113以形成開口。用以形成開口的蝕刻可包括乾式蝕刻(例如,反應性離子蝕刻(reactive ion etching,RIE)或中子束蝕刻(neutral beam etching,NBE))、濕式蝕刻等。根據本揭示案的一些實施例,蝕刻在金屬化層107上停止,使得金屬化層接合墊121及電源網格金屬跡線119的導電部分經由介電接合層113中的開口暴露。然而,可使用任何適當的製程。
介電接合層113中的第二開口亦用以加寬開口的部分,為形成接合墊金屬跡線(bond pad metal trace,BPMT)117作準備。在一實施例中,將另一光阻劑施加在介電接合層113的頂表面上方。光阻劑經圖案化並隨後用以蝕刻介電接合層113以形成第二開口。介電接合層113可藉由乾式蝕刻(例如,RIE或NBE)、濕式蝕刻等來蝕刻。
一旦開口及第二開口已經形成於介電接合層113內,則開口及第二開口可填充晶種層及板金屬,以形成接合墊通孔跡線115及接合墊金屬跡線117(其在第1圖內表示為單獨結構但在最終結構中可或不可實體分隔)。晶種層可毯覆沉積於介電接合層113的頂表面、金屬化層接合墊121及電源網格金屬跡線119的暴露的導電部分、及開口及第二開口的側壁上方。晶種層可包括銅層。取決於所需材料,可使用諸如濺射、蒸發、或電漿增強化學氣相沉積(PECVD)等製程來沉積晶種層。板金屬可經由鍍敷製程(諸如電鍍或無電鍍敷)而沉積於晶種層上方。板金屬可包括銅、銅合金等。板金屬可為填充材料。在晶種層之前,阻障層(未單獨圖示)可毯覆沉積於介電接合層113的頂表面、金屬化層接合墊121及電源網格金屬跡線119的暴露的導電部分、及開口及第二開口的側壁上方。阻障層可包括鈦、氮化鈦、鉭、氮化鉭等。
在填充開口及第二開口之後,執行平坦化製程(諸如CMP)以移除晶種層及板金屬的多餘部分,從而形成接
合墊通孔跡線115及接合墊金屬跡線117。在一些實施例中,接合墊通孔跡線115用以將接合墊金屬跡線117與金屬化層接合墊121連接,並且穿過金屬化層接合墊121,將接合墊金屬跡線與金屬化層107以及主動元件103連接。
另外,接合墊金屬跡線117用以將第一半導體元件100實體接合及電連接至上層第二半導體元件300(在第1圖中未圖示但下文關於第3圖進一步描述)。在接合墊金屬跡線117與第二半導體元件300之間電連接的情況下,接合墊金屬跡線117可用以在第一半導體元件100與第二半導體元件300之間發送及/或接收電訊號。
在一實施例中,接合墊通孔跡線115可定大小為如通孔一般以在金屬化層接合墊121與接合墊金屬跡線117之間傳遞電訊號,以促進在第一半導體元件100與第二半導體元件300之間傳遞訊號。在一些實施例中,接合墊通孔跡線115可成型為圓形(在如第2圖所示的俯視圖中),圓形直徑的第一距離D1在約1.25μm與約2.5μm之間,諸如約1.8μm。然而,可使用任何適當的尺寸。
類似地,接合墊金屬跡線117可決定大小以不僅促進在第一半導體元件100與第二半導體元件300之間傳遞訊號,而且決定大小以促進第一半導體元件100接合至第二半導體元件300。在特定實施例中,接合墊金屬跡線117可成型為圓形(在如第2圖所示的俯視圖中),圓形直徑的第二距離D2在約1.5μm與約2.5μm之間,諸
如約2.5μm。然而,可使用任何適當的尺寸。
第2圖圖示第一半導體元件100的俯視圖,其中第1圖為第2圖沿第2圖中線1-1’截取的橫截面視圖,及第2圖圖示第1圖沿線2-2’的俯視圖(其中為了簡明,從第2圖移除介電接合層113)。第2圖圖示電源網格金屬跡線119的兩條電源網格金屬跡線,其成型成電源網格條紋,此藉由將孔201引入個別電源網格金屬跡線119內而降低壓降。藉由包括孔201,用於訊號的接合墊金屬跡線117可穿過孔201放置在電源網格金屬跡線119內,而不使電源網格金屬跡線119分段成彼此分隔的不同部分。因而,在電源網格金屬跡線119不分隔及分段的情況下,電源網格的總電阻可能減小並且穿過電源網格的壓降將更少。
在一實施例中,電源網格金屬跡線119可包括多個平行條紋(例如,彼此平行的多條電源網格金屬跡線119)。在特定實施例中,電源網格金屬跡線119將決定大小成足夠大以適應接合墊金屬跡線117、接合墊通孔跡線115、及金屬化層接合墊121的孔201。在一實施例中,考慮到第一半導體元件100的整體設計以及用於製造第一半導體元件100的特定技術節點所提供的最小及最大間距,電源網格金屬跡線119經決定大小以具有儘可能大的第一寬度W1。因而,當第一寬度W1至少部分取決於半導體製造製程的技術節點時,在一個實施例中,第一寬度W1可在約0.36μm與約10.8μm之間,諸如約10.8μm。
然而,可使用任何適當的寬度。
另外,電源網格金屬跡線119的每一條具有第一重疊長度L1(其中電源網格金屬跡線119的一條電源網格金屬跡線直接鄰接電源網格金屬跡線119的第二條電源網格金屬跡線的距離),第一重疊長度L1等於電源網格金屬跡線119的長度,並且其中長度足以提供電源及接地的所需佈線。在第2圖圖示的實施例中,相鄰電源網格金屬跡線119形成為具有相同長度,並且放置成使得第一重疊長度L1可大致大於4.05μm,諸如約50μm,儘管最小長度將隨著不同處理節點至少部分地變化,並且最大長度至少部分地取決於晶片區域的整體設計及大小。另外,相鄰電源網格金屬跡線119具有彼此連接的端部,使得電源網格金屬跡線119的一條電源網格金屬跡線的整個長度與電源網格金屬跡線119的相鄰一條電源網格金屬跡線重疊。然而,可使用任何適當的長度。
為了確保金屬化層接合墊121與電源網格金屬跡線119之間的適當分隔,金屬化層接合墊121可與電源網格金屬跡線119(例如,藉由介電層109)分隔開第三距離D3。在一些實施例中,第三距離D3至少部分地取決於電源網格金屬跡線119的第一寬度W1及第一重疊長度L1。在一個實施例中,第三距離D3可為第一寬度W1或第一重疊長度L1中較小者的分數,只要已經達到第一閾值,或者可為第一閾值本身的分數。例如,當第一閾值可在約1.35μm與約4.05μm之間,諸如約1.35μm時,第一分數
可為約三分之一。
另外,在一些實施例中,亦可使用多個閾值。例如,若第一寬度W1與第一重疊長度L1兩者滿足第一閾值,則亦可使用高於第一閾值的第二閾值。在此種實施例中,若第一寬度W1與第一重疊長度L1兩者滿足第一閾值及第二閾值兩者,則第三距離D3可設置成第一寬度W1、第一重疊長度L1、或第二閾值的第一分數。
為了說明此些問題,在其中第一閾值為唯一閾值並為1.35μm的特定實施例中,第三距離D3可藉由首先確定第一重疊長度L1及第一寬度W1兩者是否大於1.35μm的第一閾值來確定。若兩者大於第一閾值,則第三距離D3可藉由將第一閾值乘以第一分數來確定。在其中第一分數為三分之一並且第一閾值為1.35的實施例中,第三距離D3可為0.45μm。
在使用多個閾值的另一實施例中,第一分數可保持三分之一,而第一閾值可設置為1.35μm及第二閾值可設置為4.05μm。在此實施例中,若第一寬度W1及第一重疊長度L1兩者大於第一閾值(例如,大於1.35μm)並且亦大於第二閾值(例如,大於4.05μm),則第三距離D3設置成為4.05μm的第二閾值的三分之一。因而,第三距離D3為至少1.35μm。
在使用多個閾值的另一實施例中,第一寬度W1及第一重疊長度L1中一者可均大於第一閾值,但其中一個可低於第二閾值。在此種實施例中,第三距離D3可設置成第
一閾值(而非第二閾值)的第一分數,因為第二閾值的條件尚未滿足。
另外,第一間距S1將電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線分隔。在一實施例中,第一間距S1可按照上述圖案來確定,並且可與第三距離D3相同。例如,第一間距S1可藉由將第一寬度W1及第一重疊長度L1與第一閾值(及,在一些實施例中,第二閾值)進行比較,及隨後使用第一閾值、第二閾值、第一寬度W1、或第一重疊長度L1的分數來確定要求間距來確定。然而,可使用任何適當的間距。
在一實施例中,金屬化層接合墊121亦可具有第二寬度W2,第二寬度W2在約0.36μm與約10.8μm之間,諸如約1.96μm。類似地,電源網格金屬跡線119可具有第三寬度W3,第三寬度W3從孔201延伸至電源網格金屬跡線119的側壁。在一實施例中,第三寬度W3可為約3.97μm。然而,可使用任何適當寬度。
第3圖圖示第一半導體元件100至第二半導體元件300的接合。在一實施例中,第二半導體元件300為一種半導體元件,其經設計以接合至第一半導體元件100並與第一半導體元件100功能性地工作,以提供所需的功能。在第一半導體元件100為例如邏輯晶片、中央處理單元(central processing unit,CPU)晶片、記憶體晶片(例如,DRAM晶片)、此些組合等的實施例中,第二半導體
元件300可為設計成與邏輯晶片一起工作及/或支援邏輯晶片的元件,諸如藉由成為記憶體元件、電源晶片、感測器晶片、此些的組合等。然而,可使用第一半導體元件100與第二半導體元件300之間的功能的任何適當組合。
在一實施例中,第二半導體元件300可具有與第一半導體元件100類似的結構。例如,第二半導體元件300可包括第二基板302(類似於基板101)、第二主動元件303(類似於主動元件103)、第二層間介電質層305(類似於層間介電質層105)、第二金屬化層307(類似於金屬化層107)、第二頂端金屬層311(類似於頂端金屬層111)、第二電源網格金屬跡線319(類似於電源網格金屬跡線119)、第二接合墊通孔跡線315(類似於接合墊通孔跡線115)、第二金屬化層接合墊321(類似於金屬化層接合墊121)、第二接合墊金屬跡線317(類似於接合墊金屬跡線117)、及第二介電接合層313(類似於介電接合層113)。然而,亦可使用任何適當的結構。
在一些實施例中,藉由例如混合接合,將第一半導體元件100接合至第二半導體元件300。在第一半導體元件100及第二半導體元件300的頂表面被平坦化之後,可激發第一半導體元件100及第二半導體元件300的頂表面。激發第一半導體元件100及第二半導體元件300的頂表面的步驟可包括例如乾式處理、濕式處理、電漿處理、暴露於惰性氣體電漿、暴露於H2、暴露於N2、暴露於O2、或上述的組合。在使用濕式處理的實施例中,例如可使用
RCA清洗。在另一實施例中,激發製程可包括其他類型的處理。激發製程有助於第一半導體元件100與第二半導體元件300的混合接合;有利地允許在後續混合接合製程中使用更低的壓力及溫度。
在激發製程後,可將第一半導體元件100及第二半導體元件300接觸。在使用混合接合的特定實施例中,將接合墊金屬跡線117放置成與第二接合墊金屬跡線317實體接觸,並且將介電接合層113放置成與第二介電接合層313實體接觸。在對表面進行化學改性的激發製程中,材料之間的接合製程開始於實體接觸後。
一旦實體接觸已經使接合製程開始,就可藉由使組件經受熱處理及接觸壓力而加強接合。在一實施例中,第一半導體元件100及第二半導體元件300可經受約200kPa或更少的壓力、及約200℃與約400℃之間的溫度,以加強介電接合層113與第二介電接合層313之間的接合。第一半導體元件100及第二半導體元件300可隨後經歷接合墊金屬跡線117的材料的共晶點處或高於共晶點的溫度,例如約150℃與約650℃之間,以將接合墊金屬跡線117熔接至第二接合墊金屬跡線317。如此,第一半導體元件100與第二半導體元件300的熔接形成混合接合的元件。
另外,儘管已經描述了特定製程以啟動及加強第一半導體元件100與第二半導體元件300之間的混合接合,但此些描述意為說明性的,且並不意圖限於此些實施例。相反,可使用烘烤、退火、受壓、或其他接合製程或製程
組合的任何適當組合。所有此種製程完全意圖包括在實施例的範疇內。
另外,儘管已經將混合接合描述為第一半導體元件100接合至第二半導體元件300的一種方法,但此也僅意為說明性的,且並不意圖限於此些實施例。相反,亦可使用任何適當的接合方法,諸如熔焊、銅至銅鍵合等,或者甚至是使用例如球狀網格陣列的焊料接合。可以使用將第一半導體元件100接合至第二半導體元件300的任何適當方法。
最終,亦可包括其他特徵及製程。例如,可包括測試結構以輔助3D封裝或3DIC元件的驗證測試。測試結構可包括例如形成於重新分佈層中或基板上的測試墊,其允許測試3D封裝或3DIC,使用探針及/或探針卡等等。可對中間結構以及最終結構執行驗證測試。另外,本文揭示的結構及方法可與測試方法結合使用以增大產量並降低成本,此測試方法包括對已知良好晶片的中間驗證。
在操作期間,電源網格內的個別電源網格金屬跡線119可連接至電源或者接地。因而,電源網格可用以在第一半導體元件100與第二半導體元件300之間提供電力。類似地,金屬化層接合墊121可連接至主動元件或其他結構,使得電訊號(非簡單地電源或接地)可在第一半導體元件100與第二半導體元件300之間傳遞。
第4圖圖示可藉由穿過電源網格金屬跡線119放置用於電訊號的接合墊金屬跡線117來實現的壓降的比較。
特別地,圖表中圖示,y軸圖示靜態壓降的百分比,而x軸圖示訊號的IO連接的百分比(與電源/接地IO連接相對)。可以看出,在使用大量分段的電源網格金屬跡線119的半導體元件中(在第4圖中由標記為401的線表示),隨著添加更多的用於訊號的IO連接(例如,線沿X軸向右移動)並且電源網格金屬跡線119被分段,在最壞情況下壓降顯著增加。
然而,當IO連接位於電源網格金屬跡線119的孔201內時(在第4圖中,由標記為403的線表示),隨著添加額外的用於訊號的IO連接,靜態壓降顯著降低,並且可與80%的IO訊號連接改進一樣大。另外,具有孔201的本實施例的壓降接近壓降的完全實現的、未分割的理想情況,如標記405的線表示。因此,藉由使用孔201避免分割電源網格金屬跡線119,可以最小化甚至移除由IO連接的位置引起的整體壓降,從而導致整體更有效的操作。
第5圖圖示另一實施例,其可用以幫助將電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線之間的間距減小至第二間距S2。在此實施例中,電源網格金屬跡線119的一條電源網格金屬跡線偏離電源網格金屬跡線119的相鄰一條電源網格金屬跡線。藉由電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線的錯位,電源網格金屬跡線119的第一條
電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線之間的第二重疊長度L2(例如,電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線彼此直接相鄰的距離)減小。藉由減小該距離,電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線之間的干擾可減小。
另外,相對於取決於第一寬度W1以及重疊長度(如上文關於第2圖描述)的第二間距S2,藉由使電源網格金屬跡線119偏離,可減小第二重疊長度L2,而不減小電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線的總長度。藉由減小第二重疊長度L2而不減小實際長度,在使用多個閾值(例如,第一閾值及第二閾值)的實施例中,第二重疊長度L2可下降至低於閾值中的一者(例如,第二閾值),此允許第二間距S2設置成第一閾值的第一分數(而不是設置成第二閾值的第一分數)。因此,可減小第二間距S2,從而允許電源網格金屬跡線119的第一條電源網格金屬跡線更靠近電源網格金屬跡線119放置。藉由將電源網格金屬跡線119彼此靠近放置,額外佈線選項為可用的,並且更多佈線可在同一區域中實現。
在特定實施例中,可將重疊長度L2減小至一距離,其允許減小第二間距S2(例如,電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二
條電源網格金屬跡線之間的間距)。在一些實施例中,重疊長度L2可減小至約1.35μm與約4.05μm之間,諸如約3μm。然而,可使用任何適當的重疊長度。
藉由減小重疊長度L2,亦可減小第二間距S2,因為在電源網格金屬跡線119的第一條與電源網格金屬跡線119的第二條之間存在較少干擾。在一些實施例中,第二間距S2可減少(在一些實施例中基於第一閾值及第二閾值)至約0.45μm與約1.35μm之間,諸如約0.45μm。然而,可使用任何適當的間距。
在第5圖中圖示的另一實施例中,除了藉由將電源網格金屬跡線119的第一條電源網格金屬跡線與電源網格金屬跡線119的第二條電源網格金屬跡線錯位而使第二重疊長度L2減小,電源網格金屬跡線119的每一條電源網格金屬跡線內的孔201的個別一者,當在其個別電源網格金屬跡線119內的第一方向上彼此對齊時,與電源網格金屬跡線119的相鄰一條電源網格金屬跡線內的孔201錯位或不對齊。藉由使相鄰電源網格金屬跡線119中的孔201錯位,將相鄰電源網格金屬跡線119中接合墊通孔跡線115之間的距離增大至第四距離D4。在一實施例中,第四距離D4可在約6μm與約50μm之間,諸如約9μm。然而,任何適當距離可使用並可至少部分地取決於正使用的精確處理節點。
藉由將金屬化層接合墊121放置於電源網格金屬跡線119的線的孔201內使得金屬化層接合墊121與電
源網格金屬跡線119的至少兩側相鄰,可放置用於在半導體元件之間發送及接收訊號的金屬化層接合墊121,而不需要對電源網格金屬跡線119的線進行分割及分段。藉由保持電源網格金屬跡線119連續及不分段,可減少穿過電源網格金屬跡線119的壓降。另外,藉由將電源網格金屬跡線119與孔201彼此偏離,相鄰電源網格金屬跡線119可彼此更靠近放置,從而允許實現額外空間節省。所有此些益處允許更小且更有效的元件。
第6A圖圖示確定第一閾值為使用的唯一閾值的實施例的第三距離D3的流程圖。在第一步驟601中,接收第一寬度W1、第一重疊長度L1及第一閾值T1。在步驟603中進行確定,以查看第一寬度W1及第一長度L1兩者是否皆大於第一閾值T1。若第一寬度W1及第一長度L1兩者大於第一閾值T1,則在步驟605中將第三距離D3設置成第一寬度W1、第一長度L1、或第一閾值T1中最小者的第一分數。然而,可使用任何順序的任何適當步驟。
第6B圖圖示確定第一閾值與第二閾值一起使用的實施例的第三距離D3的另一流程圖。在第一步驟607中,接收第一寬度W1、第一重疊長度L1、第一閾值T1及第二閾值T2。在第二步驟609中進行確定,以查看第一寬度W1及第一長度L1兩者是否皆大於第一閾值T1及第二閾值T2兩者。若確定為是,則在第三步驟611中將第三距離D3設置成第一寬度W1、第一長度L1、及第二閾值T2中最小者的第一分數。若確定為否,則在第四步驟
613中進行確定,以查看第一寬度W1及第一長度L1兩者是否大於第一閾值T1。若是,則將第三距離D3設置成第一閾值T1的第一分數。然而,可使用任何順序的任何適當步驟。
根據一實施例,一種半導體元件包括:在基板上方的金屬化層;位於金屬化層內的電源網格線;位於金屬化層並由電源網格線圍繞的第一訊號墊;及電連接至第一訊號墊的訊號外部連接。在一實施例中,半導體元件進一步包括與第一訊號墊及訊號外部連接實體接觸的接合墊通孔跡線。在一實施例中,半導體元件進一步包括接合至訊號外部連接的另一半導體元件。在一實施例中,半導體元件與另一半導體元件以混合接合進行接合。在一實施例中,半導體元件進一步包括位於金屬化層內並由電源網格線圍繞的第二訊號墊。在一實施例中,第一訊號墊藉由介電質材料與電源網格線分隔。在一實施例中,介電質材料的寬度為約0.45μm。
根據另一實施例,半導體元件包括:第一半導體元件的訊號連接;第一半導體元件的通孔,通孔與訊號連接及金屬化層的第一導電部分兩者實體接觸;及在金屬化層內的電源網格,其中電源網格的第一單線圍繞第一導電部分。根據一實施例,半導體元件進一步包括:金屬化層的第二導電部分;電源網格的第二單線,第二單線圍繞第二導電部分,第二單線不同於第一單線;及第一半導體元件的第二通孔,第二通孔與金屬化層的第二導電部分及第二
外部連接兩者實體接觸。在一實施例中,第一導電部分及第二導電部分彼此對齊。在一實施例中,第一導電部分及第二導電部分彼此錯位。在一實施例中,第一單線與第二單線分隔約0.45μm的距離。在一實施例中,第一單線的寬度為約10.8μm。在一實施例中,第一導電部分的寬度為約1.96μm。
根據另一實施例,一種製造半導體元件的方法,包括以下步驟:在第一半導體基板上方形成第一金屬化層,第一金屬化層包括具有第一線的電源網格及訊號連接器,第一線在第一方向上具有第一寬度,訊號連接器與第一線的至少兩側相鄰,訊號連接器具有小於第一方向上的第一寬度的第二寬度;以及形成與訊號連接器電連接的接合墊金屬跡線。在一實施例中,方法進一步包括將半導體晶片混合接合至接合墊金屬跡線。在一實施例中,方法進一步包括經由接合墊金屬跡線發送電訊號。在一實施例中,方法進一步包括將電源網格連接至電源。在一實施例中,在俯視圖中第一線圍繞訊號連接器。在一實施例中,第一線從第一點延續至第二點,第一點相鄰於訊號連接器的第一側,第二點相鄰於訊號連接器的第二側,第二側與第一側相對。
上文概述若干實施例的特徵或實例,使得熟習此項技術者可更好地理解本揭示案的態樣。熟習此項技術者應瞭解,可輕易使用本揭示案作為設計或修改其他製程及結構的基礎,以便實施本文所介紹的實施例或實例的相同目
的及/或實現相同優勢。熟習此項技術者亦應認識到,此類等效結構並未脫離本揭示案的精神及範疇,且可在不脫離本揭示案的精神及範疇的情況下產生本文的各種變化、替代及更改。
109:介電層
115:接合墊通孔跡線
117:接合墊金屬跡線
119:電源網格金屬跡線
121:金屬化層接合墊
201:孔
D1
,D2
,D3
:距離
L1
:重疊長度/長度
S1
:間距
W1
,W2
,W3
:寬度
1-1’:線
Claims (10)
- 一種半導體元件,包括:一金屬化層,在一基板上方;至少兩電源網格線,位於該金屬化層內,其中該兩電源網格線彼此平行且間隔設置;至少兩第一訊號墊,位於該金屬化層內,其中該兩電源網格線分別圍繞該兩第一訊號墊;以及至少兩訊號外部連接,分別電連接至該兩第一訊號墊。
- 如請求項1所述之半導體元件,進一步包括一接合墊通孔跡線,該接合墊通孔跡線與該兩第一訊號墊其中一者及該兩訊號外部連接其中一者實體接觸。
- 如請求項1所述之半導體元件,進一步包括另一半導體元件,該另一半導體元件接合至該兩訊號外部連接。
- 如請求項3所述之半導體元件,其中該半導體元件與該另一半導體元件以一混合接合進行接合。
- 如請求項1所述之半導體元件,其中該兩第一訊號墊藉由一介電質材料與該兩電源網格線分隔。
- 一種半導體元件,包括: 一第一半導體元件的至少兩訊號連接;該第一半導體元件的至少兩通孔,該兩通孔分別與該兩訊號連接實體接觸,並分別與一金屬化層的至少兩第一導電部分實體接觸;以及至少兩電源網格,位於該金屬化層內,其中該兩電源網格彼此平行且間隔設置,該兩電源網格分別包含兩第一單線,且該兩第一單線分別圍繞該兩第一導電部分。
- 如請求項6所述之半導體元件,進一步包括:該兩金屬化層其中一者的一第二導電部分;該兩電源網格其中一者的一第二單線,該第二單線圍繞該第二導電部分,該第二單線與該兩第一單線不同;以及該第一半導體元件的一第二通孔,該第二通孔與該兩金屬化層其中一者的該第二導電部分及一第二外部連接兩者實體接觸。
- 如請求項7所述之半導體元件,其中該兩第一導電部分其中一者及該第二導電部分彼此對齊。
- 如請求項7所述之半導體元件,其中該兩第一導電部分其中一者及該第二導電部分彼此錯位。
- 一種製造半導體元件的方法,該方法包括以下步驟: 在一第一半導體基板上方形成一第一金屬化層,該第一金屬化層包括至少兩電源網格及至少兩訊號連接器,該兩電源網格彼此平行且間隔設置,該兩電源網格分別具有兩第一線,每一該兩第一線在一第一方向上具有一第一寬度,該兩訊號連接器分別由該兩第一線圍繞,每一該兩訊號連接器具有小於該第一方向上的該第一寬度的一第二寬度;以及形成至少兩接合墊金屬跡線,該兩接合墊金屬跡線分別與該兩訊號連接器電連接。
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