TW201603148A - 具有較高密度之積體電路封裝結構以及方法 - Google Patents

具有較高密度之積體電路封裝結構以及方法 Download PDF

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TW201603148A
TW201603148A TW104117093A TW104117093A TW201603148A TW 201603148 A TW201603148 A TW 201603148A TW 104117093 A TW104117093 A TW 104117093A TW 104117093 A TW104117093 A TW 104117093A TW 201603148 A TW201603148 A TW 201603148A
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substrate
component
microelectronic
microelectronic component
attached
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TW104117093A
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TWI613740B (zh
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查爾斯Ｇ 渥奇克
阿爾卡爾古德Ｒ 斯塔拉姆
安德烈 曹
李豐燮
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英凡薩斯公司
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Abstract

本發明揭露一種形成半導體封裝之方法，包含：在基板之第一側上，形成至少一第一通孔，並貼附第一微電子元件之第一側至基板之第一側上，第一微電子元件電性耦接至少一第一通孔中的至少一個。此方法更包含：取得第二微電子元件，其在第一側上具有至少一第二通孔，並將基板之第二側貼附至第二微電子元件之第一側上。第二微電子元件係電性耦接至少一第一通孔中之至少一個。每一連接元件具有貼附至該第二微電子元件上的一第一端以及延伸至該第一微電子元件之第二側外的一第二端。

Description

具有較高密度之積體電路封裝結構以及方法
本發明係關於積體電路(IC)封裝技術，特別是具有高密度堆疊的IC封裝。
電子產業對體積較小且運作速度較快的電子裝置的需求不斷地增加，這些電子裝置必須能夠支持日益複雜以及精密的功能。因此，半導體產業的未來趨勢將朝低成本製作、高效能以及低功率的積體電路(IC)持續發展。迄今，通常是藉由縮小半導體IC的尺寸(例如元件尺寸最小化)，以實現這些目標，從而提昇生產效能以及降低相關成本。然而，按縮小尺寸會導致半導體製程的複雜度增加。因此，半導體IC以及元件的持續改進同時也需要半導體製程以及技術持續發展。
例如，為了盡可能在縮小的區域內增加IC的功能，而引進三維晶片(3D IC)設計。在此設計中，多層的主動電子元件可例如垂直整合於一單一基板內，或藉由使用堆疊式基板整合。在外型尺寸縮小的情況下，3D IC設計可提昇性能(例如由於較短的連接)以及不同類型的功能性(例 如邏輯電路、記憶體、圖像感測器以及MEMS等)。在3D IC的發展中，矽穿孔(TSV)技術係其中重要的方法，其在基板之正面以及背面之間提供導電路徑給垂直堆疊的複數個晶粒(或“晶片”)。然而，使用TSV的堆疊式晶粒亦有許多困難待解決，例如散熱、互連路徑、晶粒位置以及電晶體可靠度等等。
在實施例中，引入矽中介層以解決TSV實作時遇到的困難。不包含任何主動元件的矽中介層可用於形成TSV，因此減少包含TSV的主動晶粒所遇到的問題。此外，設於主動晶粒之間的中介層可用於重新佈線晶粒之間的連接點，例如藉由重新配置在中介層之前側以及背側之間的輸入/輸出(I/O)的數量。
TSV以及矽中介層已成為3D IC技術的關鍵推動因素，在外形尺寸不斷縮小的情況下，仍可在較高的元件以及I/O密度的情況下持續改善系統整合以及頻帶寬度、降低的功率消耗以及提昇的存取次數(例如記憶體區塊)。因此，目前亟需要的是適用於3D IC系統的改善半導體封裝解決方案，以提供高密度I/O配置並維持輕薄設計。
在本發明之實施例中，係提供一種形成半導體封裝之方法，其包含：在基板之第一側上，形成至少一第一通孔；將第一微電子元件之第一側貼附至基板之第一側上，第一微電子元件電性耦接至少一第一通孔中的至少一個；取得一第二微電子元件，此第二微電子元件之第一側上包含至少一第二通孔，且此第二微電子元件具有至少一連接元件，各連接元件 具有第一端，其貼附至第二微電子元件之第一側上；以及將基板之第二側貼附至第二微電子元件之第一側上，第二微電子元件電性耦接至少一第一通孔中的至少一個。在實施例中，各連接元件之第二端係延伸至第一微電子元件之第二側外。
在本發明之實施例中，半導體封裝包含一基板，此基板包含至少一第一通孔，此至少一第一通孔從基板之第一側穿過基板延伸至基板之第二側；一第一微電子元件，係貼附至基板之第一側上以及電性耦接至少一第一通孔中的至少一個；一第二微電子元件，係貼附至基板之第二側上以及電性耦接至少一第一通孔中的至少一個；至少一連接元件，各連接元件具有一第一端以及一第二端，此第一端係貼附至第二微電子元件上，第二端係延伸至第一微電子元件外。
在本發明之實施例中，半導體封裝包含一基板，此基板包含至少一通孔，此至少一通孔從基板之第一側穿過基板延伸至基板之第二側；一第一微電子元件，係貼附至基板之第一側上以及電性耦接至少一通孔中的至少一個；一密封層，係包覆第一微電子元件以及基板。在實施例中，密封層包含擴散於其內的一碳材料，用以增加密封層的導熱性。在實施例中，此半導體封裝更包含：一第二微電子元件，其係貼附至基板之第二側上以及電性耦接至少一通孔中的至少一個；以及至少一連接元件，其具有一第一端以及一第二端，此第一端係貼附至第二微電子元件上，第二端係延伸至第一微電子元件外。在實施例中，至少一連接元件中的至少一個包含一碳材料，用以增加至少一連接元件的導熱性。
100‧‧‧積體電路(IC)組件
102‧‧‧中介層(中介層基板)
104‧‧‧通孔
106‧‧‧重分配層(RDL)
112‧‧‧第一側(頂部)
114‧‧‧第二側(底部)
122‧‧‧微電子元件(ME元件)
124‧‧‧第一側
126‧‧‧第二側
132‧‧‧接觸元件
134‧‧‧底層填料
136‧‧‧密封體
137‧‧‧表面
138‧‧‧載體晶圓
139‧‧‧薄化製程
142‧‧‧重分佈層(RDL)
144‧‧‧接觸元件
146‧‧‧切割線
150‧‧‧第一階(first-level)模組
200‧‧‧積體電路(IC)組件
202‧‧‧微電子元件(ME元件)
204‧‧‧第一側
206‧‧‧第二側(底部)
207‧‧‧通孔
208‧‧‧連接元件
208a‧‧‧連接元件第一端
208b‧‧‧連接元件第二端
208c‧‧‧焊墊
210‧‧‧連接陣列
212‧‧‧底層填料
214‧‧‧密封體
216‧‧‧表面
250‧‧‧第二階(tow-level)模組
250-1‧‧‧第二階模組之一
250-2‧‧‧第二階模組之二
300‧‧‧第四階(fourth-level)模組
302‧‧‧連接件
304‧‧‧連接件
400‧‧‧IC組件
402‧‧‧第(i-2)階模組
404‧‧‧第(i-1)階ME元件
405‧‧‧連接陣列
406‧‧‧第(i-1)階模組
408‧‧‧第i階ME元件
410‧‧‧連接陣列
412‧‧‧切割線
420‧‧‧接觸件
422‧‧‧BVA或矽穿孔(TSV)
424‧‧‧接觸件
426‧‧‧BVA或TSV
450‧‧‧第i階模組
500‧‧‧IC封裝結構
502‧‧‧ME元件
504‧‧‧通孔
506‧‧‧連接陣列
508‧‧‧第一階模組
510‧‧‧第i階模組
512‧‧‧單一晶片
s1‧‧‧第一側
s2‧‧‧第二側
x‧‧‧x方向
y‧‧‧y方向
z‧‧‧z方向
第1圖至第3圖、以及第4A圖與第4B圖為本發明之實施例所製造的積體電路(IC)組件之剖面圖。
第5圖為本發明之實施例之IC組件之元件之剖面圖。
第6圖為本發明之實施例之IC組件之剖面圖。
第7A圖與第7B圖為本發明之實施例之第二階(second-level)模組之剖面圖。
第8A圖與第8B圖為本發明之不同實施例之兩個第二階模組堆疊形成的第四模組之剖面圖。
第9圖為本發明之實施例之各種模組堆疊形成的IC組件之剖面圖。
第10圖為本發明之實施例之IC封裝結構之剖面圖。
第11圖為本發明之實施例之IC封裝之方法之流程示意圖。
第1圖至第3圖以及第4A圖至第4B圖為本發明之實施例製造的積體電路(IC)組件100之剖面圖。請參閱第1圖，IC組件100包含具有一第一側(頂部)112以及一第二側(底部)114之一中介層基板102。在實施例中，中介層係作為中間基板(例如在晶粒或晶粒封裝之間、在印刷電路板以及晶粒之間等)使用，其適用於重新佈線中介層基板102之背側以及前側之間的輸入/輸出(I/O)端，及/或適用於提昇散熱性性以及機械強度，及/或適用於減緩系統的其它元件之間的熱膨脹係數(CTE)的不匹配現象。首 先，選擇具有足夠厚度的中介層基板102，其可簡單處理且在製程中具有足夠散熱性，而可在後續被薄化。在實施例中，中介層基板102可包含一單晶矽(Si)晶圓，此單晶矽晶圓具有大約200毫米或大約300毫米的直徑以及大約650微米或大於650微米的厚度。這些材料以及尺寸僅作為示例，不以此為限。中介層基板102也可包含其它的半導體材料(例如砷化鎵、玻璃、藍寶石、金屬或其它可用的材料)。針對中介層102，其它可用的材料可包含NbTaN以及LiTaN。在實施例中，中介層也可包含主動電路，例如電晶體。
再次參閱第1圖，中介層基板102可包含具有導電性的至少一導電通孔104。如第1圖所示，通孔104可以為“盲孔”，其端接至中介層基板102內部。或者，至少一通孔104可穿過中介層基板102，以形成基板穿孔(through substrate via,TSV)。通孔104可包含或可由銅(Cu)、鎢(W)或任何其它適合的金屬或非金屬導電材料製成。在實施例中，通孔104可使用微影製程、蝕刻製程以及填充/沉積製程形成。微影製程可包含在中介層基板102之第一側112上，形成一光阻層(圖中未顯示)，以及包含圖案化光阻層，以定義通孔104之位置。接著，可針對通孔104執行蝕刻製程，其使用蝕刻光阻層作為蝕刻光罩，以在中介層基板102上形成至少一孔洞。蝕刻製程可包含乾式蝕刻，例如反應式離子蝕刻(RIE)製程。通孔104可包含垂直、傾斜或任何其他型態。接著，導電材料可沈積至孔洞內，以形成通孔104。如果須要電性絕緣，可在導電材料以及孔洞之表面之間形成介電質。如果須提昇導電材料與孔洞表面之間的黏著性以及阻隔兩者之間的相互擴散，可在兩者之間形成障蔽層，其為本領域所熟知之技術。通孔可例如藉由電鍍或其它技術形成。
請再次參閱第1圖，在中介層基板102之第一側(頂部)112上，形成第一重分配層(RDL)106。在實施例中，第一RDL 106包含複數個互連線(圖中未顯示)，這些互連線係藉由RDL之介電質(圖中未顯示)使彼此絕緣以及與中介層基板102絕緣。在中介層之頂部上，RDL提供接觸墊(圖中未顯示)。如所需要的，RDL之互連線係透過在中介層基板102上的接觸墊以及通孔104相互連接；互連線可將複數個接觸墊相互連接，及/或將複數個接觸墊與至少一通孔104相連接，或可將複數個通孔104相互連接。在本文描述的各種實施方式中，中介層基板102以及RDL(包含下述的第一RDL 106或其它RDL層)也可包含電晶體、電阻、電容以及其他元件(圖中未顯示)。應當理解的是，第1圖僅為示例而非為限制，視需要第一RDL 106亦可省略。
請參閱第2圖，中介層基板102係為上下顛倒的，第二側(底部)114朝上，而第一側(頂部)112朝下。在實施例中，至少一第一微電子(ME)元件122(例如晶片(亦稱為晶粒)或其它可能的電子組件或封裝)係貼附至中介層基板102之第一側112上。例如，ME元件122之電路可耦接通孔104。ME元件122可包含記憶體電路、邏輯電路、控制電路及/或其他任何型態的電路。各ME元件122具有第一側124以及第二側126。如第2圖所示，各ME元件122之第一側124係貼附至第一RDL 106，其係形成於中介層102之第一側112上。在另一示例中，至少一ME元件122之第一側124直接地貼附至中介層102之第一側112上，而不需使用第一RDL106。在示例中，至少一通孔104可提供電性連接及/或導熱路徑，以有助於ME元件或其它熱感測元件散熱(例如通孔104亦可不具電性功能)。
請再次參閱第2圖，為了貼附ME元件122之第一側124至中介層102之第一側112上，在第一RDL 106上，可形成至少一接觸元件132(例如焊球)。接觸元件132亦可包含導電物、異方性導電膠或其它型態的連接物。如下述之一示例，複數個接觸元件132係貼附至其它結構上。在實施例中，複數個接觸元件132並非個別的元件(例如若藉由熱壓進行貼附時)。如果複數個接觸元件132可彼此分離，其可貼附至第一RDL 106所提供的至少一接觸墊(圖中未顯示)上。接觸元件132可包含金屬，例如錫(Sn)、銦(In)、金(Au)或金屬合金，在此僅舉例說明，不以此為限。接觸元件132可具有任何其它適合的外形，例如長形接頭及/或一串堆疊式導電塊。
請再次參閱第2圖，在第一RDL 106以及各ME元件122之第一側124之間，可形成底層填料134。在示例中，底層填料134可在ME元件122貼附之前或之後形成。底層填料134可包含具有二氧化矽或其它粒子的環氧樹脂或包含其它適合的高分子材料。底層填料134可保護ME元件及/或電性連接處(例如接觸元件132)不被有濕氣等污染物、紫外線、α粒子以及其它可能的有害物質損壞。底層填料134亦可增強RDL以及ME元件之間的貼附。在實施例中，底層填料134亦可有助於ME元件122散熱。
請參閱第3圖，在實施例中，在ME元件122之第二側126上，藉由模壓或其它技術形成密封體136。密封體136包含任何適合的材料，例如具有二氧化矽或其它粒子的環氧樹脂，或其它適合的高分子材料。在實施例中，密封體136包含擴散於其內的碳材料，例如石墨，用以增加密封體136之導熱性。
選擇性地，載體晶圓138可貼附至密封體136之表面137上。 在製程中，載體晶圓138可作為支撐晶圓(support wafer)使用，並可在製程結束後移除。例如，當IC組件100具有足以承受製程處理的機械強度時，載體晶圓138可省略。
如第3圖所示，如果第1圖中的至少一原始通孔104為“盲孔”，中介層基板102接著從第二側114被薄化，以暴露通孔104之埋設端，因此通孔104從盲孔轉為TSV。背面薄化製程139可包含反應式離子蝕刻(RIE)及/或其它乾式蝕刻製程及/或濕式蝕刻及/或研磨及/或精研及/或化學機械拋光(CMP)及/或其它製程。如第3圖所示，在薄化製程139之後，TSV 104以及中介層基板102可形成平坦表面。在其它實施例中，TSV 104係凸出於中介層外。請見公告日2003年10月28日、專利號6,639,303、以及發明人Siniaguine的美國專利，藉由引用將其內容併入本文。
在另一實施例中，在第1圖所示之階段並未提供通孔104，但在第3圖中，中介層基板經由薄化後顯露出通孔104。在其它實施例中，在第1圖所示之階段已顯露出通孔104，而在第3圖中，導電材料係填充此通孔104。介電層或其它層可部分地形成於第1圖以及第3圖所示之階段中的通孔104內。
請參閱第4A圖，在中介層102之第二側114上，形成第二RDL 142。RDL 142係在中介層之一側114上提供接觸墊(圖中未顯示)。RDL之互連線依需求在中介層基板102上的接觸墊以及通孔104互連；互連線可將複數個接觸墊相互連接，及/或將複數個接觸墊以及至少一通孔104相連接，或可將複數個通孔104相互連接。在實施例中，中介層基板102、RDL 106以及RDL 142可包含電晶體、電阻、電容及/或其他元件(圖中未顯示)。形 成RDL 142的元件以及方法基本上可相似於形成RDL 106的元件以及方法。在實施例中，省略RDL142。
在第二RDL 142上，提供至少一接觸元件144。這些接觸元件144可以為個別的元件，例如焊球，第4A圖為一可能的實施方式，其僅用以指出接觸元件144貼附至其它結構上。如果這些接觸元件144為個別的元件，其可貼附至第二RDL 142所提供的至少一接觸墊(圖中未顯示)上。接觸元件144可包含接合金屬，例如錫(Sn)、銦(In)、金(Au)、金屬合金或可固化材料。如第4A圖所示，接觸元件144例如為焊球，應當理解的是，其僅作為示例，非用以限制本發明。接觸元件144可具有任何適合的外形，例如長形的連接件(例如銅柱)及/或一串堆疊的導電塊。接觸元件144可基本上相似於第2圖所繪示的接觸元件132。
請再次參閱第4A圖，IC組件100接著沿切割線146進行切割，以形成複數個第一階(first-level)模組150。在切割之前或之後，可移除載體晶圓134。如第4B圖所示，第一階模組150包含堆疊於中介層102上的ME元件122，中介層102包含至少一TSV104。(值得注意的是，我們所使用的符號102係指中介層基板102以及全部的中介層，例如具有RDL的基板。)在實施例中，TSV 104係耦接ME元件122，以在ME元件122以及IC封裝內的其它元件之間提供電性連接及/或導熱，以有助於ME元件122散熱。
第5圖至第6圖為本發明之實施例之IC組件200之剖面圖。在本實施例中，IC組件200包含複數個ME元件，例如彼此堆疊的兩個ME元件。如下所述，IC組件200可用於製造至少一第二階(tow-level)模組250(第7A圖以及第7B圖)。IC組件200以及第二階模組250僅作為示例，不以此為限。 IC組件可包含適當數量的ME元件，這些ME元件彼此堆疊在一起。
請參閱第5圖，第二ME元件202可包含晶圓或晶片(“晶粒”)，晶圓或晶片包含半導體積體電路，此半導體積體電路包含記憶電路、邏輯電路或控制電路(例如電腦處理器)或其它型態的電路。第二ME元件202可或不可基本上相似於ME元件122，例如二ME元件可執行相同或不同的功能。第二ME元件202可包含相異於第一ME元件122之基板的一基板。
請再次參閱第5圖，ME元件202具有第一側(頂部)204以及第二側(底部)206。ME元件202包含至少一導電通孔207。在實施例中，如第5圖所示，通孔207為基板穿孔(TSV)207，其從上方處第一側204穿過ME元件202而延伸至底側206。TSV 207可藉由相同於上述的中介層102內的TSV 104的製程製造。在其他實施例中，通孔207為”盲孔”，其從側204進行延伸並端接至ME元件202內部。
此外，ME元件202可包含一基板(例如半導體、玻璃及/或其它材料)，此基板之頂部及/或底部上具有一RDL(圖中未顯示)；形成於基板上的通孔207為盲孔或為貫穿基板的TSV 207；複數個通孔207係與ME元件202之頂部及/或底部的複數個接觸墊相連接，複數個通孔207可選擇性地相互連接，若是需要，可藉由RDL互連線連接。
如第5圖所示，在第二ME元件202之第一側204上，形成至少一連接元件208。在實施例中，各連接元件208包含相反的第一端(例如基部)208a以及第二端(例如頂端)208b，此第一端(例如基部)208a係貼附至ME元件202上。連接元件208可為或不為垂直的。第一端208a的寬度可增 加，以在第二ME元件202之第一側204上提供焊墊208c。焊墊208c可由銅、鎳、鋁、錫、鈀、其它適合的導電材料或其組合製成。在實施例中，連接元件208可包含導電材料，例如銅、鎳、鋁、錫、鈀或其它適合的導電材料，以在ME元件202以及其它元件之間提供電性導通。在實施例中，連接元件208可包含碳材料，例如石墨，用以增加導熱性以及有助於第二ME元件202散熱。在實施例中，連接元件208可排列成連接陣列210。連接陣列210可形成於第一階模組150的周圍區域，以圍繞第一階模組150，如下所述，此第一階模組150係待貼附至第二ME元件202上。連接元件208可以為接合至上述的ME元件202的導線，例如San Jose,CA2的Invensas公司在2013年5月公布的適用於行動系統的InvensasTM高校能BVA PoP封裝，透過引用將其內容併入本文。請見公告日2013年12月31日、專利號US8,618,659以及發明人為Sato等人的美國專利，透過引用將其併入本文。
請參閱第6圖，至少一第一階模組150係貼附至第二ME元件202之第一側204上。在實施例中，第二ME元件202之通孔207可耦接中介層102之通孔104。在實施例中，如第6圖所示，在中介層基板102之第二側114上，形成電性耦接第二ME元件202之通孔207以及中介層102的第二RDL 142。RDL 142係貼附至位於第二ME元件202上的接觸元件144上。在其他實施例中，中介層102可直接貼附至第二ME元件202，而不使用第二RDL 142。在將第一階模組150貼附至第二ME元件202上之前或之後，可在第二RDL142以及第二ME元件202之間形成底層填料212。底層填料212可由相同於上述的底層填料134的材料製成，並可具有相同於底層填料134的功能。
在第6圖所示之實施例中，連接陣列210形成於第一階模組 150的周圍區域，以部分地或完全地圍繞第一階模組150，此第一階模組150貼附至第二ME元件202上。在實施例中，導電元件208可包含焊墊、導電塊(例如焊球)、由San Jose,CA的Invensas公司提出的Bond Via ArrayTM(BVA)技術或其它任何適合的元件。
請再次參閱第6圖，可例如藉由模壓或相同於上述用於密封體136的技術，以在第二ME元件202之第一側204上形成密封體214，此密封體214可具有相同於密封體136的功能。在實施例中，連接元件208之第二端208b凸出於密封體214之表面216外。如第6圖所示，凸出端208b可延伸至ME元件122外。凸出端208b可用於連接在IC封裝內的其它元件。凸出端208b可提供電性導通及/或導熱。
在實施例中，載體晶圓(圖中未顯示)可貼附至ME元件之底部206上，以在製程期間提供支撐功能，而在製程結束之後，載體晶圓可從ME元件之底部206上移除。載體晶圓可選擇性使用。
請再次參閱第6圖，IC組件200接著沿著切割線216進行切割，以形成至少一第二階模組250。各第二階模組250包含ME元件122以及第二ME元件202，此ME元件122堆疊於中介層102之第一側112上，第二ME元件202堆疊於中介層102之第二側114上。中介層102包含至少一TSV 104。第二ME元件202亦可包含至少一TSV 207。在實施例中，TSV 104、TSV 207以及連接元件208/連接陣列210中的至少一個可在第二階模組250中提供電性連接及/或導熱。
第7A圖及第7B圖為本發明之實施例之第二階模組250。第7A圖及第7B圖之結構相似，但第7B圖中的中介層上不具有RDL。第二階模 組250包含中介層102、ME元件122以及第二ME元件202，此ME元件122設於中介層102之第一側112上，此第二ME元件202設於中介層102之第二側114上。中介層102、ME元件122以及第二ME元件202可包含至少一TSV(例如TSV 104、TSV 216或TSV 207)。在第二ME元件上，亦可形成連接陣列210(例如BVA)，用於將第二ME元件與其它元件(圖中未顯示)相連接。如第7A圖以及第7B圖所示，連接陣列210包含延伸至ME元件122外的凸出端。TSV以及連接陣列210可用於電性導通及/或導熱。在實施例中，如第7A圖所示，在第一側112及/或第二側114上，可形成RDL(例如RDL 106及/或RDL 142)。在實施例中，如第7A圖所示，至少一接觸元件(例如焊球)以及底層填料可用於將ME元件122及/或第二ME元件202貼附至中介層102上。第二階模組250亦可藉由模壓或其它製程被包覆成另一密封材料(圖中未顯示)。
第8A圖至第8B圖為兩個第二階模組250(例如250-1以及250-2)堆疊形成的第四階(fourth-level)模組300之剖面圖。在第8A圖中，模組250-1之底部(例如第二側)貼附至模組250-2之底部(例如第二側)上：第二階模組250-1與250-2之第二ME元件202之第二側206可使用連接件302將彼此相互結合。各連接件302可包含至少一連接元件(例如焊球)或其它型態的連接件，這些連接件係貼附至在第二階模組上的至少一焊墊上。(如果使用熱壓，連接件302亦可為簡單的示意圖，而非分離的物理元件。)
在第8B圖中，模組250-1之底部貼附至模組250-2之頂部上：模組250-1之第二ME元件202之第二側(底部)206藉由連接件304貼附至模組250-2之頂部上，亦即貼附至模組250-2之第一ME元件122之第二側126上，此連接件304可作為連接件302。
第9圖為本發明之一實施例之組件400之剖面圖。可使用基本上相似於第1圖至第6圖、第7A圖至第7B圖以及第8A圖至8B圖中所述的製程，從第1階至第i階依序堆疊數量i的模組，以形成IC組件400。例如，第(i-2)階模組402可貼附至第(i-1)階ME元件404上，以形成第(i-1)階模組406。第(i-2)階模組402可包含數量i-2的ME元件，這些ME元件相互結合，並可藉由至少一中介層相互分離。第(i-2)階模組402所包含的各ME元件以及各中介層可包含至少一TSV。第(i-2)階模組402可透過接觸件420(例如焊球、BVA或TSV)貼附至第(i-1)階ME元件404上。第(i-1)階ME元件404可包含TSV 422或BVA 422。接觸件420可耦接第(i-1)階ME元件404之TSV 422或BVA 422。至少一連接陣列405以及第(i-2)階模組402可依序貼附至第(i-1)階ME元件404上，並與第(i-1)階ME元件404包覆(例如模壓)在一起，以形成第(i-1)階模組406。
請再次參閱第9圖，在第i階ME元件408上，可形成基本上相似於第6圖中所述的連接陣列210的連接陣列410。第(i-1)階模組406可貼附至第i階ME元件408上，並與其模壓形成IC組件400，其包含至少一第i階模組450。如第9圖所示，第(i-2)階模組402可藉由接觸件424(例如焊球、BVA或TSV)貼附至第i階ME元件408上。第i階ME元件408可包含TSV 426或BVA 426。接觸件424可耦接第i階ME元件408之TSV 426或BVA 426。IC組件400可沿切割線412進行切割，以形成至少一第i階模組450。
如第9圖所示，第i階模組450可藉由沿Z方向依序堆疊其它模組而形成，各階的中介層及/或ME元件可沿X-Y平面設置。第i階模組450之ME元件以及中介層可包含至少一TSV(例如TSV 422及/或TSV 426)，用以 沿Z方向提供電性導通及/或導熱。連接陣列(例如連接陣列405或連接陣列410)亦可沿Z方向提供電性導通及/或導熱。在實施例中，第i階模組450所包含的至少一中介層可包含至少一碳材料，例如石墨，用以在X-Y平面上提昇導熱性。
第10圖為本發明之實施例之IC封裝結構500之剖面圖。IC封裝結構500可包含一混合堆疊組件。IC封裝結構500可包含ME元件502，此ME元件502可包含具有半導體積體電路的晶片(或”晶粒”)或晶圓，其可具有任何類型的功能，例如記憶體電路、邏輯電路、控制電路及/或其它類型。ME元件502可包含具有至少一通孔504的一基板。通孔504可以為盲孔或基板穿孔(TSV)，其製造方式請見中介層基板102上的TSV104的相關說明。通孔504可在ME元件502上方、下方或內部的多個電路之間提供電性連接。通孔504亦可提供導熱功能，以有助於電路散熱。
請參閱第10圖，在ME元件502上，形成基本上相似於第6圖中所述的連接陣列210的至少一連接陣列506，此至少一連接陣列506可例如為BVA。BVA 506可在ME元件502以及IC封裝結構500內的至少一其它元件之間提供電性連接。BVA 506亦可提供導熱功能，以有助於ME502散熱。
各種IC元件從上方或下方貼附至ME元件502上，以形成IC封裝結構500。因此，第一階模組508或其它型態模組可貼附至以及電性耦接BVA 506上。在示例中，第i階模組510可貼附至ME元件502上，其中i=1,2…或n。第i階模組510可包含數量i的ME元件，其與第9圖中的第i階模組450的至少一中介層相互堆疊。在示例中，IC封裝結構500亦可包含單一晶片512。單一晶片512可包含一半導體積體電路，用以執行記憶體功能、邏輯功能、 控制功能或其它處理功能中的至少一個。如第10圖所示，單一晶片512可堆疊於第i階模組510上。單一晶片512亦可堆疊於IC封裝結構500的其它其任意元件上。製造IC封裝結構500的貼附以及堆疊製程可包含任何適合的封裝技術。例如，焊球、接觸墊、底層填料以及密封體可用於連接以及模壓在IC封裝結構500內的各種元件。IC封裝結構500亦可包含至少一RDL。
在第10圖的立體系統中，IC封裝結構500可沿Z方向堆疊，各階的中介層及/或ME元件可沿X-Y平面設置。TSV沿Z方向形成於至少一ME元件上，及/或中介層可沿Z方向在IC封裝結構500上提供電性導通及/或導熱功能。連接陣列亦可沿Z方向在IC封裝結構500上提供電性導通及/或導熱功能。在實施例中，至少一中介層可包含至少一碳材料，例如石墨，用以在IC封裝結構500中的X-Y平面上提昇導熱性。
第11圖為本發明之實施例之IC封裝之方法600之流程示意圖。應當理解的是，在第11圖之流程示意圖中，方法600僅為示例，不以此為限。在方法600之前、期間以及之後，亦可增添任何額外的製程。
此方法600之開始步驟602，係在一基板(例如中介層102)之一第一側(例如第一側112)上形成至少一通孔(例如通孔104)。通孔可以為”盲孔”，其端接至基板內部。或者，通孔可以為基板穿孔(TSV)，其從中介層基板之第一側穿過中介層基板延伸至中介層基板之第二側(例如基板之第二側114)。通孔之形成，可藉由微影以及蝕刻或雷射鑽孔製程形成孔洞，接著將導體填充至此孔洞內，並接著薄化基板之背面，以顯露出此導體。
方法600之步驟604，係將第一微電子元件(ME)(例如ME 元件122)之第一側(例如第一側124)貼附至基板之第一側上。形成於基板上的通孔可耦接第一ME元件。至少一接觸元件，例如焊球，可用於連接基板以及第一ME元件。在基板以及第一ME元件之間，可提供一底層填料，並可藉由模壓形成一密封體，用以包覆第一ME元件以及選擇性基板。
方法600之一選擇性製程606，係從基板之第二側薄化基板。在實施例中，可藉由薄化製程暴露”盲孔”之埋設端，以形成TSV。背面薄化技術可包含濕式及/或乾式蝕刻(例如反應式離子蝕刻)及/或機械研磨或精研或碾碎及/或化學機械拋光(CMP)。
方法600之步驟608，係取得第二ME元件(例如ME元件202)，其可包含至少一通孔(例如通孔207)。在第二ME元件上的通孔可包含TSV。或者，在第二ME元件上的通孔可包含“盲孔”。
方法600之步驟610，係貼附至少一連接元件(例如連接元件208/連接陣列210)至第二ME元件之第一側(例如第一側204)上。在實施例中，各連接元件垂直延伸至第二ME元件之第一端(例如基部)以及第二端(例如頂部)之間。在實施例中，連接元件可包含導電材料，以在第二ME元件以及其他元件之間提供電性導通。在實施例中，連接元件可包含碳材料，例如石墨，用以增加導熱性，以有助於第二ME元件散熱。在實施例中，至少一連接元件可呈連接陣列設置。連接陣列可形成於第一階模組之周圍區域，以圍繞第一階模組，此第一階模組待貼附至第二ME元件上。
方法600之一步驟612，係貼附第二ME元件之第一側至基板之第二側上。連接元件/連接陣列可延伸至第一ME元件之第二側(例如第二側126)外。
方法600之一選擇性步驟614，係從第二ME元件之第二側(例如第二側206)，對第二ME元件執行薄化製程。在實施例中，在薄化製程之後，可暴露“盲孔”之埋設端，以在第二ME元件上形成TSV。背面薄化製程可包含濕式蝕刻製程、乾式蝕刻製程(例如反應式離子蝕刻)及/或化學機械拋光(CMP)製程。
方法600之一製程616，係貼附至少一第三ME元件至IC連接元件上。至少一第三ME元件可包含一單一晶片、一第一階模組及/或使用任何適合的封裝技術堆疊的一多階模組。例如，至少一第三ME元件可使用至少一接觸墊(可能具有焊球)以及底層填料貼附至IC封裝結構上。
發明並不限於上述範例。其他實施例與變化例都在本發明的範圍內，如同由所附申請專利範圍所界定的。
100‧‧‧積體電路(IC)組件
102‧‧‧中介層(中介層基板)
104‧‧‧通孔
106‧‧‧重分配層(RDL)
112‧‧‧第一側(頂部)
114‧‧‧第二側(底部)
s1‧‧‧第一側
s2‧‧‧第二側

Claims (20)

  1. 一種形成一半導體封裝之方法，包含：在一基板之一第一側上，形成至少一第一通孔；貼附一第一微電子元件之一第一側至該基板之該第一側上，該第一微電子元件係電性耦接該至少一第一通孔中的至少一個；取得一第二微電子元件，該第二微電子元件之一第一側上包含至少一第二通孔，該第二微電子元件具有至少一連接元件，各該連接元件具有貼附至該第二微電子元件之一第一側上的一第一端；以及貼附該基板之一第二側至該第二微電子元件之該第一側上，該第二微電子元件係電性耦接該至少一第一通孔中之至少一個，其中各該至少一連接元件之一第二端係延伸至該第一微電子元件之一第二側外。
  2. 如申請專利範圍第1項所述之方法，其中各該第一通孔從該基板之該第一側延伸至該基板之該第二側。
  3. 如申請專利範圍第1項所述之方法，其中各該第一通孔端接至該基板內部，以及其中該方法更包含：在取得該第二微電子元件之前，從該基板之該第二側薄化該基板，以顯露出在該基板之該第二側上的該至少一第一通孔。
  4. 如申請專利範圍第1項所述之方法，其中各該第二通孔端接至該第二微電子元件內部，以及其中該方法更包含：在貼附該第二微電子元件之該第一側至該基板之該第二側上之後，從該第二微電子元件之一第二側薄化該第二微電子元件，以顯露出在該第二微電子元件之該第二側上的該至少一第二通孔。
  5. 如申請專利範圍第1項所述之方法，更包含：貼附該至少一連接元件中之至少一個之該第二端至一第三微電子元件上。
  6. 如申請專利範圍第1項所述之方法，更包含：在該基板之該第一側上，形成一重分配層(RDL)，其中貼附該第一微電子元件之該第一側至該基板之該第一側上的步驟包含將該第一微電子元件耦接該RDL。
  7. 如申請專利範圍第1項所述之方法，其中貼附該第一微電子元件之該第一側至該基板之該第一側上的步驟包含：在該基板之該第一側上，形成至少一接觸元件；在該基板之該第一側上，形成一底層填料；貼附該第一微電子元件之該第一側至該底層填料上；以及 透過一密封材料包覆該第一微電子元件以及該基板。
  8. 如申請專利範圍第1項所述之方法，其中貼附該第一微電子元件之該第一側至該基板之該第一側上的步驟包含：在該基板之該第一側上，形成至少一接觸元件；貼附該第一微電子元件之該第一側至該至少一接觸元件上；以及在該基板之該第一側以及該第一微電子元件之該第一側之間，形成一底層填料。
  9. 如申請專利範圍第1項所述之方法，其中該至少一連接元件貼附至該第二微電子元件之該第一側之一第一區域上，以及其中該基板之該第二側貼附至一第二區域上，該第二區域相異於該第二微電子元件之該第一側之該第一區域。
  10. 一種半導體封裝，包含：一基板，包含至少一第一通孔，該至少一第一通孔從該基板之一第一側延伸穿過該基板至該基板之一第二側；一第一微電子元件，貼附至該基板之該第一側上，電性耦接該至少一第一通孔中之至少一個；一第二微電子元件，貼附至該基板之該第二側上，電性耦接該至少一第一通孔中的至少一個；以及至少一連接元件，各該至少一連接元件具有貼附至該第二微電子元件上 的一第一端以及延伸過該第一微電子元件外的一第二端。
  11. 如申請專利範圍第10項所述之半導體封裝，其中該至少一第一通孔電性耦接該第一微電子元件。
  12. 如申請專利範圍第10項所述之半導體封裝，更包含：一第三微電子元件，貼附至該至少一連接元件中之至少一個之該第二端上。
  13. 如申請專利範圍第10項所述之半導體封裝，其中該第二微電子元件包含延伸穿過該第二微電子元件的至少一第二通孔。
  14. 如申請專利範圍第13項所述之半導體封裝，其中該至少一第二通孔電性耦接該至少一第一通孔。
  15. 如申請專利範圍第13項所述之半導體封裝，其中該至少一第二通孔中之至少一個具有導熱性且熱耦接該至少一第一通孔，以使該第二微電子元件可導熱至該基板。
  16. 如申請專利範圍第10項所述之半導體封裝，其中該連接元件中之至少一個具有導熱性。
  17. 如申請專利範圍第10項所述之半導體封裝，其中該基板包含一石墨，用 以增加該基板之導熱性。
  18. 一種半導體封裝，包含：一基板，包含至少一通孔，該至少一通孔從該基板之一第一側延伸穿過該基板至該基板之一第二側；一第一微電子元件，貼附至該基板之該第一側上，電性耦接該至少一通孔中之至少一個；以及一密封層，包覆該第一微電子元件以及該基板，其中該密封層包含在其內擴散之一碳材料，用以增加該密封層之導熱性。
  19. 如申請專利範圍第18項所述之半導體封裝，更包含：一第二微電子元件，係貼附至該基板之第二側上且電性耦接該至少一通孔中之至少一個；以及至少一連接元件，各該連接元件具有貼附至該第二微電子元件上的一第一端以及延伸過該第一微電子元件外的一第二端，其中該至少一連接元件中之至少一個包含一碳材料，用以增加該至少一連接元件中之該至少一個之導熱性。
  20. 如申請專利範圍第18項所述之半導體封裝，其中該至少一通孔中之至少一個具有導熱性且熱耦接該第一微電子元件，以使該基板可導熱至該第一微電子元件。
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